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[/] [g729a_codec/] [trunk/] [VHDL/] [G729A_asip_adder.vhd] - Blame information for rev 2

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-----------------------------------------------------------------
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--                                                             --
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-----------------------------------------------------------------
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--                                                             --
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-- Copyright (C) 2013 Stefano Tonello                          --
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--                                                             --
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-- This source file may be used and distributed without        --
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-- restriction provided that this copyright statement is not   --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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--                                                             --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
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-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
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-- POSSIBILITY OF SUCH DAMAGE.                                 --
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--                                                             --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- adder with carry-in
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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use WORK.G729A_ASIP_PKG.all;
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use WORK.G729A_ASIP_BASIC_PKG.all;
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use WORK.G729A_ASIP_ARITH_PKG.all;
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entity G729A_ASIP_ADDER is
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  generic(
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    WIDTH : integer := 16
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  );
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  port(
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    OPA_i : in signed(WIDTH-1 downto 0);
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    OPB_i : in signed(WIDTH-1 downto 0);
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    CI_i : in std_logic;
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    SUM_o : out signed(WIDTH-1 downto 0)
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  );
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end G729A_ASIP_ADDER;
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architecture ARC of G729A_ASIP_ADDER is
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  signal TMP : signed(WIDTH downto 0);
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begin
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  -- this encoding forces inferring of an adder with carry-in,
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  -- rather than two cascaded adders.
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  TMP <= (OPA_i & '1') + (OPB_i & CI_i);
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  SUM_o <= TMP(WIDTH downto 1);
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end ARC;

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