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[/] [g729a_codec/] [trunk/] [VHDL/] [SELF_TEST/] [G729A_codec_selftest.vhd] - Blame information for rev 3

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-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2013 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- G.729a Codec self-test module
---------------------------------------------------------------
 
---------------------------------------------------------------
-- Notes:
-- This module performs codec self-test (decoding+encoding on
-- a fixed set of data packets, comparing expected outputs with
-- actual ones). Self-test results are flagged by DONE and PASS
-- output signals (DONE = '1' => test is complete, PASS = '1'
-- => no error has been detected).
-- This module only needs clock and reset inputs: all input 
-- data are stored in ROM.
-- This module is synthesizable.
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
 
library work;
use work.G729A_ASIP_PKG.all;
use work.G729A_ASIP_CFG_PKG.all;
use work.G729A_CODEC_INTF_PKG.all;
 
entity G729A_CODEC_SELFTEST is
  port(
    CLK_i : in std_logic; -- clock
    RST_i : in std_logic; -- reset
 
    DONE_o : out std_logic; -- test complete
    PASS_o : out std_logic -- test pass
  );
end G729A_CODEC_SELFTEST;
 
architecture ARC of G729A_CODEC_SELFTEST is
 
  -- number of packets to encode/decode (do not modify!)
  constant MAX_CNT : natural := 5;
 
  -- use ROM models with MIF file.
  constant USE_ROM_MIF : std_logic := '0';
 
  -- Input/Output data ROM word count
  constant ST_MEM_SIZE : natural := MAX_CNT * (ENCODED_LEN + DECODED_LEN);
 
  -- Control FSM state type
  type XS_T is (
    XS_IDLE,
    XS_INIT,
    XS_RUN,
    XS_STOP
  );
 
  -- Write FSM state type
  type WS_T is (
    WS_IDLE,
    WS_WRITE,
    WS_WAIT
  );
 
  -- Read FSM state type
  type RS_T is (
    RS_IDLE,
    RS_READ,
    RS_WAIT
  );
 
  component G729A_CODEC_SDP is
    generic(
      -- synthesis translate_off
      ST_FILE : string;
      WB_FILE : string;
      -- synthesis translate_on
      REGISTER_INPUTS : std_logic := '0';
      REGISTER_OUTPUTS : std_logic := '0';
      USE_ROM_MIF : std_logic := '0';
      SIMULATION_ONLY : std_logic := '1'
    );
    port(
      CLK_i : in std_logic; -- clock
      RST_i : in std_logic; -- reset
      STRT_i : in std_logic; -- start
      OPS_i : in std_logic_vector(3-1 downto 0);
      RE_i : in std_logic; -- read-enable
      WE_i : in std_logic; -- write-enable
      DI_i : in std_logic_vector(SDLEN-1 downto 0); -- DMA data-in
 
      BSY_o : out std_logic; -- busy
      DMAE_o : out std_logic; -- DMA enable
      STS_o : out std_logic_vector(3-1 downto 0);
      DV_o : out std_logic; -- data-out valid
      DO_o : out std_logic_vector(SDLEN-1 downto 0) -- DMA data-out
    );
  end component;
 
  component G729A_ASIP_ROM_MIF is
    generic(
      WCOUNT : natural := 256;
      DATA_WIDTH : natural := 8;
      ADDR_WIDTH : natural := 8;
      ROM_INIT_FILE : string := "NONE"
    );
    port(
      CLK_i : in std_logic;
      A_i : in unsigned(ADDR_WIDTH-1 downto 0);
 
      Q_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
  end component;
 
  component G729A_ASIP_STI_ROM is
    generic(
      WCOUNT : natural := 425;
      DATA_WIDTH : natural := 16;
      ADDR_WIDTH : natural := 9
    );
    port(
      CLK_i : in std_logic;
      A_i : in unsigned(ADDR_WIDTH-1 downto 0);
 
      Q_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
  end component;
 
  component G729A_ASIP_STO_ROM is
    generic(
      WCOUNT : natural := 425;
      DATA_WIDTH : natural := 16;
      ADDR_WIDTH : natural := 9
    );
    port(
      CLK_i : in std_logic;
      A_i : in unsigned(ADDR_WIDTH-1 downto 0);
 
      Q_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
  end component;
 
  signal XS,XS_q : XS_T;
  signal STRT : std_logic;
  signal OPS : std_logic_vector(3-1 downto 0);
  signal RE : std_logic;
  signal WE : std_logic;
  signal SRST : std_logic := '0'; -- inactive!
  signal CDC_BSY : std_logic;
  signal CDC_DV : std_logic;
  signal CDC_DO : std_logic_vector(SDLEN-1 downto 0);
  signal CDC_STS : std_logic_vector(3-1 downto 0);
  signal PKT_CNT_q : natural range 0 to MAX_CNT;
  signal DONE,DONE_q : std_logic;
  signal PASS,PASS_q : std_logic;
  signal WS,WS_q : WS_T;
  signal RS,RS_q : RS_T;
  signal WRITE_OP : std_logic;
  signal READ_OP : std_logic;
  signal WRITEF,WRITEF_q,WRITEF_q2 : std_logic;
  signal READF,READF_q : std_logic;
  signal CNT_q : natural range 0 to DECODED_LEN-1;
  signal CNT_INIT : natural range 0 to DECODED_LEN-1;
  signal CNT_RST_R,CNT_RST_W : std_logic;
  signal ERR : std_logic;
  signal ERR_CNT_q : natural range 0 to ST_MEM_SIZE-1;
  signal STI_RE : std_logic;
  signal STI_ADR : unsigned(log2(ST_MEM_SIZE)-1 downto 0);
  signal STI_DO : std_logic_vector(SDLEN-1 downto 0);
  signal STI_CNT_q : natural range 0 to ST_MEM_SIZE-1;
  signal STO_RE : std_logic;
  signal STO_ADR : unsigned(log2(ST_MEM_SIZE)-1 downto 0);
  signal STO_DO : std_logic_vector(SDLEN-1 downto 0);
  signal STO_CNT_q : natural range 0 to ST_MEM_SIZE-1;
 
begin
 
  ---------------------------------------------------
  -- Test control FSM
  ---------------------------------------------------
 
  -- This FSM performs codec initialization and then
  -- run decoding+encoding on MAX_CNT data packets.
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        DONE_q <= '0';
        XS_q <= XS_IDLE;
      else
        DONE_q <= DONE;
        XS_q <= XS;
      end if;
    end if;
  end process;
 
  process(XS_q,CDC_BSY,PKT_CNT_q)
  begin
    STRT <= '0';
    OPS <= NOP;
    DONE <= '0';
    case XS_q is
 
         -- do nothing while reset is on
      when XS_IDLE =>
        STRT <= '1'; -- assert codec start
        OPS <= INIT; -- select codec operation
        XS <= XS_INIT;
 
         -- initialize codec
      when XS_INIT =>
        if(CDC_BSY = '0') then
          STRT <= '1'; -- assert codec start
          OPS <= RUNF; -- select codec operation
          XS <= XS_RUN;
        else
          XS <= XS_INIT;
        end if;
 
         -- run decoding+encoding
      when XS_RUN =>
        if(CDC_BSY = '0') then
          if(PKT_CNT_q > 0) then
            STRT <= '1'; -- assert codec start
            OPS <= RUNF; -- select codec operation
            XS <= XS_RUN;
          else
            XS <= XS_STOP;
          end if;
        else
          XS <= XS_RUN;
        end if;
 
      -- forever stop...
      when XS_STOP =>
        DONE <= '1';
        XS <= XS_STOP;
 
      when others =>
        XS <= XS_IDLE;
 
    end case;
  end process;
 
  ---------------------------------------------------
  -- decoded/encoded data packet (down-) counter
  ---------------------------------------------------
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        PKT_CNT_q <= MAX_CNT;
      elsif(STRT = '1' and OPS = RUNF and PKT_CNT_q > 0) then
        PKT_CNT_q <= PKT_CNT_q - 1;
      end if;
    end if;
  end process;
 
  ---------------------------------------------------
  -- Input data ROM address generator
  ---------------------------------------------------
 
  STI_RE <= WRITEF_q;
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        STI_CNT_q <= 0;
      elsif(STI_RE = '1' and STI_CNT_q < ST_MEM_SIZE-1) then
        STI_CNT_q <= STI_CNT_q + 1;
      end if;
    end if;
  end process;
 
  STI_ADR <= to_unsigned(STI_CNT_q,log2(ST_MEM_SIZE));
 
  ---------------------------------------------------
  -- Output data ROM address generator
  ---------------------------------------------------
 
  STO_RE <= READF_q;
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        STO_CNT_q <= 0;
      elsif(STO_RE = '1' and STO_CNT_q < ST_MEM_SIZE-1) then
        STO_CNT_q <= STO_CNT_q + 1;
      end if;
    end if;
  end process;
 
  STO_ADR <= to_unsigned(STO_CNT_q,log2(ST_MEM_SIZE));
 
  ---------------------------------------------------
  -- Compare output data to expected data
  -- (error counter)
  ---------------------------------------------------
 
  -- error flag
  ERR <= '1' when (CDC_DV = '1') and not(STO_DO = CDC_DO) else '0';
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        ERR_CNT_q <= 0;
      elsif(ERR = '1') then
        ERR_CNT_q <= ERR_CNT_q + 1;
      end if;
    end if;
  end process;
 
  PASS <= '1' when (ERR_CNT_q = 0) else '0';
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        PASS_q <= '0';
      elsif(DONE = '1') then
        PASS_q <= PASS;
      end if;
    end if;
  end process;
 
  ---------------------------------------------------
  -- Write FSM
  ---------------------------------------------------
 
  -- This FSM monitors codec status output to detect
  -- when a write (to codec memory) operation is
  -- needed.
 
  -- write (to codec) operation-in-progress flag
  WRITE_OP <= '1' when (
     CDC_STS = STS_COD_DIN or -- data to be encoded 
     CDC_STS = STS_DEC_DIN -- data to be decoded
    ) else '0';
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        WRITEF_q <= '0';
        WS_q <= WS_IDLE;
      else
        WRITEF_q <= WRITEF;
        WS_q <= WS;
      end if;
    end if;
  end process;
 
  process(WS_q,WRITE_OP,CNT_q)
  begin
    WRITEF <= '0';
    CNT_RST_W <= '0';
    case WS_q is
      when WS_IDLE =>
        if(WRITE_OP = '1') then
          CNT_RST_W <= '1'; -- reset counter
          WS <= WS_WRITE;
        else
          WS <= WS_IDLE;
        end if;
      when WS_WRITE =>
        WRITEF <= '1';
        if(CNT_q = 0) then
          WS <= WS_WAIT;
        else
          WS <= WS_WRITE;
        end if;
      when WS_WAIT =>
        if(WRITE_OP = '0') then
          WS <= WS_IDLE;
        else
          WS <= WS_WAIT;
        end if;
      when others =>
        WS <= WS_IDLE;
    end case;
  end process;
 
  -- delay write flag by 1 cycle.
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        WRITEF_q2 <= '0';
      else
        WRITEF_q2 <= WRITEF_q;
      end if;
    end if;
  end process;
 
  WE <= WRITEF_q2;
 
  ---------------------------------------------------
  -- Read FSM
  ---------------------------------------------------
 
  -- This FSM monitors codec status output to detect
  -- when a read (from codec memory) operation is
  -- needed.
 
  -- read (from codec) operation-in-progress flag
  READ_OP <= '1' when (
    CDC_STS = STS_COD_DOUT or -- encoded data
    CDC_STS = STS_DEC_DOUT -- decoded data
  ) else '0';
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        READF_q <= '0';
        RS_q <= RS_IDLE;
      else
        READF_q <= READF;
        RS_q <= RS;
      end if;
    end if;
  end process;
 
  process(RS_q,READ_OP,CNT_q)
  begin
    READF <= '0';
    CNT_RST_R <= '0';
    case RS_q is
      when RS_IDLE =>
        if(READ_OP = '1') then
          CNT_RST_R <= '1'; -- reset counter
          RS <= RS_READ;
        else
          RS <= RS_IDLE;
        end if;
      when RS_READ =>
        READF <= '1';
        if(CNT_q = 0) then
          RS <= RS_WAIT;
        else
          RS <= RS_READ;
        end if;
      when RS_WAIT =>
        if(READ_OP = '0') then
          RS <= RS_IDLE;
        else
          RS <= RS_WAIT;
        end if;
      when others =>
        RS <= RS_IDLE;
    end case;
  end process;
 
  RE <= READF_q;
 
  ---------------------------------------------------
  -- Read/Write word (down-) counter
  ---------------------------------------------------
 
  -- This counter counts the data word to be read from
  -- codec memory, or written to codec memory.
 
  --process(CDC_STS)
  --begin
  --  case CDC_STS is
  --    when STS_COD_DIN => CNT_INIT <= DECODED_LEN-1;
  --    when STS_COD_DOUT => CNT_INIT <= ENCODED_LEN-1;
  --    when STS_DEC_DIN => CNT_INIT <= ENCODED_LEN-1;
  --    when STS_DEC_DOUT => CNT_INIT <= DECODED_LEN-1;
  --    when others => CNT_INIT <= 0;
  --  end case;
  --end process;
 
  CNT_INIT <= DECODED_LEN-1 when (
    CDC_STS = STS_COD_DIN or
    CDC_STS = STS_DEC_DOUT
  ) else ENCODED_LEN-1;
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(RST_i = '1') then
        CNT_q <= 0;
      elsif(CNT_RST_W = '1' or CNT_RST_R = '1') then
        CNT_q <= CNT_INIT;
      elsif(CNT_q > 0) then
        CNT_q <= CNT_q - 1;
      end if;
    end if;
  end process;
 
  ---------------------------------------------------
  -- Codec instance
  ---------------------------------------------------
 
  U_CODEC : G729A_CODEC_SDP
    generic map(
      -- synthesis translate_off
      ST_FILE => "NONE",
      WB_FILE => "NONE",
      -- synthesis translate_on
      REGISTER_INPUTS => '0',
      REGISTER_OUTPUTS => '0',
      USE_ROM_MIF => USE_ROM_MIF,
      SIMULATION_ONLY => '0'
    )
    port map(
      CLK_i => CLK_i,
      RST_i => RST_i,
      STRT_i => STRT,
      OPS_i => OPS,
      RE_i => RE,
      WE_i => WE,
      DI_i  => STI_DO,
 
      BSY_o  => CDC_BSY,
      DMAE_o => open,
      STS_o => CDC_STS,
      DV_o  => CDC_DV,
      DO_o  => CDC_DO
    );
 
  ---------------------------------------------------
  -- Input data ROM
  ---------------------------------------------------
 
  G_STIROM_1 : if (USE_ROM_MIF = '1') generate
 
  -- Data content for this ROM is assigned through a MIF file.
  -- This type of ROM is ok for synthesis with Altera tools.
 
  U_STIROM : G729A_ASIP_ROM_MIF
    generic map(
      WCOUNT => ST_MEM_SIZE,
      DATA_WIDTH => SDLEN,
      ADDR_WIDTH => log2(ST_MEM_SIZE),
      ROM_INIT_FILE => "G729A_codec_sti_rom.mif"
    )
    port map(
      CLK_i => CLK_i,
      A_i => STI_ADR,
 
      Q_o => STI_DO
    );
 
  end generate;
 
  G_STIROM_0 : if (USE_ROM_MIF = '0') generate
 
  -- Data content for this ROM is explicitly assigned in VHDL code.
  -- This type of ROM is ok for simulation and for synthesis with
  -- Xilinx tools.
 
  U_STIROM : G729A_ASIP_STI_ROM
    generic map(
      WCOUNT => ST_MEM_SIZE,
      DATA_WIDTH => SDLEN,
      ADDR_WIDTH => log2(ST_MEM_SIZE)
    )
    port map(
      CLK_i => CLK_i,
      A_i => STI_ADR,
 
      Q_o => STI_DO
    );
 
  end generate;
 
  ---------------------------------------------------
  -- Output data ROM
  ---------------------------------------------------
 
  G_STOROM_1 : if (USE_ROM_MIF = '1') generate
 
  -- Data content for this ROM is assigned through a MIF file.
  -- This type of ROM is ok for synthesis with Altera tools.
 
  U_STOROM : G729A_ASIP_ROM_MIF
    generic map(
      WCOUNT => ST_MEM_SIZE,
      DATA_WIDTH => SDLEN,
      ADDR_WIDTH => log2(ST_MEM_SIZE),
      ROM_INIT_FILE => "G729A_codec_sto_rom.mif"
    )
    port map(
      CLK_i => CLK_i,
      A_i => STO_ADR,
 
      Q_o => STO_DO
    );
 
  end generate;
 
  G_STOROM_0 : if (USE_ROM_MIF = '0') generate
 
  -- Data content for this ROM is explicitly assigned in VHDL code.
  -- This type of ROM is ok for simulation and for synthesis with
  -- Xilinx tools.
 
  U_STOROM : G729A_ASIP_STO_ROM
    generic map(
      WCOUNT => ST_MEM_SIZE,
      DATA_WIDTH => SDLEN,
      ADDR_WIDTH => log2(ST_MEM_SIZE)
    )
    port map(
      CLK_i => CLK_i,
      A_i => STO_ADR,
 
      Q_o => STO_DO
    );
 
  end generate;
 
  ---------------------------------------------------
  -- Outputs
  ---------------------------------------------------
 
  DONE_o <= DONE_q;
 
  PASS_o <= PASS_q;
 
end ARC;

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Subversion Repositories g729a_codec

[/] [g729a_codec/] [trunk/] [VHDL/] [SELF_TEST/] [G729A_codec_selftest.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	madsilicon	`-----------------------------------------------------------------`
2			`-- --`
3			`-----------------------------------------------------------------`
4			`-- --`
5			`-- Copyright (C) 2013 Stefano Tonello --`
6			`-- --`
7			`-- This source file may be used and distributed without --`
8			`-- restriction provided that this copyright statement is not --`
9			`-- removed from the file and that any derivative work contains --`
10			`-- the original copyright notice and the associated disclaimer.--`
11			`-- --`
12			-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
13			`-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --`
14			`-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --`
15			`-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --`
16			`-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --`
17			`-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --`
18			`-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --`
19			`-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --`
20			`-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --`
21			`-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --`
22			`-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --`
23			`-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --`
24			`-- POSSIBILITY OF SUCH DAMAGE. --`
25			`-- --`
26			`-----------------------------------------------------------------`
27
28			`---------------------------------------------------------------`
29			`-- G.729a Codec self-test module`
30			`---------------------------------------------------------------`
31
32			`---------------------------------------------------------------`
33			`-- Notes:`
34			`-- This module performs codec self-test (decoding+encoding on`
35			`-- a fixed set of data packets, comparing expected outputs with`
36			`-- actual ones). Self-test results are flagged by DONE and PASS`
37			`-- output signals (DONE = '1' => test is complete, PASS = '1'`
38			`-- => no error has been detected).`
39			`-- This module only needs clock and reset inputs: all input`
40			`-- data are stored in ROM.`
41			`-- This module is synthesizable.`
42			`---------------------------------------------------------------`
43
44			`library IEEE;`
45			`use IEEE.std_logic_1164.all;`
46			`use IEEE.numeric_std.all;`
47			`use STD.textio.all;`
48
49			`library work;`
50			`use work.G729A_ASIP_PKG.all;`
51			`use work.G729A_ASIP_CFG_PKG.all;`
52			`use work.G729A_CODEC_INTF_PKG.all;`
53
54			`entity G729A_CODEC_SELFTEST is`
55			`port(`
56			`CLK_i : in std_logic; -- clock`
57			`RST_i : in std_logic; -- reset`
58
59			`DONE_o : out std_logic; -- test complete`
60			`PASS_o : out std_logic -- test pass`
61			`);`
62			`end G729A_CODEC_SELFTEST;`
63
64			`architecture ARC of G729A_CODEC_SELFTEST is`
65
66			`-- number of packets to encode/decode (do not modify!)`
67			`constant MAX_CNT : natural := 5;`
68
69			`-- use ROM models with MIF file.`
70			`constant USE_ROM_MIF : std_logic := '0';`
71
72			`-- Input/Output data ROM word count`
73			`constant ST_MEM_SIZE : natural := MAX_CNT * (ENCODED_LEN + DECODED_LEN);`
74
75			`-- Control FSM state type`
76			`type XS_T is (`
77			`XS_IDLE,`
78			`XS_INIT,`
79			`XS_RUN,`
80			`XS_STOP`
81			`);`
82
83			`-- Write FSM state type`
84			`type WS_T is (`
85			`WS_IDLE,`
86			`WS_WRITE,`
87			`WS_WAIT`
88			`);`
89
90			`-- Read FSM state type`
91			`type RS_T is (`
92			`RS_IDLE,`
93			`RS_READ,`
94			`RS_WAIT`
95			`);`
96
97			`component G729A_CODEC_SDP is`
98			`generic(`
99			`-- synthesis translate_off`
100			`ST_FILE : string;`
101			`WB_FILE : string;`
102			`-- synthesis translate_on`
103			`REGISTER_INPUTS : std_logic := '0';`
104			`REGISTER_OUTPUTS : std_logic := '0';`
105			`USE_ROM_MIF : std_logic := '0';`
106			`SIMULATION_ONLY : std_logic := '1'`
107			`);`
108			`port(`
109			`CLK_i : in std_logic; -- clock`
110			`RST_i : in std_logic; -- reset`
111			`STRT_i : in std_logic; -- start`
112			`OPS_i : in std_logic_vector(3-1 downto 0);`
113			`RE_i : in std_logic; -- read-enable`
114			`WE_i : in std_logic; -- write-enable`
115			`DI_i : in std_logic_vector(SDLEN-1 downto 0); -- DMA data-in`
116
117			`BSY_o : out std_logic; -- busy`
118			`DMAE_o : out std_logic; -- DMA enable`
119			`STS_o : out std_logic_vector(3-1 downto 0);`
120			`DV_o : out std_logic; -- data-out valid`
121			`DO_o : out std_logic_vector(SDLEN-1 downto 0) -- DMA data-out`
122			`);`
123			`end component;`
124
125			`component G729A_ASIP_ROM_MIF is`
126			`generic(`
127			`WCOUNT : natural := 256;`
128			`DATA_WIDTH : natural := 8;`
129			`ADDR_WIDTH : natural := 8;`
130			`ROM_INIT_FILE : string := "NONE"`
131			`);`
132			`port(`
133			`CLK_i : in std_logic;`
134			`A_i : in unsigned(ADDR_WIDTH-1 downto 0);`
135
136			`Q_o : out std_logic_vector(DATA_WIDTH-1 downto 0)`
137			`);`
138			`end component;`
139
140			`component G729A_ASIP_STI_ROM is`
141			`generic(`
142			`WCOUNT : natural := 425;`
143			`DATA_WIDTH : natural := 16;`
144			`ADDR_WIDTH : natural := 9`
145			`);`
146			`port(`
147			`CLK_i : in std_logic;`
148			`A_i : in unsigned(ADDR_WIDTH-1 downto 0);`
149
150			`Q_o : out std_logic_vector(DATA_WIDTH-1 downto 0)`
151			`);`
152			`end component;`
153
154			`component G729A_ASIP_STO_ROM is`
155			`generic(`
156			`WCOUNT : natural := 425;`
157			`DATA_WIDTH : natural := 16;`
158			`ADDR_WIDTH : natural := 9`
159			`);`
160			`port(`
161			`CLK_i : in std_logic;`
162			`A_i : in unsigned(ADDR_WIDTH-1 downto 0);`
163
164			`Q_o : out std_logic_vector(DATA_WIDTH-1 downto 0)`
165			`);`
166			`end component;`
167
168			`signal XS,XS_q : XS_T;`
169			`signal STRT : std_logic;`
170			`signal OPS : std_logic_vector(3-1 downto 0);`
171			`signal RE : std_logic;`
172			`signal WE : std_logic;`
173			`signal SRST : std_logic := '0'; -- inactive!`
174			`signal CDC_BSY : std_logic;`
175			`signal CDC_DV : std_logic;`
176			`signal CDC_DO : std_logic_vector(SDLEN-1 downto 0);`
177			`signal CDC_STS : std_logic_vector(3-1 downto 0);`
178			`signal PKT_CNT_q : natural range 0 to MAX_CNT;`
179			`signal DONE,DONE_q : std_logic;`
180			`signal PASS,PASS_q : std_logic;`
181			`signal WS,WS_q : WS_T;`
182			`signal RS,RS_q : RS_T;`
183			`signal WRITE_OP : std_logic;`
184			`signal READ_OP : std_logic;`
185			`signal WRITEF,WRITEF_q,WRITEF_q2 : std_logic;`
186			`signal READF,READF_q : std_logic;`
187			`signal CNT_q : natural range 0 to DECODED_LEN-1;`
188			`signal CNT_INIT : natural range 0 to DECODED_LEN-1;`
189			`signal CNT_RST_R,CNT_RST_W : std_logic;`
190			`signal ERR : std_logic;`
191			`signal ERR_CNT_q : natural range 0 to ST_MEM_SIZE-1;`
192			`signal STI_RE : std_logic;`
193			`signal STI_ADR : unsigned(log2(ST_MEM_SIZE)-1 downto 0);`
194			`signal STI_DO : std_logic_vector(SDLEN-1 downto 0);`
195			`signal STI_CNT_q : natural range 0 to ST_MEM_SIZE-1;`
196			`signal STO_RE : std_logic;`
197			`signal STO_ADR : unsigned(log2(ST_MEM_SIZE)-1 downto 0);`
198			`signal STO_DO : std_logic_vector(SDLEN-1 downto 0);`
199			`signal STO_CNT_q : natural range 0 to ST_MEM_SIZE-1;`
200
201			`begin`
202
203			`---------------------------------------------------`
204			`-- Test control FSM`
205			`---------------------------------------------------`
206
207			`-- This FSM performs codec initialization and then`
208			`-- run decoding+encoding on MAX_CNT data packets.`
209
210			`process(CLK_i)`
211			`begin`
212			`if(CLK_i = '1' and CLK_i'event) then`
213			`if(RST_i = '1') then`
214			`DONE_q <= '0';`
215			`XS_q <= XS_IDLE;`
216			`else`
217			`DONE_q <= DONE;`
218			`XS_q <= XS;`
219			`end if;`
220			`end if;`
221			`end process;`
222
223			`process(XS_q,CDC_BSY,PKT_CNT_q)`
224			`begin`
225			`STRT <= '0';`
226			`OPS <= NOP;`
227			`DONE <= '0';`
228			`case XS_q is`
229
230			`-- do nothing while reset is on`
231			`when XS_IDLE =>`
232			`STRT <= '1'; -- assert codec start`
233			`OPS <= INIT; -- select codec operation`
234			`XS <= XS_INIT;`
235
236			`-- initialize codec`
237			`when XS_INIT =>`
238			`if(CDC_BSY = '0') then`
239			`STRT <= '1'; -- assert codec start`
240			`OPS <= RUNF; -- select codec operation`
241			`XS <= XS_RUN;`
242			`else`
243			`XS <= XS_INIT;`
244			`end if;`
245
246			`-- run decoding+encoding`
247			`when XS_RUN =>`
248			`if(CDC_BSY = '0') then`
249			`if(PKT_CNT_q > 0) then`
250			`STRT <= '1'; -- assert codec start`
251			`OPS <= RUNF; -- select codec operation`
252			`XS <= XS_RUN;`
253			`else`
254			`XS <= XS_STOP;`
255			`end if;`
256			`else`
257			`XS <= XS_RUN;`
258			`end if;`
259
260			`-- forever stop...`
261			`when XS_STOP =>`
262			`DONE <= '1';`
263			`XS <= XS_STOP;`
264
265			`when others =>`
266			`XS <= XS_IDLE;`
267
268			`end case;`
269			`end process;`
270
271			`---------------------------------------------------`
272			`-- decoded/encoded data packet (down-) counter`
273			`---------------------------------------------------`
274
275			`process(CLK_i)`
276			`begin`
277			`if(CLK_i = '1' and CLK_i'event) then`
278			`if(RST_i = '1') then`
279			`PKT_CNT_q <= MAX_CNT;`
280			`elsif(STRT = '1' and OPS = RUNF and PKT_CNT_q > 0) then`
281			`PKT_CNT_q <= PKT_CNT_q - 1;`
282			`end if;`
283			`end if;`
284			`end process;`
285
286			`---------------------------------------------------`
287			`-- Input data ROM address generator`
288			`---------------------------------------------------`
289
290			`STI_RE <= WRITEF_q;`
291
292			`process(CLK_i)`
293			`begin`
294			`if(CLK_i = '1' and CLK_i'event) then`
295			`if(RST_i = '1') then`
296			`STI_CNT_q <= 0;`
297			`elsif(STI_RE = '1' and STI_CNT_q < ST_MEM_SIZE-1) then`
298			`STI_CNT_q <= STI_CNT_q + 1;`
299			`end if;`
300			`end if;`
301			`end process;`
302
303			`STI_ADR <= to_unsigned(STI_CNT_q,log2(ST_MEM_SIZE));`
304
305			`---------------------------------------------------`
306			`-- Output data ROM address generator`
307			`---------------------------------------------------`
308
309			`STO_RE <= READF_q;`
310
311			`process(CLK_i)`
312			`begin`
313			`if(CLK_i = '1' and CLK_i'event) then`
314			`if(RST_i = '1') then`
315			`STO_CNT_q <= 0;`
316			`elsif(STO_RE = '1' and STO_CNT_q < ST_MEM_SIZE-1) then`
317			`STO_CNT_q <= STO_CNT_q + 1;`
318			`end if;`
319			`end if;`
320			`end process;`
321
322			`STO_ADR <= to_unsigned(STO_CNT_q,log2(ST_MEM_SIZE));`
323
324			`---------------------------------------------------`
325			`-- Compare output data to expected data`
326			`-- (error counter)`
327			`---------------------------------------------------`
328
329			`-- error flag`
330			`ERR <= '1' when (CDC_DV = '1') and not(STO_DO = CDC_DO) else '0';`
331
332			`process(CLK_i)`
333			`begin`
334			`if(CLK_i = '1' and CLK_i'event) then`
335			`if(RST_i = '1') then`
336			`ERR_CNT_q <= 0;`
337			`elsif(ERR = '1') then`
338			`ERR_CNT_q <= ERR_CNT_q + 1;`
339			`end if;`
340			`end if;`
341			`end process;`
342
343			`PASS <= '1' when (ERR_CNT_q = 0) else '0';`
344
345			`process(CLK_i)`
346			`begin`
347			`if(CLK_i = '1' and CLK_i'event) then`
348			`if(RST_i = '1') then`
349			`PASS_q <= '0';`
350			`elsif(DONE = '1') then`
351			`PASS_q <= PASS;`
352			`end if;`
353			`end if;`
354			`end process;`
355
356			`---------------------------------------------------`
357			`-- Write FSM`
358			`---------------------------------------------------`
359
360			`-- This FSM monitors codec status output to detect`
361			`-- when a write (to codec memory) operation is`
362			`-- needed.`
363
364			`-- write (to codec) operation-in-progress flag`
365			`WRITE_OP <= '1' when (`
366			`CDC_STS = STS_COD_DIN or -- data to be encoded`
367			`CDC_STS = STS_DEC_DIN -- data to be decoded`
368			`) else '0';`
369
370			`process(CLK_i)`
371			`begin`
372			`if(CLK_i = '1' and CLK_i'event) then`
373			`if(RST_i = '1') then`
374			`WRITEF_q <= '0';`
375			`WS_q <= WS_IDLE;`
376			`else`
377			`WRITEF_q <= WRITEF;`
378			`WS_q <= WS;`
379			`end if;`
380			`end if;`
381			`end process;`
382
383			`process(WS_q,WRITE_OP,CNT_q)`
384			`begin`
385			`WRITEF <= '0';`
386			`CNT_RST_W <= '0';`
387			`case WS_q is`
388			`when WS_IDLE =>`
389			`if(WRITE_OP = '1') then`
390			`CNT_RST_W <= '1'; -- reset counter`
391			`WS <= WS_WRITE;`
392			`else`
393			`WS <= WS_IDLE;`
394			`end if;`
395			`when WS_WRITE =>`
396			`WRITEF <= '1';`
397			`if(CNT_q = 0) then`
398			`WS <= WS_WAIT;`
399			`else`
400			`WS <= WS_WRITE;`
401			`end if;`
402			`when WS_WAIT =>`
403			`if(WRITE_OP = '0') then`
404			`WS <= WS_IDLE;`
405			`else`
406			`WS <= WS_WAIT;`
407			`end if;`
408			`when others =>`
409			`WS <= WS_IDLE;`
410			`end case;`
411			`end process;`
412
413			`-- delay write flag by 1 cycle.`
414			`process(CLK_i)`
415			`begin`
416			`if(CLK_i = '1' and CLK_i'event) then`
417			`if(RST_i = '1') then`
418			`WRITEF_q2 <= '0';`
419			`else`
420			`WRITEF_q2 <= WRITEF_q;`
421			`end if;`
422			`end if;`
423			`end process;`
424
425			`WE <= WRITEF_q2;`
426
427			`---------------------------------------------------`
428			`-- Read FSM`
429			`---------------------------------------------------`
430
431			`-- This FSM monitors codec status output to detect`
432			`-- when a read (from codec memory) operation is`
433			`-- needed.`
434
435			`-- read (from codec) operation-in-progress flag`
436			`READ_OP <= '1' when (`
437			`CDC_STS = STS_COD_DOUT or -- encoded data`
438			`CDC_STS = STS_DEC_DOUT -- decoded data`
439			`) else '0';`
440
441			`process(CLK_i)`
442			`begin`
443			`if(CLK_i = '1' and CLK_i'event) then`
444			`if(RST_i = '1') then`
445			`READF_q <= '0';`
446			`RS_q <= RS_IDLE;`
447			`else`
448			`READF_q <= READF;`
449			`RS_q <= RS;`
450			`end if;`
451			`end if;`
452			`end process;`
453
454			`process(RS_q,READ_OP,CNT_q)`
455			`begin`
456			`READF <= '0';`
457			`CNT_RST_R <= '0';`
458			`case RS_q is`
459			`when RS_IDLE =>`
460			`if(READ_OP = '1') then`
461			`CNT_RST_R <= '1'; -- reset counter`
462			`RS <= RS_READ;`
463			`else`
464			`RS <= RS_IDLE;`
465			`end if;`
466			`when RS_READ =>`
467			`READF <= '1';`
468			`if(CNT_q = 0) then`
469			`RS <= RS_WAIT;`
470			`else`
471			`RS <= RS_READ;`
472			`end if;`
473			`when RS_WAIT =>`
474			`if(READ_OP = '0') then`
475			`RS <= RS_IDLE;`
476			`else`
477			`RS <= RS_WAIT;`
478			`end if;`
479			`when others =>`
480			`RS <= RS_IDLE;`
481			`end case;`
482			`end process;`
483
484			`RE <= READF_q;`
485
486			`---------------------------------------------------`
487			`-- Read/Write word (down-) counter`
488			`---------------------------------------------------`
489
490			`-- This counter counts the data word to be read from`
491			`-- codec memory, or written to codec memory.`
492
493	3	madsilicon	`--process(CDC_STS)`
494			`--begin`
495			`-- case CDC_STS is`
496			`-- when STS_COD_DIN => CNT_INIT <= DECODED_LEN-1;`
497			`-- when STS_COD_DOUT => CNT_INIT <= ENCODED_LEN-1;`
498			`-- when STS_DEC_DIN => CNT_INIT <= ENCODED_LEN-1;`
499			`-- when STS_DEC_DOUT => CNT_INIT <= DECODED_LEN-1;`
500			`-- when others => CNT_INIT <= 0;`
501			`-- end case;`
502			`--end process;`
503	2	madsilicon
504	3	madsilicon	`CNT_INIT <= DECODED_LEN-1 when (`
505			`CDC_STS = STS_COD_DIN or`
506			`CDC_STS = STS_DEC_DOUT`
507			`) else ENCODED_LEN-1;`
508
509	2	madsilicon	`process(CLK_i)`
510			`begin`
511			`if(CLK_i = '1' and CLK_i'event) then`
512			`if(RST_i = '1') then`
513			`CNT_q <= 0;`
514			`elsif(CNT_RST_W = '1' or CNT_RST_R = '1') then`
515			`CNT_q <= CNT_INIT;`
516			`elsif(CNT_q > 0) then`
517			`CNT_q <= CNT_q - 1;`
518			`end if;`
519			`end if;`
520			`end process;`
521
522			`---------------------------------------------------`
523			`-- Codec instance`
524			`---------------------------------------------------`
525
526			`U_CODEC : G729A_CODEC_SDP`
527			`generic map(`
528			`-- synthesis translate_off`
529			`ST_FILE => "NONE",`
530			`WB_FILE => "NONE",`
531			`-- synthesis translate_on`
532			`REGISTER_INPUTS => '0',`
533			`REGISTER_OUTPUTS => '0',`
534			`USE_ROM_MIF => USE_ROM_MIF,`
535			`SIMULATION_ONLY => '0'`
536			`)`
537			`port map(`
538			`CLK_i => CLK_i,`
539			`RST_i => RST_i,`
540			`STRT_i => STRT,`
541			`OPS_i => OPS,`
542			`RE_i => RE,`
543			`WE_i => WE,`
544			`DI_i => STI_DO,`
545
546			`BSY_o => CDC_BSY,`
547			`DMAE_o => open,`
548			`STS_o => CDC_STS,`
549			`DV_o => CDC_DV,`
550			`DO_o => CDC_DO`
551			`);`
552
553			`---------------------------------------------------`
554			`-- Input data ROM`
555			`---------------------------------------------------`
556
557			`G_STIROM_1 : if (USE_ROM_MIF = '1') generate`
558
559			`-- Data content for this ROM is assigned through a MIF file.`
560			`-- This type of ROM is ok for synthesis with Altera tools.`
561
562			`U_STIROM : G729A_ASIP_ROM_MIF`
563			`generic map(`
564			`WCOUNT => ST_MEM_SIZE,`
565			`DATA_WIDTH => SDLEN,`
566			`ADDR_WIDTH => log2(ST_MEM_SIZE),`
567			`ROM_INIT_FILE => "G729A_codec_sti_rom.mif"`
568			`)`
569			`port map(`
570			`CLK_i => CLK_i,`
571			`A_i => STI_ADR,`
572
573			`Q_o => STI_DO`
574			`);`
575
576			`end generate;`
577
578			`G_STIROM_0 : if (USE_ROM_MIF = '0') generate`
579
580			`-- Data content for this ROM is explicitly assigned in VHDL code.`
581			`-- This type of ROM is ok for simulation and for synthesis with`
582			`-- Xilinx tools.`
583
584			`U_STIROM : G729A_ASIP_STI_ROM`
585			`generic map(`
586			`WCOUNT => ST_MEM_SIZE,`
587			`DATA_WIDTH => SDLEN,`
588			`ADDR_WIDTH => log2(ST_MEM_SIZE)`
589			`)`
590			`port map(`
591			`CLK_i => CLK_i,`
592			`A_i => STI_ADR,`
593
594			`Q_o => STI_DO`
595			`);`
596
597			`end generate;`
598
599			`---------------------------------------------------`
600			`-- Output data ROM`
601			`---------------------------------------------------`
602
603			`G_STOROM_1 : if (USE_ROM_MIF = '1') generate`
604
605			`-- Data content for this ROM is assigned through a MIF file.`
606			`-- This type of ROM is ok for synthesis with Altera tools.`
607
608			`U_STOROM : G729A_ASIP_ROM_MIF`
609			`generic map(`
610			`WCOUNT => ST_MEM_SIZE,`
611			`DATA_WIDTH => SDLEN,`
612			`ADDR_WIDTH => log2(ST_MEM_SIZE),`
613			`ROM_INIT_FILE => "G729A_codec_sto_rom.mif"`
614			`)`
615			`port map(`
616			`CLK_i => CLK_i,`
617			`A_i => STO_ADR,`
618
619			`Q_o => STO_DO`
620			`);`
621
622			`end generate;`
623
624			`G_STOROM_0 : if (USE_ROM_MIF = '0') generate`
625
626			`-- Data content for this ROM is explicitly assigned in VHDL code.`
627			`-- This type of ROM is ok for simulation and for synthesis with`
628			`-- Xilinx tools.`
629
630			`U_STOROM : G729A_ASIP_STO_ROM`
631			`generic map(`
632			`WCOUNT => ST_MEM_SIZE,`
633			`DATA_WIDTH => SDLEN,`
634			`ADDR_WIDTH => log2(ST_MEM_SIZE)`
635			`)`
636			`port map(`
637			`CLK_i => CLK_i,`
638			`A_i => STO_ADR,`
639
640			`Q_o => STO_DO`
641			`);`
642
643			`end generate;`
644
645			`---------------------------------------------------`
646			`-- Outputs`
647			`---------------------------------------------------`
648
649			`DONE_o <= DONE_q;`
650
651			`PASS_o <= PASS_q;`
652
653			`end ARC;`