1 |
3 |
oana.bonca |
genesys_ddr2: DDR2 memory controller for Digilent Genesys board
|
2 |
|
|
===================================================
|
3 |
|
|
|
4 |
|
|
|
5 |
|
|
What is this stuff?
|
6 |
|
|
==================
|
7 |
|
|
|
8 |
|
|
This is DDR2 memory controller for Digilent Genesys Board with wishbone slave interface and synthesizable test bench.
|
9 |
|
|
|
10 |
|
|
This IP is made-of several design files structured in the following directories:
|
11 |
|
|
- rtl: the user interface for the DDR2, the wishbone interface, external PLL clock generator, reset button debouncer as well as global reset generator
|
12 |
|
|
- rtl\ipcore_dir\MemCtrl: the DDR2 memory controller files generated by Xilinx MIG tool
|
13 |
|
|
- par: ucf file used for testing the synthesisable bench. The ucf file contains the memory pin placement as well as a reset pin connected to button from LOC = "G7"
|
14 |
|
|
- bench: synthesisable test files - top level module (test_DDR2_wb.v) and simple wishbone master mock that generates burst transactions for write followed by a read from the same address
|
15 |
|
|
|
16 |
|
|
|
17 |
|
|
|
18 |
|
|
DDR2 IP core
|
19 |
|
|
==============
|
20 |
|
|
|
21 |
|
|
DDR2_Mem.v - top level DDR2 memory wishbone compatible if module
|
22 |
|
|
|
|
23 |
|
|
|
|
24 |
|
|
--- ddr2_user_if_top.v - user interface top module: receives write/read commands from bus interface module
|
25 |
|
|
generates FIFO wr commands for address and data
|
26 |
|
|
|
27 |
|
|
|
|
28 |
|
|
|
|
29 |
|
|
--- ddr2_adr_data_gen.v : latches commands data byte enable rd/wr data to/from FIFOS
|
30 |
|
|
|
|
31 |
|
|
|
|
32 |
|
|
--- clkGenPLL.v - generates clk signals for memory controller: clk0_125MHz, clk0Phase90, clk0Div2, clk200MHz as well as clkTFT10MHz and clkTFT10_180 for VMODTFT
|
33 |
|
|
|
|
34 |
|
|
|
|
35 |
|
|
--- DDR2_mem_wb_if.v - wishbone slave interface: generates rd/wr command requests for user interface (ddr2_user_if_top.v) module
|
36 |
|
|
|
|
37 |
|
|
|
|
38 |
|
|
--- debounceRst.v - global reset generator & reset button debouncer
|
39 |
|
|
|
|
40 |
|
|
|
|
41 |
|
|
--- rtl\ipcore_dir\MemCtrl - files generated using Xilinx MIG Version: 3.6.1. Parameters: Bust length: 4, Data size: 64.
|
42 |
|
|
|
43 |
|
|
|
44 |
|
|
|
45 |
|
|
Synthesizable bench
|
46 |
|
|
====================
|
47 |
|
|
test_DDR2_wb.v - top level module FPGA proven
|
48 |
|
|
|
|
49 |
|
|
|
|
50 |
|
|
--- DDR2_Mem.v -top level DDR2 memory wishbone compatible if module
|
51 |
|
|
|
|
52 |
|
|
|
|
53 |
|
|
--- wishbone_master_mock - master wishbone interface connected to the memory slave interface; it generates a write burst followed by a read burst transaction
|
54 |
|
|
|
55 |
|
|
|
56 |
|
|
Tools used
|
57 |
|
|
=========
|
58 |
|
|
|
59 |
|
|
Xilinx ISE 14.4, Chipscope courtesy of Xilinx through Xilinx University Program.
|
60 |
|
|
|
61 |
|
|
|
62 |
|
|
Bench test
|
63 |
|
|
==============
|
64 |
|
|
|
65 |
|
|
FPGA proven toplevel module - top level module: test_DDR2_wb.v verified using Chipscope.
|
66 |
|
|
|
67 |
|
|
|
68 |
|
|
Known issues
|
69 |
|
|
=============
|
70 |
|
|
Attempt to move the PLL instance one level up in the hierarchy to test_DDR2_wb (test_DDR2_wb.v) resulted in the FPGA design not working.
|
71 |
|
|
|
72 |
|
|
|
73 |
|
|
|
74 |
|
|
genesys_ddr2 and OpenCores
|
75 |
|
|
==========================
|
76 |
|
|
|
77 |
|
|
This project is licensed under the GNU Public License version 3.
|
78 |
|
|
|
79 |
|
|
|
80 |
|
|
About the same idea as with GNU project except we want free and open source
|
81 |
|
|
IP (intellectual property) cores. We design open source, synthesizable
|
82 |
|
|
cores.
|
83 |
|
|
|
84 |
|
|
For more information visit us at http://www.opencores.org.
|