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//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: 3.6.1

//  \   \         Application: MIG

//  /   /         Filename: ddr2_phy_init.v

// /___/   /\     Date Last Modified: $Date: 2010/11/26 18:26:02 $

// \   \  /  \    Date Created: Thu Aug 24 2006

//  \___\/\___\

//

//Device: Virtex-5

//Design Name: DDR2

//Purpose:

//Reference:

//   This module is the intialization control logic of the memory interface.

//   All commands are issued from here acoording to the burst, CAS Latency and

//   the user commands.

//Revision History:

//   Rev 1.1 - Localparam WR_RECOVERY added and mapped to

//             load mode register. PK. 14/7/08

//   Rev 1.2 - To issue an Auto Refresh command to each chip during various

//             calibration stages logic modified. PK. 08/10/08

//   Rev 1.3 - Retain current data pattern for stage 4 calibration, and create

//             new pattern for stage 4. RC. 09/21/09.

//*****************************************************************************

`timescale 1ns/1ps

module ddr2_phy_init #

  (

   // Following parameters are for 72-bit RDIMM design (for ML561 Reference

   // board design). Actual values may be different. Actual parameters values

   // are passed from design top module MEMCtrl module. Please refer to

   // the MEMCtrl module for actual values.

   parameter BANK_WIDTH    = 2,

   parameter CKE_WIDTH     = 1,

   parameter COL_WIDTH     = 10,

   parameter CS_BITS       = 0,

   parameter CS_NUM        = 1,

   parameter DQ_WIDTH      = 72,

   parameter ODT_WIDTH     = 1,

   parameter ROW_WIDTH     = 14,

   parameter ADDITIVE_LAT  = 0,

   parameter BURST_LEN     = 4,

   parameter TWO_T_TIME_EN = 0,

   parameter BURST_TYPE    = 0,

   parameter CAS_LAT       = 5,

   parameter ODT_TYPE      = 1,

   parameter REDUCE_DRV    = 0,

   parameter REG_ENABLE    = 1,

   parameter TWR           = 15000,

   parameter CLK_PERIOD    = 3000,

   parameter DDR_TYPE      = 1,

   parameter SIM_ONLY      = 0

   )

  (

   input                                   clk0,

   input                                   clkdiv0,

   input                                   rst0,

   input                                   rstdiv0,

   input [3:0]                             calib_done,

   input                                   ctrl_ref_flag,

   input                                   calib_ref_req,

   output reg [3:0]                        calib_start,

   output reg                              calib_ref_done,

   output reg                              phy_init_wren,

   output reg                              phy_init_rden,

   output [ROW_WIDTH-1:0]                  phy_init_addr,

   output [BANK_WIDTH-1:0]                 phy_init_ba,

   output                                  phy_init_ras_n,

   output                                  phy_init_cas_n,

   output                                  phy_init_we_n,

   output [CS_NUM-1:0]                     phy_init_cs_n,

   output [CKE_WIDTH-1:0]                  phy_init_cke,

   output reg                              phy_init_done,

   output                                  phy_init_data_sel

   );

  // time to wait between consecutive commands in PHY_INIT - this is a

  // generic number, and must be large enough to account for worst case

  // timing parameter (tRFC - refresh-to-active) across all memory speed

  // grades and operating frequencies. Expressed in CLKDIV clock cycles.

  localparam  CNTNEXT_CMD = 7'b1111111;

  // time to wait between read and read or precharge for stage 3 & 4

  // the larger CNTNEXT_CMD can also be used, use smaller number to

  // speed up calibration - avoid tRAS violation, and speeds up simulation

  localparam  CNTNEXT_RD  = 4'b1111;

  // Write recovery (WR) time - is defined by

  // tWR (in nanoseconds) by tCK (in nanoseconds) and rounding up a

  // noninteger value to the next integer

  localparam integer WR_RECOVERY =  ((TWR + CLK_PERIOD) - 1)/CLK_PERIOD;

  localparam CS_BITS_FIX         = (CS_BITS == 0) ? 1 : CS_BITS;

  localparam  INIT_CAL1_READ            = 5'h00;

  localparam  INIT_CAL2_READ            = 5'h01;

  localparam  INIT_CAL3_READ            = 5'h02;

  localparam  INIT_CAL4_READ            = 5'h03;

  localparam  INIT_CAL1_WRITE           = 5'h04;

  localparam  INIT_CAL2_WRITE           = 5'h05;

  localparam  INIT_CAL3_WRITE           = 5'h06;

  localparam  INIT_DUMMY_ACTIVE_WAIT    = 5'h07;

  localparam  INIT_PRECHARGE            = 5'h08;

  localparam  INIT_LOAD_MODE            = 5'h09;

  localparam  INIT_AUTO_REFRESH         = 5'h0A;

  localparam  INIT_IDLE                 = 5'h0B;

  localparam  INIT_CNT_200              = 5'h0C;

  localparam  INIT_CNT_200_WAIT         = 5'h0D;

  localparam  INIT_PRECHARGE_WAIT       = 5'h0E;

  localparam  INIT_MODE_REGISTER_WAIT   = 5'h0F;

  localparam  INIT_AUTO_REFRESH_WAIT    = 5'h10;

  localparam  INIT_DEEP_MEMORY_ST       = 5'h11;

  localparam  INIT_DUMMY_ACTIVE         = 5'h12;

  localparam  INIT_CAL1_WRITE_READ      = 5'h13;

  localparam  INIT_CAL1_READ_WAIT       = 5'h14;

  localparam  INIT_CAL2_WRITE_READ      = 5'h15;

  localparam  INIT_CAL2_READ_WAIT       = 5'h16;

  localparam  INIT_CAL3_WRITE_READ      = 5'h17;

  localparam  INIT_CAL3_READ_WAIT       = 5'h18;

  localparam  INIT_CAL4_READ_WAIT       = 5'h19;

  localparam  INIT_CALIB_REF            = 5'h1A;

  localparam  INIT_ZQCL                 = 5'h1B;

  localparam  INIT_WAIT_DLLK_ZQINIT     = 5'h1C;

  localparam  INIT_CAL4_WRITE           = 5'h1D;  // MIG 3.3: New state

  localparam  INIT_CAL4_WRITE_READ      = 5'h1E;  // MIG 3.3: New state

  localparam  INIT_CNTR_INIT            = 4'h0;

  localparam  INIT_CNTR_PRECH_1         = 4'h1;

  localparam  INIT_CNTR_EMR2_INIT       = 4'h2;

  localparam  INIT_CNTR_EMR3_INIT       = 4'h3;

  localparam  INIT_CNTR_EMR_EN_DLL      = 4'h4;

  localparam  INIT_CNTR_MR_RST_DLL      = 4'h5;

  localparam  INIT_CNTR_CNT_200_WAIT    = 4'h6;

  localparam  INIT_CNTR_PRECH_2         = 4'h7;

  localparam  INIT_CNTR_AR_1            = 4'h8;

  localparam  INIT_CNTR_AR_2            = 4'h9;

  localparam  INIT_CNTR_MR_ACT_DLL      = 4'hA;

  localparam  INIT_CNTR_EMR_DEF_OCD     = 4'hB;

  localparam  INIT_CNTR_EMR_EXIT_OCD    = 4'hC;

  localparam  INIT_CNTR_DEEP_MEM        = 4'hD;

  // MIG 3.3: Remove extra precharge occurring at end of calibration

//  localparam  INIT_CNTR_PRECH_3         = 4'hE;

//  localparam  INIT_CNTR_DONE            = 4'hF;

  localparam  INIT_CNTR_DONE            = 4'hE;

  localparam   DDR1                     = 0;

  localparam   DDR2                     = 1;

  localparam   DDR3                     = 2;

  reg [CS_BITS_FIX :0]  auto_cnt_r;

  reg [1:0]             burst_addr_r;

  reg [1:0]             burst_cnt_r;

  wire [1:0]            burst_val;

  wire                  cal_read;

  wire                  cal_write;

  wire                  cal_write_read;

  reg                   cal1_started_r;

  reg                   cal2_started_r;

  reg                   cal4_started_r;

  reg [3:0]             calib_done_r;

  reg                   calib_ref_req_posedge;

  reg                   calib_ref_req_r;

  reg [15:0]            calib_start_shift0_r;

  reg [15:0]            calib_start_shift1_r;

  reg [15:0]            calib_start_shift2_r;

  reg [15:0]            calib_start_shift3_r;

  reg [1:0]             chip_cnt_r;

  reg [4:0]             cke_200us_cnt_r;

  reg                   cke_200us_cnt_en_r;

  reg [7:0]             cnt_200_cycle_r;

  reg                   cnt_200_cycle_done_r;

  reg [6:0]             cnt_cmd_r;

  reg                   cnt_cmd_ok_r;

  reg [3:0]             cnt_rd_r;

  reg                   cnt_rd_ok_r;

  reg                   ctrl_ref_flag_r;

  reg                   done_200us_r;

  reg [ROW_WIDTH-1:0]   ddr_addr_r;

  reg [ROW_WIDTH-1:0]   ddr_addr_r1;

  reg [BANK_WIDTH-1:0]  ddr_ba_r;

  reg [BANK_WIDTH-1:0]  ddr_ba_r1;

  reg                   ddr_cas_n_r;

  reg                   ddr_cas_n_r1;

  reg [CKE_WIDTH-1:0]   ddr_cke_r;

  reg [CS_NUM-1:0]      ddr_cs_n_r;

  reg [CS_NUM-1:0]      ddr_cs_n_r1;

  reg [CS_NUM-1:0]      ddr_cs_disable_r;

  reg                   ddr_ras_n_r;

  reg                   ddr_ras_n_r1;

  reg                   ddr_we_n_r;

  reg                   ddr_we_n_r1;

  wire [15:0]           ext_mode_reg;

  reg [3:0]             init_cnt_r;

  reg                   init_done_r;

  reg [4:0]             init_next_state;

  reg [4:0]             init_state_r;

  reg [4:0]             init_state_r1;

  reg [4:0]             init_state_r1_2t;

  reg [4:0]             init_state_r2;

  wire [15:0]           load_mode_reg;

  wire [15:0]           load_mode_reg0;

  wire [15:0]           load_mode_reg1;

  wire [15:0]           load_mode_reg2;

  wire [15:0]           load_mode_reg3;

  reg                   phy_init_done_r;

  reg                   phy_init_done_r1;

  reg                   phy_init_done_r2;

  reg                   phy_init_done_r3;

  reg                   refresh_req;

  wire [3:0]            start_cal;

  //***************************************************************************

  //*****************************************************************

  // DDR1 and DDR2 Load mode register

  // Mode Register (MR):

  //   [15:14] - unused          - 00

  //   [13]    - reserved        - 0

  //   [12]    - Power-down mode - 0 (normal)

  //   [11:9]  - write recovery  - for Auto Precharge (tWR/tCK)

  //   [8]     - DLL reset       - 0 or 1

  //   [7]     - Test Mode       - 0 (normal)

  //   [6:4]   - CAS latency     - CAS_LAT

  //   [3]     - Burst Type      - BURST_TYPE

  //   [2:0]   - Burst Length    - BURST_LEN

  //*****************************************************************

  generate

    if (DDR_TYPE == DDR2) begin: gen_load_mode_reg_ddr2

      assign load_mode_reg[2:0]   = (BURST_LEN == 8) ? 3'b011 :

                                    ((BURST_LEN == 4) ? 3'b010 : 3'b111);

      assign load_mode_reg[3]     = BURST_TYPE;

      assign load_mode_reg[6:4]   = (CAS_LAT == 3) ? 3'b011 :

                                    ((CAS_LAT == 4) ? 3'b100 :

                                     ((CAS_LAT == 5) ? 3'b101 : 3'b111));

      assign load_mode_reg[7]     = 1'b0;

      assign load_mode_reg[8]     = 1'b0;    // init value only (DLL not reset)

      assign load_mode_reg[11:9]  = (WR_RECOVERY == 6) ? 3'b101 :

                                    ((WR_RECOVERY == 5) ? 3'b100 :

                                     ((WR_RECOVERY == 4) ? 3'b011 :

                                      ((WR_RECOVERY == 3) ? 3'b010 :

                                      3'b001)));

      assign load_mode_reg[15:12] = 4'b000;

    end else if (DDR_TYPE == DDR1)begin: gen_load_mode_reg_ddr1

      assign load_mode_reg[2:0]   = (BURST_LEN == 8) ? 3'b011 :

                                    ((BURST_LEN == 4) ? 3'b010 :

                                     ((BURST_LEN == 2) ? 3'b001 : 3'b111));

      assign load_mode_reg[3]     = BURST_TYPE;

      assign load_mode_reg[6:4]   = (CAS_LAT == 2) ? 3'b010 :

                                    ((CAS_LAT == 3) ? 3'b011 :

                                     ((CAS_LAT == 25) ? 3'b110 : 3'b111));

      assign load_mode_reg[12:7]  = 6'b000000; // init value only

      assign load_mode_reg[15:13]  = 3'b000;

    end

  endgenerate

  //*****************************************************************

  // DDR1 and DDR2 ext mode register

  // Extended Mode Register (MR):

  //   [15:14] - unused          - 00

  //   [13]    - reserved        - 0

  //   [12]    - output enable   - 0 (enabled)

  //   [11]    - RDQS enable     - 0 (disabled)

  //   [10]    - DQS# enable     - 0 (enabled)

  //   [9:7]   - OCD Program     - 111 or 000 (first 111, then 000 during init)

  //   [6]     - RTT[1]          - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)

  //   [5:3]   - Additive CAS    - ADDITIVE_CAS

  //   [2]     - RTT[0]

  //   [1]     - Output drive    - REDUCE_DRV (= 0(full), = 1 (reduced)

  //   [0]     - DLL enable      - 0 (normal)

  //*****************************************************************

  generate

    if (DDR_TYPE == DDR2) begin: gen_ext_mode_reg_ddr2

      assign ext_mode_reg[0]     = 1'b0;

      assign ext_mode_reg[1]     = REDUCE_DRV;

      assign ext_mode_reg[2]     = ((ODT_TYPE == 1) || (ODT_TYPE == 3)) ?

                                   1'b1 : 1'b0;

      assign ext_mode_reg[5:3]   = (ADDITIVE_LAT == 0) ? 3'b000 :

                                   ((ADDITIVE_LAT == 1) ? 3'b001 :

                                    ((ADDITIVE_LAT == 2) ? 3'b010 :

                                     ((ADDITIVE_LAT == 3) ? 3'b011 :

                                      ((ADDITIVE_LAT == 4) ? 3'b100 :

                                      3'b111))));

      assign ext_mode_reg[6]     = ((ODT_TYPE == 2) || (ODT_TYPE == 3)) ?

                                   1'b1 : 1'b0;

      assign ext_mode_reg[9:7]   = 3'b000;

      assign ext_mode_reg[10]    = 1'b0;

      assign ext_mode_reg[15:10] = 6'b000000;

    end else if (DDR_TYPE == DDR1) begin: gen_ext_mode_reg_ddr1

      assign ext_mode_reg[0]     = 1'b0;

      assign ext_mode_reg[1]     = REDUCE_DRV;

      assign ext_mode_reg[12:2]  = 11'b00000000000;

      assign ext_mode_reg[15:13] = 3'b000;

    end

  endgenerate

  //*****************************************************************

  // DDR3 Load mode reg0

  // Mode Register (MR0):

  //   [15:13] - unused          - 000

  //   [12]    - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),

  //             1 (DLL maintained)

  //   [11:9]  - write recovery for Auto Precharge (tWR/tCK = 6)

  //   [8]     - DLL reset       - 0 or 1

  //   [7]     - Test Mode       - 0 (normal)

  //   [6:4],[2]   - CAS latency     - CAS_LAT

  //   [3]     - Burst Type      - BURST_TYPE

  //   [1:0]   - Burst Length    - BURST_LEN

  //*****************************************************************

  generate

    if (DDR_TYPE == DDR3) begin: gen_load_mode_reg0_ddr3

      assign load_mode_reg0[1:0]   = (BURST_LEN == 8) ? 2'b00 :

                                     ((BURST_LEN == 4) ? 2'b10 : 2'b11);

      // Part of CAS latency. This bit is '0' for all CAS latencies

      assign load_mode_reg0[2]     = 1'b0;

      assign load_mode_reg0[3]     = BURST_TYPE;

      assign load_mode_reg0[6:4]   = (CAS_LAT == 5) ? 3'b001 :

                                     (CAS_LAT == 6) ? 3'b010 : 3'b111;

      assign load_mode_reg0[7]     = 1'b0;

      // init value only (DLL reset)

      assign load_mode_reg0[8]     = 1'b1;

      assign load_mode_reg0[11:9]  = 3'b010;

      // Precharge Power-Down DLL 'slow-exit'

      assign load_mode_reg0[12]    = 1'b0;

      assign load_mode_reg0[15:13] = 3'b000;

    end

  endgenerate

  //*****************************************************************

  // DDR3 Load mode reg1

  // Mode Register (MR1):

  //   [15:13] - unused          - 00

  //   [12]    - output enable   - 0 (enabled for DQ, DQS, DQS#)

  //   [11]    - TDQS enable     - 0 (TDQS disabled and DM enabled)

  //   [10]    - reserved   - 0 (must be '0')

  //   [9]     - RTT[2]     - 0

  //   [8]     - reserved   - 0 (must be '0')

  //   [7]     - write leveling - 0 (disabled), 1 (enabled)

  //   [6]     - RTT[1]          - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)

  //   [5]     - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)

  //   [4:3]   - Additive CAS    - ADDITIVE_CAS

  //   [2]     - RTT[0]

  //   [1]     - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)

  //   [0]     - DLL enable      - 0 (normal)

  //*****************************************************************

  generate

    if (DDR_TYPE == DDR3) begin: gen_ext_mode_reg1_ddr3

      // DLL enabled during Imitialization

      assign load_mode_reg1[0]     = 1'b0;

      // RZQ/6

      assign load_mode_reg1[1]     = REDUCE_DRV;

      assign load_mode_reg1[2]     = ((ODT_TYPE == 1) || (ODT_TYPE == 3)) ?

                                     1'b1 : 1'b0;

      assign load_mode_reg1[4:3]   = (ADDITIVE_LAT == 0) ? 2'b00 :

                                     ((ADDITIVE_LAT == 1) ? 2'b01 :

                                      ((ADDITIVE_LAT == 2) ? 2'b10 :

                                       3'b111));

      // RZQ/6

      assign load_mode_reg1[5]     = 1'b0;

      assign load_mode_reg1[6]     = ((ODT_TYPE == 2) || (ODT_TYPE == 3)) ?

                                   1'b1 : 1'b0;

      // Make zero WRITE_LEVEL

      assign load_mode_reg1[7]   = 0;

      assign load_mode_reg1[8]   = 1'b0;

      assign load_mode_reg1[9]   = 1'b0;

      assign load_mode_reg1[10]    = 1'b0;

      assign load_mode_reg1[15:11] = 5'b00000;

    end

  endgenerate

  //*****************************************************************

  // DDR3 Load mode reg2

  // Mode Register (MR2):

  //   [15:11] - unused     - 00

  //   [10:9]  - RTT_WR     - 00 (Dynamic ODT off)

  //   [8]     - reserved   - 0 (must be '0')

  //   [7]     - self-refresh temperature range -

  //               0 (normal), 1 (extended)

  //   [6]     - Auto Self-Refresh - 0 (manual), 1(auto)

  //   [5:3]   - CAS Write Latency (CWL) -

  //               000 (5 for 400 MHz device),

  //               001 (6 for 400 MHz to 533 MHz devices),

  //               010 (7 for 533 MHz to 667 MHz devices),

  //               011 (8 for 667 MHz to 800 MHz)

  //   [2:0]   - Partial Array Self-Refresh (Optional)      -

  //               000 (full array)

  //*****************************************************************

  generate

    if (DDR_TYPE == DDR3) begin: gen_ext_mode_reg2_ddr3

      assign load_mode_reg2[2:0]     = 3'b000;

      assign load_mode_reg2[5:3]   = (CAS_LAT == 5) ? 3'b000 :

                                     (CAS_LAT == 6) ? 3'b001 : 3'b111;

      assign load_mode_reg2[6]     = 1'b0; // Manual Self-Refresh

      assign load_mode_reg2[7]   = 1'b0;

      assign load_mode_reg2[8]   = 1'b0;

      assign load_mode_reg2[10:9]  = 2'b00;

      assign load_mode_reg2[15:11] = 5'b00000;

    end

  endgenerate

  //*****************************************************************

  // DDR3 Load mode reg3

  // Mode Register (MR3):

  //   [15:3] - unused          - All zeros

  //   [2]     - MPR Operation - 0(normal operation), 1(data flow from MPR)

  //   [1:0]   - MPR location     - 00 (Predefined pattern)

  //*****************************************************************

  generate

    if (DDR_TYPE == DDR3)begin: gen_ext_mode_reg3_ddr3

      assign load_mode_reg3[1:0]   = 2'b00;

      assign load_mode_reg3[2]     = 1'b0;

      assign load_mode_reg3[15:3] = 13'b0000000000000;

    end

  endgenerate

  //***************************************************************************

  // Logic for calibration start, and for auto-refresh during cal request

  // CALIB_REF_REQ is used by calibration logic to request auto-refresh

  // durign calibration (used to avoid tRAS violation is certain calibration

  // stages take a long time). Once the auto-refresh is complete and cal can

  // be resumed, CALIB_REF_DONE is asserted by PHY_INIT.

  //***************************************************************************

  // generate pulse for each of calibration start controls

  assign start_cal[0] = ((init_state_r1 == INIT_CAL1_READ) &&

                         (init_state_r2 != INIT_CAL1_READ));

  assign start_cal[1] = ((init_state_r1 == INIT_CAL2_READ) &&

                         (init_state_r2 != INIT_CAL2_READ));

  assign start_cal[2] = ((init_state_r1 == INIT_CAL3_READ) &&

                         (init_state_r2 == INIT_CAL3_WRITE_READ));

  assign start_cal[3] = ((init_state_r1 == INIT_CAL4_READ) &&

                         (init_state_r2 != INIT_CAL4_READ));

  // MIG 3.3: Change to accomodate FSM changes related to stage 4 calibration

//                         (init_state_r2 == INIT_CAL4_WRITE_READ));

  // Generate positive-edge triggered, latched signal to force initialization

  // to pause calibration, and to issue auto-refresh. Clear flag as soon as

  // refresh initiated

  always @(posedge clkdiv0)

    if (rstdiv0) begin

      calib_ref_req_r       <= 1'b0;

      calib_ref_req_posedge <= 1'b0;

      refresh_req           <= 1'b0;

    end else begin

      calib_ref_req_r       <= calib_ref_req;

      calib_ref_req_posedge <= calib_ref_req & ~calib_ref_req_r;

      if (init_state_r1 == INIT_AUTO_REFRESH)

        refresh_req <= 1'b0;

      else if (calib_ref_req_posedge)

        refresh_req <= 1'b1;

    end

  // flag to tell cal1 calibration was started.

  // This flag is used for cal1 auto refreshes

  // some of these bits may not be needed - only needed for those stages that

  // need refreshes within the stage (i.e. very long stages)

  always @(posedge clkdiv0)

    if (rstdiv0) begin

      cal1_started_r <= 1'b0;

      cal2_started_r <= 1'b0;

      cal4_started_r <= 1'b0;

    end else begin

      if (calib_start[0])

        cal1_started_r <= 1'b1;

      if (calib_start[1])

        cal2_started_r <= 1'b1;

      if (calib_start[3])

        cal4_started_r <= 1'b1;

    end

  // Delay start of each calibration by 16 clock cycles to

  // ensure that when calibration logic begins, that read data is already

  // appearing on the bus. Don't really need it, it's more for simulation

  // purposes. Each circuit should synthesize using an SRL16.

  // In first stage of calibration  periodic auto refreshes

  // will be issued to meet memory timing. calib_start_shift0_r[15] will be

  // asserted more than once.calib_start[0] is anded with cal1_started_r so

  // that it is asserted only once. cal1_refresh_done is anded with

  // cal1_started_r so that it is asserted after the auto refreshes.

  always @(posedge clkdiv0) begin

    calib_start_shift0_r <= {calib_start_shift0_r[14:0], start_cal[0]};

    calib_start_shift1_r <= {calib_start_shift1_r[14:0], start_cal[1]};

    calib_start_shift2_r <= {calib_start_shift2_r[14:0], start_cal[2]};

    calib_start_shift3_r <= {calib_start_shift3_r[14:0], start_cal[3]};

    calib_start[0]       <= calib_start_shift0_r[15] & ~cal1_started_r;

    calib_start[1]       <= calib_start_shift1_r[15] & ~cal2_started_r;

    calib_start[2]       <= calib_start_shift2_r[15];

    calib_start[3]       <= calib_start_shift3_r[15] & ~cal4_started_r;

    calib_ref_done       <= calib_start_shift0_r[15] |

                            calib_start_shift1_r[15] |

                            calib_start_shift3_r[15];

  end

  // generate delay for various states that require it (no maximum delay

  // requirement, make sure that terminal count is large enough to cover

  // all cases)

  always @(posedge clkdiv0) begin

    case (init_state_r)

      INIT_PRECHARGE_WAIT,

      INIT_MODE_REGISTER_WAIT,

      INIT_AUTO_REFRESH_WAIT,

      INIT_DUMMY_ACTIVE_WAIT,

      INIT_CAL1_WRITE_READ,

      INIT_CAL1_READ_WAIT,

      INIT_CAL2_WRITE_READ,

      INIT_CAL2_READ_WAIT,

      INIT_CAL3_WRITE_READ,

      INIT_CAL4_WRITE_READ :

        cnt_cmd_r <= cnt_cmd_r + 1;

      default:

        cnt_cmd_r <= 7'b0000000;

    endcase

  end

  // assert when count reaches the value

  always @(posedge clkdiv0) begin

    if(cnt_cmd_r == CNTNEXT_CMD)

      cnt_cmd_ok_r <= 1'b1;

    else

      cnt_cmd_ok_r <= 1'b0;

  end

  always @(posedge clkdiv0) begin

    case (init_state_r)

      INIT_CAL3_READ_WAIT,

      INIT_CAL4_READ_WAIT:

        cnt_rd_r <= cnt_rd_r + 1;

      default:

        cnt_rd_r <= 4'b0000;

    endcase

  end

  always @(posedge clkdiv0) begin

    if(cnt_rd_r == CNTNEXT_RD)

      cnt_rd_ok_r <= 1'b1;

    else

      cnt_rd_ok_r <= 1'b0;

  end

  //***************************************************************************

  // Initial delay after power-on

  //***************************************************************************

  // register the refresh flag from the controller.

  // The refresh flag is in full frequency domain - so a pulsed version must

  // be generated for half freq domain using 2 consecutive full clk cycles

  // The registered version is used for the 200us counter

  always @(posedge clk0)

    ctrl_ref_flag_r <= ctrl_ref_flag;

  always @(posedge clkdiv0)

    cke_200us_cnt_en_r <= ctrl_ref_flag || ctrl_ref_flag_r;

  // 200us counter for cke

  always @(posedge clkdiv0)

    if (rstdiv0) begin

      // skip power-up count if only simulating

      if (SIM_ONLY)

        cke_200us_cnt_r <= 5'b00001;

      else

        cke_200us_cnt_r <= 5'd27;

    end else if (cke_200us_cnt_en_r)

      cke_200us_cnt_r <= cke_200us_cnt_r - 1;

  always @(posedge clkdiv0)

    if (rstdiv0)

      done_200us_r <= 1'b0;

    else if (!done_200us_r)

      done_200us_r <= (cke_200us_cnt_r == 5'b00000);

  // 200 clocks counter - count value : h'64 required for initialization

  // Counts 100 divided by two clocks

  always @(posedge clkdiv0)

    if (rstdiv0 || (init_state_r == INIT_CNT_200))

      cnt_200_cycle_r <= 8'h64;

    else if  (init_state_r == INIT_ZQCL) // ddr3

      cnt_200_cycle_r <= 8'hC8;

    else if (cnt_200_cycle_r != 8'h00)