| 1 |
5 |
pas. |
v1
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| 2 |
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RAM_PACKING,0,M512,18,18,SimpleDual,0,3,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0,
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| 3 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,2,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a1,
|
| 4 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,8,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a2,
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| 5 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,16,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a3,
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| 6 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,9,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a4,
|
| 7 |
|
|
RAM_PACKING,0,M512,18,18,SimpleDual,0,10,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a5,
|
| 8 |
|
|
RAM_PACKING,0,M512,18,18,SimpleDual,0,13,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a6,
|
| 9 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,4,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7,
|
| 10 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,1,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a8,
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| 11 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,11,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a9,
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| 12 |
|
|
RAM_PACKING,0,M512,18,18,SimpleDual,0,17,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a10,
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| 13 |
|
|
RAM_PACKING,0,M512,18,18,SimpleDual,0,7,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a11,
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| 14 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,14,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a12,
|
| 15 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,6,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a13,
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| 16 |
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RAM_PACKING,0,M512,18,18,SimpleDual,0,12,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a14,
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| 17 |
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|
RAM_PACKING,0,M512,18,18,SimpleDual,0,0,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a15,
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