URL
https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk
/EdgeDetector - arch
/Fifo8b - arch
/Fifo8b_Test_vhd - behavior
/RegsGpibFasade - arch
/RegsGpibFasade_communication_test - behavior
/Uart - arch
/gpibInterface - Behavioral
/main - Behavioral
/main - Behavioral/gpib0 - RegsGpibFasade - arch
/main - Behavioral/gpib0 - RegsGpibFasade - arch/ev - EventReg - arch
/main - Behavioral/gpib0 - RegsGpibFasade - arch/gpib - gpibInterface - Behavioral
/main - Behavioral/gpib0 - RegsGpibFasade - arch/ig - InterruptGenerator - arch
/main - Behavioral/gpib0 - RegsGpibFasade - arch/rc0 - ReaderControlReg0 - arch
/main - Behavioral/gpib0 - RegsGpibFasade - arch/readerFifo - Fifo8b - arch
/main - Behavioral/gpib0 - RegsGpibFasade - arch/wc0 - WriterControlReg0 - arch
/main - Behavioral/gpib0 - RegsGpibFasade - arch/writerFifo - Fifo8b - arch
main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/src/main.vhd)
0
0
000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000163000000020000000000000000000000000000000064ffffffff000000810000000000000002000001630000000100000000000000000000000100000000
true
main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/src/main.vhd)
Design Utilities/Compile HDL Simulation Libraries
Implement Design
Synthesize - XST
0
0
000000ff00000000000000010000000100000000000000000000000000000000000000000000000172000000010000000100000000000000000000000064ffffffff000000810000000000000001000001720000000100000000
false
0
0
000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000040101000100000000000000000000000064ffffffff000000810000000000000004000000b40000000100000000000000240000000100000000000000660000000100000000000000640000000100000000
false
main.ucf
0
0
000000ff00000000000000010000000000000000010000000000000000000000000000000000000163000000010001000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000
false
work
Design Utilities/Compile HDL Simulation Libraries
Implement Design
Synthesize - XST
Generate Programming File
6
0
000000ff0000000000000001000000010000000000000000000000000000000000000000000000011b000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011b0000000100000000
false
Generate Programming File
User Constraints
Add Existing Source
0
0
000000ff0000000000000001000000010000000000000000000000000000000000000000000000012a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012a0000000100000000
false
Add Existing Source
000000ff00000000000000020000015e0000012a01000000040100000002
Implementation
/Fifo8b_Test_vhd - behavior
/MemoryBlock_Test_vhd - behavior
/MemoryBlock_Test_vhd - behavior/uut - MemoryBlock - arch
/RegMultiplexer_Test_vhd - behavior
/RegsGpibFasade_communication_test - behavior
/RegsGpibFasade_test - behavior
/RegsGpibFasade_test - behavior/uut - RegsGpibFasade - arch
/gpibInterfaceTest - behavior
/gpibReaderTest - behavior
/gpibWriterReaderTest - behavior
/gpib_DC_Test - behavior
/gpib_DT_Test - behavior
/gpib_PP_Test - behavior
/gpib_RL_Test - behavior
/gpib_SeriallPoll_Test - behavior
/gpib_TE_LE_Test - behavior
/main - Behavioral
/main - Behavioral/gpib0 - RegsGpibFasade - arch
main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/src/main.vhd)
3
0
000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002a0000000020000000000000000000000000000000064ffffffff000000810000000000000002000002a00000000100000000000000000000000100000000
false
main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/src/main.vhd)
Design Utilities
Add Existing Source
0
0
000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000
false
Add Existing Source
Behavioral Check Syntax
0
0
000000ff00000000000000010000000100000000000000000000000000000000000000000000000124000000010000000100000000000000000000000064ffffffff000000810000000000000001000001240000000100000000
false
Behavioral Check Syntax
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