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[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_C.vhd] - Blame information for rev 13

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--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller.  If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity:      if_func_C
-- Date:        23:00:30 10/04/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library ieee;
 
use ieee.std_logic_1164.all;
 
use work.utilPkg.all;
 
 
entity if_func_C is
        port(
                -- device inputs
                clk : in std_logic; -- clock
                pon : in std_logic; -- power on
                gts : in std_logic; -- go to standby
                rpp : in std_logic; -- request parallel poll
                tcs : in std_logic; -- take control synchronously
                tca : in std_logic; -- take control asynchronously
                sic : in std_logic; -- send interface clear
                rsc : in std_logic; -- request system control
                sre : in std_logic; -- send remote enable
                -- state inputs
                TADS : in std_logic; -- talker addressed state (T or TE)
                ACDS : in std_logic; -- accept data state (AH)
                ANRS : in std_logic; -- acceptor not ready state (AH)
                STRS : in std_logic; -- source transfer state (SH)
                SDYS : in std_logic; -- source delay state (SH)
                -- command inputs
                ATN_in : in std_logic; -- attention
                IFC_in : in std_logic; -- interface clear
                TCT_in : in std_logic; -- take control
                SRQ_in : in std_logic; -- service request
                -- command outputs
                ATN_out : out std_logic; -- attention
                IFC_out : out std_logic; -- interface clear
                TCT_out : out std_logic; -- take control
                IDY_out : out std_logic; -- identify
                REN_out : out std_logic; -- remote enable
                -- reported states
                CACS : out std_logic; -- controller active state
                CTRS : out std_logic; -- controller transfer state
                CSBS : out std_logic; -- controller standby state
                CPPS : out std_logic; -- controller parallel poll state
                CSRS : out std_logic; -- controller service requested state
                SACS : out std_logic -- system control active state
        );
end if_func_C;
 
architecture Behavioral of if_func_C is
 
        -- states
        type C_STATE_1 is (
                -- controller idle state
                ST_CIDS,
                -- controller addressed state
                ST_CADS,
                -- controller transfer state
                ST_CTRS,
                -- controller active state
                ST_CACS,
                -- controller standby state
                ST_CSBS,
                -- controllet synchronous wait state
                ST_CSWS,
                -- controller active wait state
                ST_CAWS,
                -- controller parallel poll wait state
                ST_CPWS,
                -- controller parallel poll wait state
                ST_CPPS
        );
 
        -- states
        type C_STATE_2 is (
                -- controller service not requested state
                ST_CSNS,
                -- controller service requested state
                ST_CSRS
 
        );
 
        -- states
        type C_STATE_3 is (
                -- system control interface clear idle state
                ST_SIIS,
                -- system control interface clear active state
                ST_SIAS,
                -- system control interface clear not active state
                ST_SINS
 
        );
 
        -- states
        type C_STATE_4 is (
                -- system control remote enable idle state
                ST_SRIS,
                -- system control remote enable active state
                ST_SRAS,
                -- system control remote enable not active state
                ST_SRNS
 
        );
 
        -- states
        type C_STATE_5 is (
                -- system control not active state
                ST_SNAS,
                -- system control active state
                ST_SACS
 
        );
 
        -- current state
        signal current_state_1 : C_STATE_1;
        signal current_state_2 : C_STATE_2;
        signal current_state_3 : C_STATE_3;
        signal current_state_4 : C_STATE_4;
        signal current_state_5 : C_STATE_5;
 
        -- events
        signal event1_1, event1_2, event1_3, event1_4, event1_5,
                event1_6, event1_7, event1_8, event1_9, event1_10,
                event1_11, event1_12 : boolean;
 
        signal event2_1, event2_2 : boolean;
 
        signal event3_1, event3_2, event3_3, event3_4, event3_5 : boolean;
 
        signal event4_1, event4_2, event4_3, event4_4, event4_5 : boolean;
 
        signal event5_1, event5_2 : boolean;
 
        -- timers
        constant TIMER_T6_TIMEOUT : integer := 110;
        constant TIMER_T7_TIMEOUT : integer := 25;
        constant TIMER_T9_TIMEOUT : integer := 75;
        constant TIMER_A_MAX : integer := 128;
        signal timer_a : integer range 0 to TIMER_A_MAX;
        signal timer_T6Expired : boolean;
        signal timer_T7Expired : boolean;
        signal timer_T9Expired : boolean;
 
        constant TIMER_T8_TIMEOUT : integer := 5000;
        constant TIMER_B_MAX : integer := 5004;
        signal timer_b : integer range 0 to TIMER_B_MAX;
        signal timer_b_1 : integer range 0 to TIMER_B_MAX;
        signal timer_T8Expired : boolean;
        signal timer_T8_1Expired : boolean;
 
 
begin
 
        -- state machine process - C_STATE_1
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        current_state_1 <= ST_CIDS;
                elsif rising_edge(clk) then
 
                        -- timer
                        if timer_a < TIMER_A_MAX then
                                timer_a <= timer_a + 1;
                        end if;
 
                        -- state machine
                        case current_state_1 is
                                ------------------
                                when ST_CIDS =>
                                        if event1_1 then
                                                -- no state change
                                        elsif event1_2 then
                                                current_state_1 <= ST_CADS;
                                        end if;
                                ------------------
                                when ST_CADS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_4 then
                                                current_state_1 <= ST_CACS;
                                        end if;
                                ------------------
                                when ST_CACS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_5 then
                                                current_state_1 <= ST_CTRS;
                                        elsif event1_6 then
                                                current_state_1 <= ST_CSBS;
                                        elsif event1_7 then
                                                timer_a <= 0;
                                                current_state_1 <= ST_CPWS;
                                        end if;
                                ------------------
                                when ST_CTRS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_3 or event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        end if;
                                ------------------
                                when ST_CSBS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_9 then
                                                timer_a <= 0;
                                                current_state_1 <= ST_CSWS;
                                        end if;
                                ------------------
                                when ST_CSWS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_10 then
                                                timer_a <= 0;
                                                current_state_1 <= ST_CAWS;
                                        end if;
                                ------------------
                                when ST_CAWS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_8 then
                                                current_state_1 <= ST_CACS;
                                        elsif event1_7 then
                                                timer_a <= 0;
                                                current_state_1 <= ST_CPWS;
                                        end if;
                                ------------------
                                when ST_CPWS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_11 then
                                                current_state_1 <= ST_CPPS;
                                        end if;
                                ------------------
                                when ST_CPPS =>
                                        if event1_1 then
                                                current_state_1 <= ST_CIDS;
                                        elsif event1_12 then
                                                current_state_1 <= ST_CAWS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_1 <= ST_CIDS;
                        end case;
                end if;
        end process;
 
        -- state machine process - C_STATE_2
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        current_state_2 <= ST_CSNS;
                elsif rising_edge(clk) then
                        -- state machine
                        case current_state_2 is
                                ------------------
                                when ST_CSNS =>
                                        if event2_1 then
                                                current_state_2 <= ST_CSRS;
                                        end if;
                                ------------------
                                when ST_CSRS =>
                                        if event2_2 then
                                                current_state_2 <= ST_CSNS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_2 <= ST_CSNS;
                        end case;
                end if;
        end process;
 
        -- state machine process - C_STATE_3
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        current_state_3 <= ST_SIIS;
                elsif rising_edge(clk) then
 
                        -- timer
                        if timer_b < TIMER_B_MAX then
                                timer_b <= timer_b + 1;
                        end if;
 
                        -- state machine
                        case current_state_3 is
                                ------------------
                                when ST_SIIS =>
                                        if event3_1 then
                                                -- no state change
                                        elsif event3_2 then
                                                timer_b <= 0;
                                                current_state_3 <= ST_SIAS;
                                        elsif event3_3 then
                                                current_state_3 <= ST_SINS;
                                        end if;
                                ------------------
                                when ST_SIAS =>
                                        if event3_1 then
                                                current_state_3 <= ST_SIIS;
                                        elsif event3_5 then
                                                current_state_3 <= ST_SINS;
                                        end if;
                                ------------------
                                when ST_SINS =>
                                        if event3_1 then
                                                current_state_3 <= ST_SIIS;
                                        elsif event3_4 then
                                                current_state_3 <= ST_SIAS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_3 <= ST_SIIS;
                        end case;
                end if;
        end process;
 
        -- state machine process - C_STATE_4
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        timer_b_1 <= 0;
                        current_state_4 <= ST_SRIS;
                elsif rising_edge(clk) then
 
                        -- timer
                        if timer_b_1 < TIMER_B_MAX then
                                timer_b_1 <= timer_b_1 + 1;
                        end if;
 
                        -- state machine
                        case current_state_4 is
                                ------------------
                                when ST_SRIS =>
                                        if event4_1 then
                                                -- no state change
                                        elsif event4_2 then
                                                timer_b_1 <= 0;
                                                current_state_4 <= ST_SRAS;
                                        elsif event4_3 then
                                                current_state_4 <= ST_SRNS;
                                        end if;
                                ------------------
                                when ST_SRAS =>
                                        if event4_1 then
                                                current_state_4 <= ST_SRIS;
                                        elsif event4_5 then
                                                current_state_4 <= ST_SRNS;
                                        end if;
                                ------------------
                                when ST_SRNS =>
                                        if event4_1 then
                                                current_state_4 <= ST_SRIS;
                                        elsif event4_4 then
                                                timer_b_1 <= 0;
                                                current_state_4 <= ST_SRAS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_4 <= ST_SRIS;
                        end case;
                end if;
        end process;
 
        -- state machine process - C_STATE_5
        process(pon, clk) begin
                -- async reset
                if pon='1' then
                        current_state_5 <= ST_SNAS;
                elsif rising_edge(clk) then
                        -- state machine
                        case current_state_5 is
                                ------------------
                                when ST_SNAS =>
                                        if event5_1 then
                                                current_state_5 <= ST_SACS;
                                        end if;
                                ------------------
                                when ST_SACS =>
                                        if event5_2 then
                                                current_state_5 <= ST_SNAS;
                                        end if;
                                ------------------
                                when others =>
                                        current_state_5 <= ST_SNAS;
                        end case;
                end if;
        end process;
 
        -- events
        event1_1 <= IFC_in='1' and current_state_5/=ST_SACS;
        event1_2 <= (TCT_in='1' and TADS='1' and ACDS='1') or current_state_3=ST_SIAS;
        event1_3 <= STRS='0';
        event1_4 <= ATN_in='0';
        event1_5 <= TCT_in='1' and TADS='0' and ACDS='1';
        event1_6 <= SDYS='0' and STRS='0' and gts='1';
        event1_7 <= rpp='1';
        event1_8 <= timer_T9Expired and rpp='0';
        event1_9 <= (tcs='1' and ANRS='1') or tca='1';
        event1_10 <= timer_T7Expired;
        event1_11 <= timer_T6Expired;
        event1_12 <= rpp='0';
 
        event2_1 <= SRQ_in='1';
        event2_2 <= SRQ_in='0';
 
        event3_1 <= current_state_5/=ST_SACS;
        event3_2 <= current_state_5=ST_SACS and sic='1';
        event3_3 <= current_state_5=ST_SACS and sic='0';
        event3_4 <= sic='1';
        event3_5 <= sic='0' and timer_T8Expired;
 
        event4_1 <= current_state_5/=ST_SACS;
        event4_2 <= current_state_5=ST_SACS and sre='1';
        event4_3 <= current_state_5=ST_SACS and sre='0';
        event4_4 <= sre='1';
        event4_5 <= sre='0' and timer_T8_1Expired;
 
        event5_1 <= rsc='1';
        event5_2 <= rsc='0';
 
        -- timers
        timer_T6Expired <= timer_a >= TIMER_T6_TIMEOUT;
        timer_T7Expired <= timer_a >= TIMER_T7_TIMEOUT;
        timer_T9Expired <= timer_a >= TIMER_T9_TIMEOUT;
 
        timer_T8Expired <= timer_b >= TIMER_T8_TIMEOUT;
        timer_T8_1Expired <= timer_b_1 >= TIMER_T8_TIMEOUT;
 
 
        CPPS <= to_stdl(current_state_1 = ST_CPPS);
        CSRS <= to_stdl(current_state_2 = ST_CSRS);
        CSBS <= to_stdl(current_state_1 = ST_CSBS);
        CACS <= to_stdl(current_state_1 = ST_CACS);
        SACS <= to_stdl(current_state_5 = ST_SACS);
 
        -- CTRS
        with current_state_1 select
                CTRS <=
                        '1' when ST_CTRS,
                        '0' when others;
 
        -- ATN
        with current_state_1 select
                ATN_out <=
                        '0' when ST_CIDS,
                        '0' when ST_CADS,
                        '0' when ST_CSBS,
                        '1' when others;
 
        -- IDY_out
        with current_state_1 select
                IDY_out <=
                        '1' when ST_CPWS,
                        '1' when ST_CPPS,
                        '0' when others;
 
        -- TCT
        with current_state_1 select
                TCT_out <=
                        '1' when ST_CTRS,
                        '0' when others;
 
        -- IFC
        with current_state_3 select
                IFC_out <=
                        '1' when ST_SIAS,
                        '0' when others;
 
        -- REN
        with current_state_4 select
                REN_out <=
                        '1' when ST_SRAS,
                        '0' when others;
 
end Behavioral;
 

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Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [vhdl/] [src/] [gpib/] [if_func_C.vhd] - Blame information for rev 13

Line No.	Rev	Author	Line
1	3	Andrewski	`--------------------------------------------------------------------------------`
2	13	Andrewski	`--This file is part of fpga_gpib_controller.`
3			`--`
4			`-- Fpga_gpib_controller is free software: you can redistribute it and/or modify`
5			`-- it under the terms of the GNU General Public License as published by`
6			`-- the Free Software Foundation, either version 3 of the License, or`
7			`-- (at your option) any later version.`
8			`--`
9			`-- Fpga_gpib_controller is distributed in the hope that it will be useful,`
10			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
11			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
12			`-- GNU General Public License for more details.`
13
14			`-- You should have received a copy of the GNU General Public License`
15			`-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.`
16			`--------------------------------------------------------------------------------`
17	3	Andrewski	`-- Entity: if_func_C`
18			`-- Date: 23:00:30 10/04/2011`
19	13	Andrewski	`-- Author: Andrzej Paluch`
20	3	Andrewski	`--------------------------------------------------------------------------------`
21			`library ieee;`
22
23			`use ieee.std_logic_1164.all;`
24
25			`use work.utilPkg.all;`
26
27
28			`entity if_func_C is`
29			`port(`
30			`-- device inputs`
31			`clk : in std_logic; -- clock`
32			`pon : in std_logic; -- power on`
33			`gts : in std_logic; -- go to standby`
34			`rpp : in std_logic; -- request parallel poll`
35			`tcs : in std_logic; -- take control synchronously`
36			`tca : in std_logic; -- take control asynchronously`
37			`sic : in std_logic; -- send interface clear`
38			`rsc : in std_logic; -- request system control`
39			`sre : in std_logic; -- send remote enable`
40			`-- state inputs`
41			`TADS : in std_logic; -- talker addressed state (T or TE)`
42			`ACDS : in std_logic; -- accept data state (AH)`
43			`ANRS : in std_logic; -- acceptor not ready state (AH)`
44			`STRS : in std_logic; -- source transfer state (SH)`
45			`SDYS : in std_logic; -- source delay state (SH)`
46			`-- command inputs`
47			`ATN_in : in std_logic; -- attention`
48			`IFC_in : in std_logic; -- interface clear`
49			`TCT_in : in std_logic; -- take control`
50			`SRQ_in : in std_logic; -- service request`
51			`-- command outputs`
52			`ATN_out : out std_logic; -- attention`
53			`IFC_out : out std_logic; -- interface clear`
54			`TCT_out : out std_logic; -- take control`
55			`IDY_out : out std_logic; -- identify`
56			`REN_out : out std_logic; -- remote enable`
57			`-- reported states`
58			`CACS : out std_logic; -- controller active state`
59			`CTRS : out std_logic; -- controller transfer state`
60			`CSBS : out std_logic; -- controller standby state`
61			`CPPS : out std_logic; -- controller parallel poll state`
62			`CSRS : out std_logic; -- controller service requested state`
63			`SACS : out std_logic -- system control active state`
64			`);`
65			`end if_func_C;`
66
67			`architecture Behavioral of if_func_C is`
68
69			`-- states`
70			`type C_STATE_1 is (`
71			`-- controller idle state`
72			`ST_CIDS,`
73			`-- controller addressed state`
74			`ST_CADS,`
75			`-- controller transfer state`
76			`ST_CTRS,`
77			`-- controller active state`
78			`ST_CACS,`
79			`-- controller standby state`
80			`ST_CSBS,`
81			`-- controllet synchronous wait state`
82			`ST_CSWS,`
83			`-- controller active wait state`
84			`ST_CAWS,`
85			`-- controller parallel poll wait state`
86			`ST_CPWS,`
87			`-- controller parallel poll wait state`
88			`ST_CPPS`
89			`);`
90
91			`-- states`
92			`type C_STATE_2 is (`
93			`-- controller service not requested state`
94			`ST_CSNS,`
95			`-- controller service requested state`
96			`ST_CSRS`
97
98			`);`
99
100			`-- states`
101			`type C_STATE_3 is (`
102			`-- system control interface clear idle state`
103			`ST_SIIS,`
104			`-- system control interface clear active state`
105			`ST_SIAS,`
106			`-- system control interface clear not active state`
107			`ST_SINS`
108
109			`);`
110
111			`-- states`
112			`type C_STATE_4 is (`
113			`-- system control remote enable idle state`
114			`ST_SRIS,`
115			`-- system control remote enable active state`
116			`ST_SRAS,`
117			`-- system control remote enable not active state`
118			`ST_SRNS`
119
120			`);`
121
122			`-- states`
123			`type C_STATE_5 is (`
124			`-- system control not active state`
125			`ST_SNAS,`
126			`-- system control active state`
127			`ST_SACS`
128
129			`);`
130
131			`-- current state`
132			`signal current_state_1 : C_STATE_1;`
133			`signal current_state_2 : C_STATE_2;`
134			`signal current_state_3 : C_STATE_3;`
135			`signal current_state_4 : C_STATE_4;`
136			`signal current_state_5 : C_STATE_5;`
137
138			`-- events`
139			`signal event1_1, event1_2, event1_3, event1_4, event1_5,`
140			`event1_6, event1_7, event1_8, event1_9, event1_10,`
141			`event1_11, event1_12 : boolean;`
142
143			`signal event2_1, event2_2 : boolean;`
144
145			`signal event3_1, event3_2, event3_3, event3_4, event3_5 : boolean;`
146
147			`signal event4_1, event4_2, event4_3, event4_4, event4_5 : boolean;`
148
149			`signal event5_1, event5_2 : boolean;`
150
151			`-- timers`
152			`constant TIMER_T6_TIMEOUT : integer := 110;`
153			`constant TIMER_T7_TIMEOUT : integer := 25;`
154			`constant TIMER_T9_TIMEOUT : integer := 75;`
155			`constant TIMER_A_MAX : integer := 128;`
156			`signal timer_a : integer range 0 to TIMER_A_MAX;`
157			`signal timer_T6Expired : boolean;`
158			`signal timer_T7Expired : boolean;`
159			`signal timer_T9Expired : boolean;`
160
161			`constant TIMER_T8_TIMEOUT : integer := 5000;`
162			`constant TIMER_B_MAX : integer := 5004;`
163			`signal timer_b : integer range 0 to TIMER_B_MAX;`
164			`signal timer_b_1 : integer range 0 to TIMER_B_MAX;`
165			`signal timer_T8Expired : boolean;`
166			`signal timer_T8_1Expired : boolean;`
167
168
169			`begin`
170
171			`-- state machine process - C_STATE_1`
172			`process(pon, clk) begin`
173			`-- async reset`
174			`if pon='1' then`
175			`current_state_1 <= ST_CIDS;`
176			`elsif rising_edge(clk) then`
177
178			`-- timer`
179			`if timer_a < TIMER_A_MAX then`
180			`timer_a <= timer_a + 1;`
181			`end if;`
182
183			`-- state machine`
184			`case current_state_1 is`
185			`------------------`
186			`when ST_CIDS =>`
187			`if event1_1 then`
188			`-- no state change`
189			`elsif event1_2 then`
190			`current_state_1 <= ST_CADS;`
191			`end if;`
192			`------------------`
193			`when ST_CADS =>`
194			`if event1_1 then`
195			`current_state_1 <= ST_CIDS;`
196			`elsif event1_4 then`
197			`current_state_1 <= ST_CACS;`
198			`end if;`
199			`------------------`
200			`when ST_CACS =>`
201			`if event1_1 then`
202			`current_state_1 <= ST_CIDS;`
203			`elsif event1_5 then`
204			`current_state_1 <= ST_CTRS;`
205			`elsif event1_6 then`
206			`current_state_1 <= ST_CSBS;`
207			`elsif event1_7 then`
208			`timer_a <= 0;`
209			`current_state_1 <= ST_CPWS;`
210			`end if;`
211			`------------------`
212			`when ST_CTRS =>`
213			`if event1_1 then`
214			`current_state_1 <= ST_CIDS;`
215			`elsif event1_3 or event1_1 then`
216			`current_state_1 <= ST_CIDS;`
217			`end if;`
218			`------------------`
219			`when ST_CSBS =>`
220			`if event1_1 then`
221			`current_state_1 <= ST_CIDS;`
222			`elsif event1_9 then`
223			`timer_a <= 0;`
224			`current_state_1 <= ST_CSWS;`
225			`end if;`
226			`------------------`
227			`when ST_CSWS =>`
228			`if event1_1 then`
229			`current_state_1 <= ST_CIDS;`
230			`elsif event1_10 then`
231			`timer_a <= 0;`
232			`current_state_1 <= ST_CAWS;`
233			`end if;`
234			`------------------`
235			`when ST_CAWS =>`
236			`if event1_1 then`
237			`current_state_1 <= ST_CIDS;`
238			`elsif event1_8 then`
239			`current_state_1 <= ST_CACS;`
240			`elsif event1_7 then`
241			`timer_a <= 0;`
242			`current_state_1 <= ST_CPWS;`
243			`end if;`
244			`------------------`
245			`when ST_CPWS =>`
246			`if event1_1 then`
247			`current_state_1 <= ST_CIDS;`
248			`elsif event1_11 then`
249			`current_state_1 <= ST_CPPS;`
250			`end if;`
251			`------------------`
252			`when ST_CPPS =>`
253			`if event1_1 then`
254			`current_state_1 <= ST_CIDS;`
255			`elsif event1_12 then`
256			`current_state_1 <= ST_CAWS;`
257			`end if;`
258			`------------------`
259			`when others =>`
260			`current_state_1 <= ST_CIDS;`
261			`end case;`
262			`end if;`
263			`end process;`
264
265			`-- state machine process - C_STATE_2`
266			`process(pon, clk) begin`
267			`-- async reset`
268			`if pon='1' then`
269			`current_state_2 <= ST_CSNS;`
270			`elsif rising_edge(clk) then`
271			`-- state machine`
272			`case current_state_2 is`
273			`------------------`
274			`when ST_CSNS =>`
275			`if event2_1 then`
276			`current_state_2 <= ST_CSRS;`
277			`end if;`
278			`------------------`
279			`when ST_CSRS =>`
280			`if event2_2 then`
281			`current_state_2 <= ST_CSNS;`
282			`end if;`
283			`------------------`
284			`when others =>`
285			`current_state_2 <= ST_CSNS;`
286			`end case;`
287			`end if;`
288			`end process;`
289
290			`-- state machine process - C_STATE_3`
291			`process(pon, clk) begin`
292			`-- async reset`
293			`if pon='1' then`
294			`current_state_3 <= ST_SIIS;`
295			`elsif rising_edge(clk) then`
296
297			`-- timer`
298			`if timer_b < TIMER_B_MAX then`
299			`timer_b <= timer_b + 1;`
300			`end if;`
301
302			`-- state machine`
303			`case current_state_3 is`
304			`------------------`
305			`when ST_SIIS =>`
306			`if event3_1 then`
307			`-- no state change`
308			`elsif event3_2 then`
309			`timer_b <= 0;`
310			`current_state_3 <= ST_SIAS;`
311			`elsif event3_3 then`
312			`current_state_3 <= ST_SINS;`
313			`end if;`
314			`------------------`
315			`when ST_SIAS =>`
316			`if event3_1 then`
317			`current_state_3 <= ST_SIIS;`
318			`elsif event3_5 then`
319			`current_state_3 <= ST_SINS;`
320			`end if;`
321			`------------------`
322			`when ST_SINS =>`
323			`if event3_1 then`
324			`current_state_3 <= ST_SIIS;`
325			`elsif event3_4 then`
326			`current_state_3 <= ST_SIAS;`
327			`end if;`
328			`------------------`
329			`when others =>`
330			`current_state_3 <= ST_SIIS;`
331			`end case;`
332			`end if;`
333			`end process;`
334
335			`-- state machine process - C_STATE_4`
336			`process(pon, clk) begin`
337			`-- async reset`
338			`if pon='1' then`
339			`timer_b_1 <= 0;`
340			`current_state_4 <= ST_SRIS;`
341			`elsif rising_edge(clk) then`
342
343			`-- timer`
344			`if timer_b_1 < TIMER_B_MAX then`
345			`timer_b_1 <= timer_b_1 + 1;`
346			`end if;`
347
348			`-- state machine`
349			`case current_state_4 is`
350			`------------------`
351			`when ST_SRIS =>`
352			`if event4_1 then`
353			`-- no state change`
354			`elsif event4_2 then`
355			`timer_b_1 <= 0;`
356			`current_state_4 <= ST_SRAS;`
357			`elsif event4_3 then`
358			`current_state_4 <= ST_SRNS;`
359			`end if;`
360			`------------------`
361			`when ST_SRAS =>`
362			`if event4_1 then`
363			`current_state_4 <= ST_SRIS;`
364			`elsif event4_5 then`
365			`current_state_4 <= ST_SRNS;`
366			`end if;`
367			`------------------`
368			`when ST_SRNS =>`
369			`if event4_1 then`
370			`current_state_4 <= ST_SRIS;`
371			`elsif event4_4 then`
372			`timer_b_1 <= 0;`
373			`current_state_4 <= ST_SRAS;`
374			`end if;`
375			`------------------`
376			`when others =>`
377			`current_state_4 <= ST_SRIS;`
378			`end case;`
379			`end if;`
380			`end process;`
381
382			`-- state machine process - C_STATE_5`
383			`process(pon, clk) begin`
384			`-- async reset`
385			`if pon='1' then`
386			`current_state_5 <= ST_SNAS;`
387			`elsif rising_edge(clk) then`
388			`-- state machine`
389			`case current_state_5 is`
390			`------------------`
391			`when ST_SNAS =>`
392			`if event5_1 then`
393			`current_state_5 <= ST_SACS;`
394			`end if;`
395			`------------------`
396			`when ST_SACS =>`
397			`if event5_2 then`
398			`current_state_5 <= ST_SNAS;`
399			`end if;`
400			`------------------`
401			`when others =>`
402			`current_state_5 <= ST_SNAS;`
403			`end case;`
404			`end if;`
405			`end process;`
406
407			`-- events`
408			`event1_1 <= IFC_in='1' and current_state_5/=ST_SACS;`
409			`event1_2 <= (TCT_in='1' and TADS='1' and ACDS='1') or current_state_3=ST_SIAS;`
410			`event1_3 <= STRS='0';`
411			`event1_4 <= ATN_in='0';`
412			`event1_5 <= TCT_in='1' and TADS='0' and ACDS='1';`
413			`event1_6 <= SDYS='0' and STRS='0' and gts='1';`
414			`event1_7 <= rpp='1';`
415			`event1_8 <= timer_T9Expired and rpp='0';`
416			`event1_9 <= (tcs='1' and ANRS='1') or tca='1';`
417			`event1_10 <= timer_T7Expired;`
418			`event1_11 <= timer_T6Expired;`
419			`event1_12 <= rpp='0';`
420
421			`event2_1 <= SRQ_in='1';`
422			`event2_2 <= SRQ_in='0';`
423
424			`event3_1 <= current_state_5/=ST_SACS;`
425			`event3_2 <= current_state_5=ST_SACS and sic='1';`
426			`event3_3 <= current_state_5=ST_SACS and sic='0';`
427			`event3_4 <= sic='1';`
428			`event3_5 <= sic='0' and timer_T8Expired;`
429
430			`event4_1 <= current_state_5/=ST_SACS;`
431			`event4_2 <= current_state_5=ST_SACS and sre='1';`
432			`event4_3 <= current_state_5=ST_SACS and sre='0';`
433			`event4_4 <= sre='1';`
434			`event4_5 <= sre='0' and timer_T8_1Expired;`
435
436			`event5_1 <= rsc='1';`
437			`event5_2 <= rsc='0';`
438
439			`-- timers`
440			`timer_T6Expired <= timer_a >= TIMER_T6_TIMEOUT;`
441			`timer_T7Expired <= timer_a >= TIMER_T7_TIMEOUT;`
442			`timer_T9Expired <= timer_a >= TIMER_T9_TIMEOUT;`
443
444			`timer_T8Expired <= timer_b >= TIMER_T8_TIMEOUT;`
445			`timer_T8_1Expired <= timer_b_1 >= TIMER_T8_TIMEOUT;`
446
447
448			`CPPS <= to_stdl(current_state_1 = ST_CPPS);`
449			`CSRS <= to_stdl(current_state_2 = ST_CSRS);`
450			`CSBS <= to_stdl(current_state_1 = ST_CSBS);`
451			`CACS <= to_stdl(current_state_1 = ST_CACS);`
452			`SACS <= to_stdl(current_state_5 = ST_SACS);`
453
454			`-- CTRS`
455			`with current_state_1 select`
456			`CTRS <=`
457			`'1' when ST_CTRS,`
458			`'0' when others;`
459
460			`-- ATN`
461			`with current_state_1 select`
462			`ATN_out <=`
463			`'0' when ST_CIDS,`
464			`'0' when ST_CADS,`
465			`'0' when ST_CSBS,`
466			`'1' when others;`
467
468			`-- IDY_out`
469			`with current_state_1 select`
470			`IDY_out <=`
471			`'1' when ST_CPWS,`
472			`'1' when ST_CPPS,`
473			`'0' when others;`
474
475			`-- TCT`
476			`with current_state_1 select`
477			`TCT_out <=`
478			`'1' when ST_CTRS,`
479			`'0' when others;`
480
481			`-- IFC`
482			`with current_state_3 select`
483			`IFC_out <=`
484			`'1' when ST_SIAS,`
485			`'0' when others;`
486
487			`-- REN`
488			`with current_state_4 select`
489			`REN_out <=`
490			`'1' when ST_SRAS,`
491			`'0' when others;`
492
493			`end Behavioral;`
494