| 1 |
2 |
OmarMokhta |
Release 12.3 - xst M.70d (lin)
|
| 2 |
|
|
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
| 3 |
|
|
-->
|
| 4 |
|
|
Parameter TMPDIR set to xst/projnav.tmp
|
| 5 |
|
|
|
| 6 |
|
|
|
| 7 |
|
|
Total REAL time to Xst completion: 0.00 secs
|
| 8 |
|
|
Total CPU time to Xst completion: 0.04 secs
|
| 9 |
|
|
|
| 10 |
|
|
-->
|
| 11 |
|
|
Parameter xsthdpdir set to xst
|
| 12 |
|
|
|
| 13 |
|
|
|
| 14 |
|
|
Total REAL time to Xst completion: 0.00 secs
|
| 15 |
|
|
Total CPU time to Xst completion: 0.04 secs
|
| 16 |
|
|
|
| 17 |
|
|
-->
|
| 18 |
|
|
Reading design: FrameBuffer.prj
|
| 19 |
|
|
|
| 20 |
|
|
TABLE OF CONTENTS
|
| 21 |
|
|
1) Synthesis Options Summary
|
| 22 |
|
|
2) HDL Compilation
|
| 23 |
|
|
3) Design Hierarchy Analysis
|
| 24 |
|
|
4) HDL Analysis
|
| 25 |
|
|
5) HDL Synthesis
|
| 26 |
|
|
5.1) HDL Synthesis Report
|
| 27 |
|
|
6) Advanced HDL Synthesis
|
| 28 |
|
|
6.1) Advanced HDL Synthesis Report
|
| 29 |
|
|
7) Low Level Synthesis
|
| 30 |
|
|
8) Partition Report
|
| 31 |
|
|
9) Final Report
|
| 32 |
|
|
9.1) Device utilization summary
|
| 33 |
|
|
9.2) Partition Resource Summary
|
| 34 |
|
|
9.3) TIMING REPORT
|
| 35 |
|
|
|
| 36 |
|
|
|
| 37 |
|
|
=========================================================================
|
| 38 |
|
|
* Synthesis Options Summary *
|
| 39 |
|
|
=========================================================================
|
| 40 |
|
|
---- Source Parameters
|
| 41 |
|
|
Input File Name : "FrameBuffer.prj"
|
| 42 |
|
|
Input Format : mixed
|
| 43 |
|
|
Ignore Synthesis Constraint File : NO
|
| 44 |
|
|
|
| 45 |
|
|
---- Target Parameters
|
| 46 |
|
|
Output File Name : "FrameBuffer"
|
| 47 |
|
|
Output Format : NGC
|
| 48 |
|
|
Target Device : xa3s200-4-ftg256
|
| 49 |
|
|
|
| 50 |
|
|
---- Source Options
|
| 51 |
|
|
Top Module Name : FrameBuffer
|
| 52 |
|
|
Automatic FSM Extraction : YES
|
| 53 |
|
|
FSM Encoding Algorithm : Auto
|
| 54 |
|
|
Safe Implementation : No
|
| 55 |
|
|
FSM Style : LUT
|
| 56 |
|
|
RAM Extraction : Yes
|
| 57 |
|
|
RAM Style : Auto
|
| 58 |
|
|
ROM Extraction : Yes
|
| 59 |
|
|
Mux Style : Auto
|
| 60 |
|
|
Decoder Extraction : YES
|
| 61 |
|
|
Priority Encoder Extraction : Yes
|
| 62 |
|
|
Shift Register Extraction : YES
|
| 63 |
|
|
Logical Shifter Extraction : YES
|
| 64 |
|
|
XOR Collapsing : YES
|
| 65 |
|
|
ROM Style : Auto
|
| 66 |
|
|
Mux Extraction : Yes
|
| 67 |
|
|
Resource Sharing : YES
|
| 68 |
|
|
Asynchronous To Synchronous : NO
|
| 69 |
|
|
Multiplier Style : Auto
|
| 70 |
|
|
Automatic Register Balancing : No
|
| 71 |
|
|
|
| 72 |
|
|
---- Target Options
|
| 73 |
|
|
Add IO Buffers : YES
|
| 74 |
|
|
Global Maximum Fanout : 500
|
| 75 |
|
|
Add Generic Clock Buffer(BUFG) : 8
|
| 76 |
|
|
Register Duplication : YES
|
| 77 |
|
|
Slice Packing : YES
|
| 78 |
|
|
Optimize Instantiated Primitives : NO
|
| 79 |
|
|
Use Clock Enable : Yes
|
| 80 |
|
|
Use Synchronous Set : Yes
|
| 81 |
|
|
Use Synchronous Reset : Yes
|
| 82 |
|
|
Pack IO Registers into IOBs : Auto
|
| 83 |
|
|
Equivalent register Removal : YES
|
| 84 |
|
|
|
| 85 |
|
|
---- General Options
|
| 86 |
|
|
Optimization Goal : Speed
|
| 87 |
|
|
Optimization Effort : 1
|
| 88 |
|
|
Keep Hierarchy : No
|
| 89 |
|
|
Netlist Hierarchy : As_Optimized
|
| 90 |
|
|
RTL Output : Yes
|
| 91 |
|
|
Global Optimization : AllClockNets
|
| 92 |
|
|
Read Cores : YES
|
| 93 |
|
|
Write Timing Constraints : NO
|
| 94 |
|
|
Cross Clock Analysis : NO
|
| 95 |
|
|
Hierarchy Separator : /
|
| 96 |
|
|
Bus Delimiter : <>
|
| 97 |
|
|
Case Specifier : Maintain
|
| 98 |
|
|
Slice Utilization Ratio : 100
|
| 99 |
|
|
BRAM Utilization Ratio : 100
|
| 100 |
|
|
Verilog 2001 : YES
|
| 101 |
|
|
Auto BRAM Packing : NO
|
| 102 |
|
|
Slice Utilization Ratio Delta : 5
|
| 103 |
|
|
|
| 104 |
|
|
=========================================================================
|
| 105 |
|
|
|
| 106 |
|
|
|
| 107 |
|
|
=========================================================================
|
| 108 |
|
|
* HDL Compilation *
|
| 109 |
|
|
=========================================================================
|
| 110 |
|
|
Compiling vhdl file "/home/omar/LineFPGA/FrameBuffer2.vhd" in Library work.
|
| 111 |
|
|
Entity compiled.
|
| 112 |
|
|
Entity (Architecture ) compiled.
|
| 113 |
|
|
|
| 114 |
|
|
=========================================================================
|
| 115 |
|
|
* Design Hierarchy Analysis *
|
| 116 |
|
|
=========================================================================
|
| 117 |
|
|
Analyzing hierarchy for entity in library (architecture ).
|
| 118 |
|
|
|
| 119 |
|
|
|
| 120 |
|
|
=========================================================================
|
| 121 |
|
|
* HDL Analysis *
|
| 122 |
|
|
=========================================================================
|
| 123 |
|
|
Analyzing Entity in library (Architecture ).
|
| 124 |
|
|
WARNING:Xst:790 - "/home/omar/LineFPGA/FrameBuffer2.vhd" line 23: Index value(s) does not match array range, simulation mismatch.
|
