URL https://opencores.org/ocsvn/graphicsaccelerator/graphicsaccelerator/trunk

Subversion Repositories graphicsaccelerator

[/] [graphicsaccelerator/] [trunk/] [iseconfig/] [LineFPGA.projectmgr] - Blame information for rev 2

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         2
      
      
         VGA_Top - Behavioral (/home/omar/LineFPGA/VGA_Top.vhd)
      
      2
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f7000000020000000000000000000000000000000064ffffffff000000810000000000000002000001f70000000100000000000000000000000100000000
      true
      VGA_Top - Behavioral (/home/omar/LineFPGA/VGA_Top.vhd)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000011a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011a0000000100000000
      false
      
   
   
      
         1
      
      
      0
      0
      000000ff0000000000000001000000000000000001000000000000000000000000000000000000028a000000040101000100000000000000000000000064ffffffff0000008100000000000000040000005100000001000000000000002900000001000000000000008400000001000000000000018c0000000100000000
      false
      Bresenhamer.vhd
   
   
      
         1
         work
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000118000000010001000100000000000000000000000064ffffffff000000810000000000000001000001180000000100000000
      false
      work
   
   
      
         1
         Configure Target Device
         Implement Design
         Synthesize - XST
         User Constraints
      
      
         Generate Programming File
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000
      false
      Generate Programming File
   
   000000ff00000000000000020000014c0000011d01000000060100000002
   Implementation
   
      
         1
         User Constraints
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000011a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011a0000000100000000
      false
      
   
   
      
         2
      
      
         Bresenhammer_Sim - behavior (/home/omar/LineFPGA/Bresenhammer_Sim.vhd)
      
      1
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001ef000000020000000000000000000000000000000064ffffffff000000810000000000000002000001ef0000000100000000000000000000000100000000
      false
      Bresenhammer_Sim - behavior (/home/omar/LineFPGA/Bresenhammer_Sim.vhd)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000011a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011a0000000100000000
      false
      
   
   
      
         1
      
      
         Simulate Behavioral Model
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
      false
      Simulate Behavioral Model
   


Line No.	Rev	Author	Line
1	2	OmarMokhta
2
3
4
5
6
7
8
9			`2`
10
11
12			`VGA_Top - Behavioral (/home/omar/LineFPGA/VGA_Top.vhd)`
13
14			`2`
15			`0`
16			`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f7000000020000000000000000000000000000000064ffffffff000000810000000000000002000001f70000000100000000000000000000000100000000`
17			`true`
18			`VGA_Top - Behavioral (/home/omar/LineFPGA/VGA_Top.vhd)`
19
20
21
22			`1`
23			`Design Utilities`
24
25
26
27
28			`0`
29			`0`
30			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011a0000000100000000`
31			`false`
32
33
34
35
36			`1`
37
38
39			`0`
40			`0`
41			`000000ff0000000000000001000000000000000001000000000000000000000000000000000000028a000000040101000100000000000000000000000064ffffffff0000008100000000000000040000005100000001000000000000002900000001000000000000008400000001000000000000018c0000000100000000`
42			`false`
43			`Bresenhamer.vhd`
44
45
46
47			`1`
48			`work`
49
50
51			`0`
52			`0`
53			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000118000000010001000100000000000000000000000064ffffffff000000810000000000000001000001180000000100000000`
54			`false`
55			`work`
56
57
58
59			`1`
60			`Configure Target Device`
61			`Implement Design`
62			`Synthesize - XST`
63			`User Constraints`
64
65
66			`Generate Programming File`
67
68			`0`
69			`0`
70			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000`
71			`false`
72			`Generate Programming File`
73
74			`000000ff00000000000000020000014c0000011d01000000060100000002`
75			`Implementation`
76
77
78			`1`
79			`User Constraints`
80
81
82
83
84			`0`
85			`0`
86			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011a0000000100000000`
87			`false`
88
89
90
91
92			`2`
93
94
95			`Bresenhammer_Sim - behavior (/home/omar/LineFPGA/Bresenhammer_Sim.vhd)`
96
97			`1`
98			`0`
99			`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001ef000000020000000000000000000000000000000064ffffffff000000810000000000000002000001ef0000000100000000000000000000000100000000`
100			`false`
101			`Bresenhammer_Sim - behavior (/home/omar/LineFPGA/Bresenhammer_Sim.vhd)`
102
103
104
105			`1`
106			`Design Utilities`
107
108
109
110
111			`0`
112			`0`
113			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000011a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011a0000000100000000`
114			`false`
115
116
117
118
119			`1`
120
121
122			`Simulate Behavioral Model`
123
124			`0`
125			`0`
126			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
127			`false`
128			`Simulate Behavioral Model`
129
130

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Subversion Repositories graphicsaccelerator

[/] [graphicsaccelerator/] [trunk/] [iseconfig/] [LineFPGA.projectmgr] - Blame information for rev 2