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/******************************************************
    HD63701V0(Mode6) Compatible Processor Core
              Written by Tsuyoshi HASEGAWA 2013-14
*******************************************************/
module HD63701V0_M6
(
        input                                   CLKx2,  // XTAL/EXTAL (200K~2.0MHz)
 
        input                                   RST,            // RES
        input                                   NMI,            // NMI
        input                                   IRQ,            // IRQ1
 
        output                          RW,             // CS2
        output    [15:0] AD,             //  AS ? {PO4,PO3}
        output          [7:0]    DO,             // ~AS ? {PO3}
        input           [7:0] DI,                //       {PI3}
 
        input                   [7:0]    PI1,            // Port1 IN
        output          [7:0]    PO1,            //                      OUT
 
        input                   [4:0]    PI2,            // Port2 IN
        output          [4:0]    PO2,            //                      OUT
 
        // for DEBUG
        output      [6:0] phase
);
 
// Built-In Instruction ROM
wire en_birom = (AD[15:12]==4'b1111);                   // $F000-$FFFF
wire [7:0] biromd;
MCU_BIROM irom( CLKx2, AD[11:0], biromd );
 
 
// Built-In WorkRAM
wire              en_biram;
wire [7:0] biramd;
HD63701_BIRAM biram( CLKx2, AD, RW, DO, en_biram, biramd );
 
 
// Built-In I/O Ports
wire              en_biio;
wire [7:0] biiod;
HD63701_IOPort iopt( RST, CLKx2, AD, RW, DO, en_biio, biiod, PI1, PI2, PO1, PO2 );
 
 
// Built-In Timer
wire              irq2;
wire [3:0] irq2v;
wire              en_bitim;
wire [7:0] bitimd;
HD63701_Timer timer( RST, CLKx2, AD, RW, DO, irq2, irq2v, en_bitim, bitimd );
 
 
// Built-In Devices Data Selector
wire [7:0] biddi;
HD63701_BIDSEL bidsel
(
        biddi,
        en_birom, biromd,
        en_biram, biramd,
        en_biio , biiod,
        en_bitim, bitimd,
        DI
);
 
// Processor Core
HD63701_Core core
(
        .CLKx2(CLKx2),.RST(RST),
        .NMI(NMI),.IRQ(IRQ),.IRQ2(irq2),.IRQ2V(irq2v),
        .RW(RW),.AD(AD),.DO(DO),.DI(biddi),
        .PH(phase[5:0])
);
assign phase[6] = irq2;
 
endmodule
 
 
module HD63701_BIDSEL
(
        output [7:0] o,
 
        input e0, input [7:0] d0,
        input e1, input [7:0] d1,
        input e2, input [7:0] d2,
        input e3, input [7:0] d3,
 
                                 input [7:0] dx
);
 
assign o =      e0 ? d0 :
                                e1 ? d1 :
                                e2 ? d2 :
                                e3 ? d3 :
                                dx;
 
endmodule
 
 
module HD63701_BIRAM
(
        input                           mcu_clx2,
        input [15:0]     mcu_ad,
        input                           mcu_wr,
        input  [7:0]     mcu_do,
        output                  en_biram,
        output reg [7:0] biramd
);
 
assign en_biram = (mcu_ad[15: 7]==9'b000000001);        // $0080-$00FF
wire [6:0] biad = mcu_ad[6:0];
 
reg [7:0] bimem[0:127];
always @( posedge mcu_clx2 ) begin
        if (en_biram & mcu_wr) bimem[biad] <= mcu_do;
        else biramd <= bimem[biad];
end
 
endmodule
 
 
module HD63701_IOPort
(
        input                    mcu_rst,
        input                    mcu_clx2,
        input [15:0] mcu_ad,
        input            mcu_wr,
        input  [7:0] mcu_do,
 
        output           en_io,
        output [7:0] iod,
 
        input  [7:0] PI1,
        input  [3:0] PI2,
 
        output reg [7:0] PO1,
        output reg [3:0] PO2
);
 
always @( posedge mcu_clx2 or posedge mcu_rst ) begin
        if (mcu_rst) begin
                PO1 <= 8'hFF;
                PO2 <= 4'hF;
        end
        else begin
                if (mcu_wr) begin
                        if (mcu_ad==16'h2) PO1 <= mcu_do;
                        if (mcu_ad==16'h3) PO2 <= mcu_do[3:0];
                end
        end
end
 
assign en_io = (mcu_ad==16'h2)|(mcu_ad==16'h3);
assign   iod = (mcu_ad==16'h2) ? PI1 : {4'hF,PI2};
 
endmodule
 
 
module HD63701_Timer
(
        input                    mcu_rst,
        input                    mcu_clx2,
        input [15:0] mcu_ad,
        input            mcu_wr,
        input  [7:0] mcu_do,
 
        output           mcu_irq2,
        output [3:0] mcu_irq2v,
 
        output           en_timer,
        output [7:0] timerd
);
 
reg               oci, oce;
reg [15:0] ocr, icr;
reg [16:0] frc;
reg  [7:0] frt;
reg  [7:0] rmc, rg5;
 
always @( posedge mcu_clx2 or posedge mcu_rst ) begin
        if (mcu_rst) begin
                oce <= 0;
                ocr <= 16'hFFFF;
                icr <= 16'hFFFF;
                frc <= 0;
                frt <= 0;
                rmc <= 8'h40;
                rg5 <= 0;
        end
        else begin
                frc <= frc+1;
                if (mcu_wr) begin
                        case (mcu_ad)
                                16'h05: rg5 <= mcu_do;
                                16'h08: oce <= mcu_do[3];
                                16'h09: frt <= mcu_do;
                                16'h0A: frc <= {frt,mcu_do,1'h0};
                                16'h0B: ocr[15:8] <= mcu_do;
                                16'h0C: ocr[ 7:0] <= mcu_do;
                                16'h0D: icr[15:8] <= mcu_do;
                                16'h0E: icr[ 7:0] <= mcu_do;
                                16'h14: rmc <= {mcu_do[7:6],6'h0};
                                default:;
                        endcase
                end
        end
end
 
always @( negedge mcu_clx2 or posedge mcu_rst ) begin
        if (mcu_rst) begin
                oci <= 0;
        end
        else begin
                case (mcu_ad)
                        16'h0B: oci <= 0;
                        16'h0C: oci <= 0;
                        default: if (frc[16:1]==ocr) oci <= 1'b1;
                endcase
        end
end
 
assign mcu_irq2  = oci & oce;
assign mcu_irq2v = 4'h4;
 
assign en_timer =       (mcu_ad==16'h05)|((mcu_ad>=16'h8)&(mcu_ad<=16'hE))|(mcu_ad==16'h14);
 
assign   timerd = (mcu_ad==16'h05) ? rg5 :
                                                (mcu_ad==16'h08) ? {1'b0,oci,2'b10,oce,3'b000}:
                                                (mcu_ad==16'h09) ? frc[16:9] :
                                                (mcu_ad==16'h0A) ? frc[ 8:1] :
                                                (mcu_ad==16'h0B) ? ocr[15:8] :
                                                (mcu_ad==16'h0C) ? ocr[ 7:0] :
                                                (mcu_ad==16'h0D) ? icr[15:8] :
                                                (mcu_ad==16'h0E) ? icr[ 7:0] :
                                                (mcu_ad==16'h14) ? rmc :
                                                8'h0;
 
endmodule
 

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[/] [hd63701/] [trunk/] [HD63701.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	thasega	`/******************************************************`
2			`HD63701V0(Mode6) Compatible Processor Core`
3			`Written by Tsuyoshi HASEGAWA 2013-14`
4			`*******************************************************/`
5			`module HD63701V0_M6`
6			`(`
7			`input CLKx2, // XTAL/EXTAL (200K~2.0MHz)`
8
9			`input RST, // RES`
10			`input NMI, // NMI`
11			`input IRQ, // IRQ1`
12
13			`output RW, // CS2`
14			`output [15:0] AD, // AS ? {PO4,PO3}`
15			`output [7:0] DO, // ~AS ? {PO3}`
16			`input [7:0] DI, // {PI3}`
17
18			`input [7:0] PI1, // Port1 IN`
19			`output [7:0] PO1, // OUT`
20
21			`input [4:0] PI2, // Port2 IN`
22			`output [4:0] PO2, // OUT`
23
24			`// for DEBUG`
25			`output [6:0] phase`
26			`);`
27
28			`// Built-In Instruction ROM`
29			`wire en_birom = (AD[15:12]==4'b1111); // $F000-$FFFF`
30			`wire [7:0] biromd;`
31			`MCU_BIROM irom( CLKx2, AD[11:0], biromd );`
32
33
34			`// Built-In WorkRAM`
35			`wire en_biram;`
36			`wire [7:0] biramd;`
37			`HD63701_BIRAM biram( CLKx2, AD, RW, DO, en_biram, biramd );`
38
39
40			`// Built-In I/O Ports`
41			`wire en_biio;`
42			`wire [7:0] biiod;`
43			`HD63701_IOPort iopt( RST, CLKx2, AD, RW, DO, en_biio, biiod, PI1, PI2, PO1, PO2 );`
44
45
46			`// Built-In Timer`
47			`wire irq2;`
48			`wire [3:0] irq2v;`
49			`wire en_bitim;`
50			`wire [7:0] bitimd;`
51			`HD63701_Timer timer( RST, CLKx2, AD, RW, DO, irq2, irq2v, en_bitim, bitimd );`
52
53
54			`// Built-In Devices Data Selector`
55			`wire [7:0] biddi;`
56			`HD63701_BIDSEL bidsel`
57			`(`
58			`biddi,`
59			`en_birom, biromd,`
60			`en_biram, biramd,`
61			`en_biio , biiod,`
62			`en_bitim, bitimd,`
63			`DI`
64			`);`
65
66			`// Processor Core`
67			`HD63701_Core core`
68			`(`
69			`.CLKx2(CLKx2),.RST(RST),`
70			`.NMI(NMI),.IRQ(IRQ),.IRQ2(irq2),.IRQ2V(irq2v),`
71			`.RW(RW),.AD(AD),.DO(DO),.DI(biddi),`
72			`.PH(phase[5:0])`
73			`);`
74			`assign phase[6] = irq2;`
75
76			`endmodule`
77
78
79			`module HD63701_BIDSEL`
80			`(`
81			`output [7:0] o,`
82
83			`input e0, input [7:0] d0,`
84			`input e1, input [7:0] d1,`
85			`input e2, input [7:0] d2,`
86			`input e3, input [7:0] d3,`
87
88			`input [7:0] dx`
89			`);`
90
91			`assign o = e0 ? d0 :`
92			`e1 ? d1 :`
93			`e2 ? d2 :`
94			`e3 ? d3 :`
95			`dx;`
96
97			`endmodule`
98
99
100			`module HD63701_BIRAM`
101			`(`
102			`input mcu_clx2,`
103			`input [15:0] mcu_ad,`
104			`input mcu_wr,`
105			`input [7:0] mcu_do,`
106			`output en_biram,`
107			`output reg [7:0] biramd`
108			`);`
109
110			`assign en_biram = (mcu_ad[15: 7]==9'b000000001); // $0080-$00FF`
111			`wire [6:0] biad = mcu_ad[6:0];`
112
113			`reg [7:0] bimem[0:127];`
114			`always @( posedge mcu_clx2 ) begin`
115			`if (en_biram & mcu_wr) bimem[biad] <= mcu_do;`
116			`else biramd <= bimem[biad];`
117			`end`
118
119			`endmodule`
120
121
122			`module HD63701_IOPort`
123			`(`
124			`input mcu_rst,`
125			`input mcu_clx2,`
126			`input [15:0] mcu_ad,`
127			`input mcu_wr,`
128			`input [7:0] mcu_do,`
129
130			`output en_io,`
131			`output [7:0] iod,`
132
133			`input [7:0] PI1,`
134			`input [3:0] PI2,`
135
136			`output reg [7:0] PO1,`
137			`output reg [3:0] PO2`
138			`);`
139
140			`always @( posedge mcu_clx2 or posedge mcu_rst ) begin`
141			`if (mcu_rst) begin`
142			`PO1 <= 8'hFF;`
143			`PO2 <= 4'hF;`
144			`end`
145			`else begin`
146			`if (mcu_wr) begin`
147			`if (mcu_ad==16'h2) PO1 <= mcu_do;`
148			`if (mcu_ad==16'h3) PO2 <= mcu_do[3:0];`
149			`end`
150			`end`
151			`end`
152
153			`assign en_io = (mcu_ad==16'h2)\|(mcu_ad==16'h3);`
154			`assign iod = (mcu_ad==16'h2) ? PI1 : {4'hF,PI2};`
155
156			`endmodule`
157
158
159			`module HD63701_Timer`
160			`(`
161			`input mcu_rst,`
162			`input mcu_clx2,`
163			`input [15:0] mcu_ad,`
164			`input mcu_wr,`
165			`input [7:0] mcu_do,`
166
167			`output mcu_irq2,`
168			`output [3:0] mcu_irq2v,`
169
170			`output en_timer,`
171			`output [7:0] timerd`
172			`);`
173
174			`reg oci, oce;`
175			`reg [15:0] ocr, icr;`
176			`reg [16:0] frc;`
177			`reg [7:0] frt;`
178			`reg [7:0] rmc, rg5;`
179
180			`always @( posedge mcu_clx2 or posedge mcu_rst ) begin`
181			`if (mcu_rst) begin`
182			`oce <= 0;`
183			`ocr <= 16'hFFFF;`
184			`icr <= 16'hFFFF;`
185			`frc <= 0;`
186			`frt <= 0;`
187			`rmc <= 8'h40;`
188			`rg5 <= 0;`
189			`end`
190			`else begin`
191			`frc <= frc+1;`
192			`if (mcu_wr) begin`
193			`case (mcu_ad)`
194			`16'h05: rg5 <= mcu_do;`
195			`16'h08: oce <= mcu_do[3];`
196			`16'h09: frt <= mcu_do;`
197			`16'h0A: frc <= {frt,mcu_do,1'h0};`
198			`16'h0B: ocr[15:8] <= mcu_do;`
199			`16'h0C: ocr[ 7:0] <= mcu_do;`
200			`16'h0D: icr[15:8] <= mcu_do;`
201			`16'h0E: icr[ 7:0] <= mcu_do;`
202			`16'h14: rmc <= {mcu_do[7:6],6'h0};`
203			`default:;`
204			`endcase`
205			`end`
206			`end`
207			`end`
208
209			`always @( negedge mcu_clx2 or posedge mcu_rst ) begin`
210			`if (mcu_rst) begin`
211			`oci <= 0;`
212			`end`
213			`else begin`
214			`case (mcu_ad)`
215			`16'h0B: oci <= 0;`
216			`16'h0C: oci <= 0;`
217			`default: if (frc[16:1]==ocr) oci <= 1'b1;`
218			`endcase`
219			`end`
220			`end`
221
222			`assign mcu_irq2 = oci & oce;`
223			`assign mcu_irq2v = 4'h4;`
224
225			`assign en_timer = (mcu_ad==16'h05)\|((mcu_ad>=16'h8)&(mcu_ad<=16'hE))\|(mcu_ad==16'h14);`
226
227			`assign timerd = (mcu_ad==16'h05) ? rg5 :`
228			`(mcu_ad==16'h08) ? {1'b0,oci,2'b10,oce,3'b000}:`
229			`(mcu_ad==16'h09) ? frc[16:9] :`
230			`(mcu_ad==16'h0A) ? frc[ 8:1] :`
231			`(mcu_ad==16'h0B) ? ocr[15:8] :`
232			`(mcu_ad==16'h0C) ? ocr[ 7:0] :`
233			`(mcu_ad==16'h0D) ? icr[15:8] :`
234			`(mcu_ad==16'h0E) ? icr[ 7:0] :`
235			`(mcu_ad==16'h14) ? rmc :`
236			`8'h0;`
237
238			`endmodule`
239