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[/] [hd63701/] [trunk/] [HD63701_SEQ.v] - Blame information for rev 2

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/***************************************************************************
       This file is part of "HD63701V0 Compatible Processor Core".
****************************************************************************/
`timescale 1ps / 1ps
 
`include "HD63701_defs.i"
 
module HD63701_SEQ
(
        input                                           CLK,
        input                                           RST,
 
        input                                           NMI,
        input                                           IRQ,
 
        input                                           IRQ2,
        input   [3:0]                    IRQ2V,
 
        input   [7:0]                    DI,
 
        output `mcwidth         mcout,
        input           [7:0]                    vect,
        input                                           inte,
        output                                  fncu,
 
        output  [5:0]            PH
);
 
`define MC_SEI {`mcSCB,   `bfI    ,`mcrC,`mcpN,`amPC,`pcN}
`define MC_YLD {`mcNOP,`mcrn,`mcrn,`mcrn,`mcpK,`amPC,`pcN}
 
reg [7:0]   opcode;
reg `mcwidth mcode;
reg  mcside;
 
 
reg  pNMI, pIRQ, pIR2;
 
reg  [2:0]  fINT;
wire bIRQ  = fINT[1] & inte;
wire bIRQ2 = fINT[0] & inte;
 
wire              bINT = fINT[2]|bIRQ|bIRQ2;
wire [7:0] vINT = fINT[2] ? `vaNMI :
                                                bIRQ    ? `vaIRQ :
                                                bIRQ2   ? {4'hF,IRQ2V} :
                                                0;
 
function [2:0] INTUpd;
input [2:0] n;
        case(n)
        3'b000: INTUpd = 3'b000;
        3'b001: INTUpd = 3'b000;
        3'b010: INTUpd = 3'b000;
        3'b011: INTUpd = 3'b001;
        3'b100: INTUpd = 3'b000;
        3'b101: INTUpd = 3'b001;
        3'b110: INTUpd = 3'b010;
        3'b111: INTUpd = 3'b011;
        endcase
endfunction
 
 
reg [5:0] PHASE;
always @( posedge CLK or posedge RST ) begin
        if (RST) begin
                fINT <= 0;
                pIRQ <= 0;
                pNMI <= 0;
                pIR2 <= 0;
 
                opcode <= 0;
                mcode  <= 0;
                mcside <= 0;
        end
        else begin
 
                // Capture Interrupt signal edge
                if ((pNMI^NMI)&NMI)   fINT[2] <= 1'b1; pNMI <= NMI;
                if ((pIRQ^IRQ)&IRQ)   fINT[1] <= 1'b1; pIRQ <= IRQ;
                if ((pIR2^IRQ2)&IRQ2) fINT[0] <= 1'b1; pIR2 <= IRQ2;
 
 
                case (PHASE)
 
                // Reset
                `phRST :        mcside <= 1;
 
                // Load Vector
                `phVECT: mcside <= 1;
 
                // Execute
                `phEXEC: begin
                                                opcode <= DI;
                                                if ( bINT & (opcode[7:1]!=7'b0000111) ) begin
                                                        mcside <= 0;
                                                        mcode  <= {`mcINT,vINT,`mcrn,`mcpI,`amPC,`pcN};
                                                        fINT   <= INTUpd(fINT);
                                                end
                                                else mcside <= 1;
                                        end
 
                // Interrupt (TRAP/IRQ/NMI/SWI/WAI)
                `phINTR:  mcside <= 1;
                `phINTR8: begin
                                                mcside <= 0;
                                                if (vect==`vaWAI) begin
                                                        if (bINT) begin
                                                                mcode  <= `MC_SEI;
                                                                opcode <= vINT;
                                                                fINT   <= INTUpd(fINT);
                                                        end
                                                        else mcode <= `MC_YLD;
                                                end
                                                else begin
                                                        opcode <= vect;
                                                        mcode  <= `MC_SEI;
                                                end
                                         end
                `phINTR9: mcode <= {`mcLDV, opcode,`mcrn,`mcpV,`amE0,`pcN};     //(Load Vector)
 
                // Sleep
                `phSLEP: begin
                                                mcside <= 0;
                                                if (bINT) begin
                                                        mcode  <= {`mcINT,vINT,`mcrn,`mcpI,`amPC,`pcN};
                                                        fINT   <= INTUpd(fINT);
                                                end
                                                else mcode <= `MC_YLD;
                                        end
 
                // HALT (Bug in MicroCode)
                `phHALT: $stop;
 
                default:;
                endcase
        end
end
 
// Update Phase
wire [2:0] mcph = mcout[6:4];
always @( negedge CLK or posedge RST ) begin
        if (RST) PHASE <= 0;
        else begin
                case (mcph)
                        `mcpN: PHASE <= PHASE+6'h1;
                        `mcp0: PHASE <=`phEXEC;
                        `mcpI: PHASE <=`phINTR;
                        `mcpV: PHASE <=`phVECT;
                        `mcpH: PHASE <=`phHALT;
                        `mcpS: PHASE <=`phSLEP;
                 default: PHASE <= PHASE;
                endcase
        end
end
assign PH = PHASE;
 
// Output MicroCode
wire `mcwidth mcoder;
HD63701_MCROM mcr( CLK, PHASE, (PHASE==`phEXEC) ? DI : opcode, mcoder );
assign mcout = mcside ? mcoder : mcode;
 
assign fncu = ( opcode[7:4]==4'h2)|
                                  ((opcode[7:4]==4'h3)&(opcode[3:0]!=4'hD));
 
endmodule
 

Line No.	Rev	Author	Line
1	2	thasega	`/***************************************************************************`
2			`This file is part of "HD63701V0 Compatible Processor Core".`
3			`****************************************************************************/`
4			`timescale 1ps / 1ps
5
6			`include "HD63701_defs.i"
7
8			`module HD63701_SEQ`
9			`(`
10			`input CLK,`
11			`input RST,`
12
13			`input NMI,`
14			`input IRQ,`
15
16			`input IRQ2,`
17			`input [3:0] IRQ2V,`
18
19			`input [7:0] DI,`
20
21			output `mcwidth mcout,
22			`input [7:0] vect,`
23			`input inte,`
24			`output fncu,`
25
26			`output [5:0] PH`
27			`);`
28
29			`define MC_SEI {`mcSCB, `bfI ,`mcrC,`mcpN,`amPC,`pcN}
30			`define MC_YLD {`mcNOP,`mcrn,`mcrn,`mcrn,`mcpK,`amPC,`pcN}
31
32			`reg [7:0] opcode;`
33			reg `mcwidth mcode;
34			`reg mcside;`
35
36
37			`reg pNMI, pIRQ, pIR2;`
38
39			`reg [2:0] fINT;`
40			`wire bIRQ = fINT[1] & inte;`
41			`wire bIRQ2 = fINT[0] & inte;`
42
43			`wire bINT = fINT[2]\|bIRQ\|bIRQ2;`
44			wire [7:0] vINT = fINT[2] ? `vaNMI :
45			bIRQ ? `vaIRQ :
46			`bIRQ2 ? {4'hF,IRQ2V} :`
47			`0;`
48
49			`function [2:0] INTUpd;`
50			`input [2:0] n;`
51			`case(n)`
52			`3'b000: INTUpd = 3'b000;`
53			`3'b001: INTUpd = 3'b000;`
54			`3'b010: INTUpd = 3'b000;`
55			`3'b011: INTUpd = 3'b001;`
56			`3'b100: INTUpd = 3'b000;`
57			`3'b101: INTUpd = 3'b001;`
58			`3'b110: INTUpd = 3'b010;`
59			`3'b111: INTUpd = 3'b011;`
60			`endcase`
61			`endfunction`
62
63
64			`reg [5:0] PHASE;`
65			`always @( posedge CLK or posedge RST ) begin`
66			`if (RST) begin`
67			`fINT <= 0;`
68			`pIRQ <= 0;`
69			`pNMI <= 0;`
70			`pIR2 <= 0;`
71
72			`opcode <= 0;`
73			`mcode <= 0;`
74			`mcside <= 0;`
75			`end`
76			`else begin`
77
78			`// Capture Interrupt signal edge`
79			`if ((pNMI^NMI)&NMI) fINT[2] <= 1'b1; pNMI <= NMI;`
80			`if ((pIRQ^IRQ)&IRQ) fINT[1] <= 1'b1; pIRQ <= IRQ;`
81			`if ((pIR2^IRQ2)&IRQ2) fINT[0] <= 1'b1; pIR2 <= IRQ2;`
82
83
84			`case (PHASE)`
85
86			`// Reset`
87			`phRST : mcside <= 1;
88
89			`// Load Vector`
90			`phVECT: mcside <= 1;
91
92			`// Execute`
93			`phEXEC: begin
94			`opcode <= DI;`
95			`if ( bINT & (opcode[7:1]!=7'b0000111) ) begin`
96			`mcside <= 0;`
97			mcode <= {`mcINT,vINT,`mcrn,`mcpI,`amPC,`pcN};
98			`fINT <= INTUpd(fINT);`
99			`end`
100			`else mcside <= 1;`
101			`end`
102
103			`// Interrupt (TRAP/IRQ/NMI/SWI/WAI)`
104			`phINTR: mcside <= 1;
105			`phINTR8: begin
106			`mcside <= 0;`
107			if (vect==`vaWAI) begin
108			`if (bINT) begin`
109			mcode <= `MC_SEI;
110			`opcode <= vINT;`
111			`fINT <= INTUpd(fINT);`
112			`end`
113			else mcode <= `MC_YLD;
114			`end`
115			`else begin`
116			`opcode <= vect;`
117			mcode <= `MC_SEI;
118			`end`
119			`end`
120			`phINTR9: mcode <= {`mcLDV, opcode,`mcrn,`mcpV,`amE0,`pcN}; //(Load Vector)
121
122			`// Sleep`
123			`phSLEP: begin
124			`mcside <= 0;`
125			`if (bINT) begin`
126			mcode <= {`mcINT,vINT,`mcrn,`mcpI,`amPC,`pcN};
127			`fINT <= INTUpd(fINT);`
128			`end`
129			else mcode <= `MC_YLD;
130			`end`
131
132			`// HALT (Bug in MicroCode)`
133			`phHALT: $stop;
134
135			`default:;`
136			`endcase`
137			`end`
138			`end`
139
140			`// Update Phase`
141			`wire [2:0] mcph = mcout[6:4];`
142			`always @( negedge CLK or posedge RST ) begin`
143			`if (RST) PHASE <= 0;`
144			`else begin`
145			`case (mcph)`
146			`mcpN: PHASE <= PHASE+6'h1;
147			`mcp0: PHASE <=`phEXEC;
148			`mcpI: PHASE <=`phINTR;
149			`mcpV: PHASE <=`phVECT;
150			`mcpH: PHASE <=`phHALT;
151			`mcpS: PHASE <=`phSLEP;
152			`default: PHASE <= PHASE;`
153			`endcase`
154			`end`
155			`end`
156			`assign PH = PHASE;`
157
158			`// Output MicroCode`
159			wire `mcwidth mcoder;
160			HD63701_MCROM mcr( CLK, PHASE, (PHASE==`phEXEC) ? DI : opcode, mcoder );
161			`assign mcout = mcside ? mcoder : mcode;`
162
163			`assign fncu = ( opcode[7:4]==4'h2)\|`
164			`((opcode[7:4]==4'h3)&(opcode[3:0]!=4'hD));`
165
166			`endmodule`
167

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[/] [hd63701/] [trunk/] [HD63701_SEQ.v] - Blame information for rev 2