| 1 |
18 |
umairsiddi |
# Generated from HPC16.g4 by ANTLR 4.5.1
|
| 2 |
|
|
# encoding: utf-8
|
| 3 |
|
|
from __future__ import print_function
|
| 4 |
|
|
from antlr4 import *
|
| 5 |
|
|
from io import StringIO
|
| 6 |
|
|
|
| 7 |
|
|
def serializedATN():
|
| 8 |
|
|
with StringIO() as buf:
|
| 9 |
|
|
buf.write(u"\3\u0430\ud6d1\u8206\uad2d\u4417\uaef1\u8d80\uaadd\3")
|
| 10 |
|
|
buf.write(u"R\u017b\4\2\t\2\4\3\t\3\4\4\t\4\3\2\6\2\n\n\2\r\2\16")
|
| 11 |
|
|
buf.write(u"\2\13\3\3\5\3\17\n\3\3\3\3\3\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 12 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 13 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 14 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 15 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 16 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 17 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 18 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 19 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 20 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 21 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 22 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 23 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 24 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 25 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 26 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 27 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 28 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 29 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 30 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 31 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 32 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 33 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 34 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 35 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 36 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 37 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 38 |
|
|
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4")
|
| 39 |
|
|
buf.write(u"\3\4\5\4\u0179\n\4\3\4\2\2\5\2\4\6\2\2\u01df\2\t\3\2")
|
| 40 |
|
|
buf.write(u"\2\2\4\16\3\2\2\2\6\u0178\3\2\2\2\b\n\5\4\3\2\t\b\3\2")
|
| 41 |
|
|
buf.write(u"\2\2\n\13\3\2\2\2\13\t\3\2\2\2\13\f\3\2\2\2\f\3\3\2\2")
|
| 42 |
|
|
buf.write(u"\2\r\17\5\6\4\2\16\r\3\2\2\2\16\17\3\2\2\2\17\20\3\2")
|
| 43 |
|
|
buf.write(u"\2\2\20\21\7R\2\2\21\5\3\2\2\2\22\23\7\3\2\2\23\24\7")
|
| 44 |
|
|
buf.write(u"M\2\2\24\25\7\4\2\2\25\u0179\7M\2\2\26\27\7\3\2\2\27")
|
| 45 |
|
|
buf.write(u"\30\7O\2\2\30\31\7\4\2\2\31\u0179\7M\2\2\32\33\7\3\2")
|
| 46 |
|
|
buf.write(u"\2\33\34\7M\2\2\34\35\7\4\2\2\35\u0179\7O\2\2\36\37\7")
|
| 47 |
|
|
buf.write(u"\5\2\2\37 \7M\2\2 !\7\4\2\2!\"\7\6\2\2\"#\7M\2\2#\u0179")
|
| 48 |
|
|
buf.write(u"\7\7\2\2$%\7\5\2\2%&\7M\2\2&\'\7\4\2\2\'(\7\6\2\2()\7")
|
| 49 |
|
|
buf.write(u"M\2\2)*\7\b\2\2*+\7N\2\2+\u0179\7\7\2\2,-\7\5\2\2-.\7")
|
| 50 |
|
|
buf.write(u"M\2\2./\7\4\2\2/\60\7\6\2\2\60\61\7O\2\2\61\u0179\7\7")
|
| 51 |
|
|
buf.write(u"\2\2\62\63\7\5\2\2\63\64\7M\2\2\64\65\7\4\2\2\65\66\7")
|
| 52 |
|
|
buf.write(u"\6\2\2\66\67\7O\2\2\678\7\b\2\289\7N\2\29\u0179\7\7\2")
|
| 53 |
|
|
buf.write(u"\2:;\7\t\2\2;<\7M\2\2<=\7\4\2\2=>\7\6\2\2>?\7M\2\2?\u0179")
|
| 54 |
|
|
buf.write(u"\7\7\2\2@A\7\t\2\2AB\7M\2\2BC\7\4\2\2CD\7\6\2\2DE\7M")
|
| 55 |
|
|
buf.write(u"\2\2EF\7\b\2\2FG\7N\2\2G\u0179\7\7\2\2HI\7\t\2\2IJ\7")
|
| 56 |
|
|
buf.write(u"M\2\2JK\7\4\2\2KL\7\6\2\2LM\7O\2\2M\u0179\7\7\2\2NO\7")
|
| 57 |
|
|
buf.write(u"\t\2\2OP\7M\2\2PQ\7\4\2\2QR\7\6\2\2RS\7O\2\2ST\7\b\2")
|
| 58 |
|
|
buf.write(u"\2TU\7N\2\2U\u0179\7\7\2\2VW\7\n\2\2WX\7M\2\2XY\7\4\2")
|
| 59 |
|
|
buf.write(u"\2YZ\7\6\2\2Z[\7M\2\2[\u0179\7\7\2\2\\]\7\n\2\2]^\7M")
|
| 60 |
|
|
buf.write(u"\2\2^_\7\4\2\2_`\7\6\2\2`a\7M\2\2ab\7\b\2\2bc\7N\2\2")
|
| 61 |
|
|
buf.write(u"c\u0179\7\7\2\2de\7\13\2\2ef\7M\2\2fg\7\4\2\2gh\7\6\2")
|
| 62 |
|
|
buf.write(u"\2hi\7M\2\2i\u0179\7\7\2\2jk\7\13\2\2kl\7M\2\2lm\7\4")
|
| 63 |
|
|
buf.write(u"\2\2mn\7\6\2\2no\7M\2\2op\7\b\2\2pq\7N\2\2q\u0179\7\7")
|
| 64 |
|
|
buf.write(u"\2\2rs\7\f\2\2st\7M\2\2tu\7\4\2\2uv\7\6\2\2vw\7M\2\2")
|
| 65 |
|
|
buf.write(u"w\u0179\7\7\2\2xy\7\f\2\2yz\7M\2\2z{\7\4\2\2{|\7\6\2")
|
| 66 |
|
|
buf.write(u"\2|}\7M\2\2}~\7\b\2\2~\177\7N\2\2\177\u0179\7\7\2\2\u0080")
|
| 67 |
|
|
buf.write(u"\u0081\7\r\2\2\u0081\u0082\7M\2\2\u0082\u0083\7\4\2\2")
|
| 68 |
|
|
buf.write(u"\u0083\u0179\7N\2\2\u0084\u0085\7\r\2\2\u0085\u0086\7")
|
| 69 |
|
|
buf.write(u"O\2\2\u0086\u0087\7\4\2\2\u0087\u0179\7N\2\2\u0088\u0089")
|
| 70 |
|
|
buf.write(u"\7\16\2\2\u0089\u0179\7M\2\2\u008a\u008b\7\17\2\2\u008b")
|
| 71 |
|
|
buf.write(u"\u0179\7M\2\2\u008c\u008d\7\20\2\2\u008d\u008e\7M\2\2")
|
| 72 |
|
|
buf.write(u"\u008e\u008f\7\4\2\2\u008f\u0179\7M\2\2\u0090\u0091\7")
|
| 73 |
|
|
buf.write(u"\21\2\2\u0091\u0092\7M\2\2\u0092\u0093\7\4\2\2\u0093")
|
| 74 |
|
|
buf.write(u"\u0179\7M\2\2\u0094\u0095\7\22\2\2\u0095\u0096\7M\2\2")
|
| 75 |
|
|
buf.write(u"\u0096\u0097\7\4\2\2\u0097\u0179\7M\2\2\u0098\u0099\7")
|
| 76 |
|
|
buf.write(u"\23\2\2\u0099\u009a\7M\2\2\u009a\u009b\7\4\2\2\u009b")
|
| 77 |
|
|
buf.write(u"\u0179\7M\2\2\u009c\u009d\7\24\2\2\u009d\u009e\7M\2\2")
|
| 78 |
|
|
buf.write(u"\u009e\u009f\7\4\2\2\u009f\u0179\7M\2\2\u00a0\u00a1\7")
|
| 79 |
|
|
buf.write(u"\25\2\2\u00a1\u00a2\7M\2\2\u00a2\u00a3\7\4\2\2\u00a3")
|
| 80 |
|
|
buf.write(u"\u0179\7M\2\2\u00a4\u00a5\7\26\2\2\u00a5\u00a6\7M\2\2")
|
| 81 |
|
|
buf.write(u"\u00a6\u00a7\7\4\2\2\u00a7\u0179\7M\2\2\u00a8\u00a9\7")
|
| 82 |
|
|
buf.write(u"\27\2\2\u00a9\u0179\7M\2\2\u00aa\u00ab\7\20\2\2\u00ab")
|
| 83 |
|
|
buf.write(u"\u00ac\7M\2\2\u00ac\u00ad\7\4\2\2\u00ad\u0179\7N\2\2")
|
| 84 |
|
|
buf.write(u"\u00ae\u00af\7\21\2\2\u00af\u00b0\7M\2\2\u00b0\u00b1")
|
| 85 |
|
|
buf.write(u"\7\4\2\2\u00b1\u0179\7N\2\2\u00b2\u00b3\7\22\2\2\u00b3")
|
| 86 |
|
|
buf.write(u"\u00b4\7M\2\2\u00b4\u00b5\7\4\2\2\u00b5\u0179\7N\2\2")
|
| 87 |
|
|
buf.write(u"\u00b6\u00b7\7\23\2\2\u00b7\u00b8\7M\2\2\u00b8\u00b9")
|
| 88 |
|
|
buf.write(u"\7\4\2\2\u00b9\u0179\7N\2\2\u00ba\u00bb\7\24\2\2\u00bb")
|
| 89 |
|
|
buf.write(u"\u00bc\7M\2\2\u00bc\u00bd\7\4\2\2\u00bd\u0179\7N\2\2")
|
| 90 |
|
|
buf.write(u"\u00be\u00bf\7\25\2\2\u00bf\u00c0\7M\2\2\u00c0\u00c1")
|
| 91 |
|
|
buf.write(u"\7\4\2\2\u00c1\u0179\7N\2\2\u00c2\u00c3\7\26\2\2\u00c3")
|
| 92 |
|
|
buf.write(u"\u00c4\7M\2\2\u00c4\u00c5\7\4\2\2\u00c5\u0179\7N\2\2")
|
| 93 |
|
|
buf.write(u"\u00c6\u00c7\7\22\2\2\u00c7\u00c8\7O\2\2\u00c8\u00c9")
|
| 94 |
|
|
buf.write(u"\7\4\2\2\u00c9\u0179\7N\2\2\u00ca\u00cb\7\20\2\2\u00cb")
|
| 95 |
|
|
buf.write(u"\u00cc\7O\2\2\u00cc\u00cd\7\4\2\2\u00cd\u0179\7N\2\2")
|
| 96 |
|
|
buf.write(u"\u00ce\u00cf\7\30\2\2\u00cf\u00d0\7M\2\2\u00d0\u00d1")
|
| 97 |
|
|
buf.write(u"\7\4\2\2\u00d1\u0179\7M\2\2\u00d2\u00d3\7\31\2\2\u00d3")
|
| 98 |
|
|
buf.write(u"\u00d4\7M\2\2\u00d4\u00d5\7\4\2\2\u00d5\u0179\7M\2\2")
|
| 99 |
|
|
buf.write(u"\u00d6\u00d7\7\30\2\2\u00d7\u00d8\7M\2\2\u00d8\u00d9")
|
| 100 |
|
|
buf.write(u"\7\4\2\2\u00d9\u0179\7N\2\2\u00da\u00db\7\31\2\2\u00db")
|
| 101 |
|
|
buf.write(u"\u00dc\7M\2\2\u00dc\u00dd\7\4\2\2\u00dd\u0179\7N\2\2")
|
| 102 |
|
|
buf.write(u"\u00de\u00df\7\32\2\2\u00df\u00e0\7M\2\2\u00e0\u00e1")
|
| 103 |
|
|
buf.write(u"\7\4\2\2\u00e1\u0179\7M\2\2\u00e2\u00e3\7\33\2\2\u00e3")
|
| 104 |
|
|
buf.write(u"\u00e4\7M\2\2\u00e4\u00e5\7\4\2\2\u00e5\u0179\7M\2\2")
|
| 105 |
|
|
buf.write(u"\u00e6\u00e7\7\34\2\2\u00e7\u00e8\7M\2\2\u00e8\u00e9")
|
| 106 |
|
|
buf.write(u"\7\4\2\2\u00e9\u0179\7M\2\2\u00ea\u00eb\7\35\2\2\u00eb")
|
| 107 |
|
|
buf.write(u"\u00ec\7M\2\2\u00ec\u00ed\7\4\2\2\u00ed\u0179\7M\2\2")
|
| 108 |
|
|
buf.write(u"\u00ee\u00ef\7\36\2\2\u00ef\u00f0\7M\2\2\u00f0\u00f1")
|
| 109 |
|
|
buf.write(u"\7\4\2\2\u00f1\u0179\7M\2\2\u00f2\u00f3\7\37\2\2\u00f3")
|
| 110 |
|
|
buf.write(u"\u00f4\7M\2\2\u00f4\u00f5\7\4\2\2\u00f5\u0179\7M\2\2")
|
| 111 |
|
|
buf.write(u"\u00f6\u00f7\7 \2\2\u00f7\u00f8\7M\2\2\u00f8\u00f9\7")
|
| 112 |
|
|
buf.write(u"\4\2\2\u00f9\u0179\7M\2\2\u00fa\u00fb\7!\2\2\u00fb\u00fc")
|
| 113 |
|
|
buf.write(u"\7M\2\2\u00fc\u00fd\7\4\2\2\u00fd\u0179\7M\2\2\u00fe")
|
| 114 |
|
|
buf.write(u"\u00ff\7\32\2\2\u00ff\u0100\7M\2\2\u0100\u0101\7\4\2")
|
| 115 |
|
|
buf.write(u"\2\u0101\u0179\7N\2\2\u0102\u0103\7\33\2\2\u0103\u0104")
|
| 116 |
|
|
buf.write(u"\7M\2\2\u0104\u0105\7\4\2\2\u0105\u0179\7N\2\2\u0106")
|
| 117 |
|
|
buf.write(u"\u0107\7\34\2\2\u0107\u0108\7M\2\2\u0108\u0109\7\4\2")
|
| 118 |
|
|
buf.write(u"\2\u0109\u0179\7N\2\2\u010a\u010b\7\35\2\2\u010b\u010c")
|
| 119 |
|
|
buf.write(u"\7M\2\2\u010c\u010d\7\4\2\2\u010d\u0179\7N\2\2\u010e")
|
| 120 |
|
|
buf.write(u"\u010f\7\36\2\2\u010f\u0110\7M\2\2\u0110\u0111\7\4\2")
|
| 121 |
|
|
buf.write(u"\2\u0111\u0179\7N\2\2\u0112\u0113\7\37\2\2\u0113\u0114")
|
| 122 |
|
|
buf.write(u"\7M\2\2\u0114\u0115\7\4\2\2\u0115\u0179\7N\2\2\u0116")
|
| 123 |
|
|
buf.write(u"\u0117\7 \2\2\u0117\u0118\7M\2\2\u0118\u0119\7\4\2\2")
|
| 124 |
|
|
buf.write(u"\u0119\u0179\7N\2\2\u011a\u011b\7!\2\2\u011b\u011c\7")
|
| 125 |
|
|
buf.write(u"M\2\2\u011c\u011d\7\4\2\2\u011d\u0179\7N\2\2\u011e\u011f")
|
| 126 |
|
|
buf.write(u"\7\"\2\2\u011f\u0179\7M\2\2\u0120\u0179\7#\2\2\u0121")
|
| 127 |
|
|
buf.write(u"\u0122\7$\2\2\u0122\u0179\7M\2\2\u0123\u0179\7%\2\2\u0124")
|
| 128 |
|
|
buf.write(u"\u0125\7&\2\2\u0125\u0126\7\6\2\2\u0126\u0127\7M\2\2")
|
| 129 |
|
|
buf.write(u"\u0127\u0179\7\7\2\2\u0128\u0129\7\'\2\2\u0129\u012a")
|
| 130 |
|
|
buf.write(u"\7\6\2\2\u012a\u012b\7M\2\2\u012b\u0179\7\7\2\2\u012c")
|
| 131 |
|
|
buf.write(u"\u012d\7\'\2\2\u012d\u012e\7\6\2\2\u012e\u012f\7N\2\2")
|
| 132 |
|
|
buf.write(u"\u012f\u0179\7\7\2\2\u0130\u0179\7(\2\2\u0131\u0179\7")
|
| 133 |
|
|
buf.write(u")\2\2\u0132\u0179\7*\2\2\u0133\u0179\7+\2\2\u0134\u0179")
|
| 134 |
|
|
buf.write(u"\7,\2\2\u0135\u0179\7-\2\2\u0136\u0179\7.\2\2\u0137\u0138")
|
| 135 |
|
|
buf.write(u"\7/\2\2\u0138\u0179\7N\2\2\u0139\u0179\7\60\2\2\u013a")
|
| 136 |
|
|
buf.write(u"\u013b\7\61\2\2\u013b\u013c\7\6\2\2\u013c\u013d\7M\2")
|
| 137 |
|
|
buf.write(u"\2\u013d\u0179\7\7\2\2\u013e\u013f\7\62\2\2\u013f\u0140")
|
| 138 |
|
|
buf.write(u"\7\6\2\2\u0140\u0141\7M\2\2\u0141\u0179\7\7\2\2\u0142")
|
| 139 |
|
|
buf.write(u"\u0143\7\62\2\2\u0143\u0144\7\6\2\2\u0144\u0145\7N\2")
|
| 140 |
|
|
buf.write(u"\2\u0145\u0179\7\7\2\2\u0146\u0179\7\63\2\2\u0147\u0179")
|
| 141 |
|
|
buf.write(u"\7\64\2\2\u0148\u0149\7\65\2\2\u0149\u0179\7N\2\2\u014a")
|
| 142 |
|
|
buf.write(u"\u014b\7\66\2\2\u014b\u0179\7N\2\2\u014c\u014d\7\67\2")
|
| 143 |
|
|
buf.write(u"\2\u014d\u0179\7N\2\2\u014e\u014f\78\2\2\u014f\u0179")
|
| 144 |
|
|
buf.write(u"\7N\2\2\u0150\u0151\79\2\2\u0151\u0179\7N\2\2\u0152\u0153")
|
| 145 |
|
|
buf.write(u"\7:\2\2\u0153\u0179\7N\2\2\u0154\u0155\7;\2\2\u0155\u0179")
|
| 146 |
|
|
buf.write(u"\7N\2\2\u0156\u0157\7<\2\2\u0157\u0179\7N\2\2\u0158\u0159")
|
| 147 |
|
|
buf.write(u"\7=\2\2\u0159\u0179\7N\2\2\u015a\u015b\7>\2\2\u015b\u0179")
|
| 148 |
|
|
buf.write(u"\7N\2\2\u015c\u015d\7?\2\2\u015d\u0179\7N\2\2\u015e\u015f")
|
| 149 |
|
|
buf.write(u"\7@\2\2\u015f\u0179\7N\2\2\u0160\u0161\7A\2\2\u0161\u0179")
|
| 150 |
|
|
buf.write(u"\7N\2\2\u0162\u0163\7B\2\2\u0163\u0179\7N\2\2\u0164\u0165")
|
| 151 |
|
|
buf.write(u"\7C\2\2\u0165\u0179\7N\2\2\u0166\u0167\7D\2\2\u0167\u0179")
|
| 152 |
|
|
buf.write(u"\7N\2\2\u0168\u0169\7E\2\2\u0169\u0179\7N\2\2\u016a\u016b")
|
| 153 |
|
|
buf.write(u"\7F\2\2\u016b\u0179\7N\2\2\u016c\u016d\7G\2\2\u016d\u0179")
|
| 154 |
|
|
buf.write(u"\7N\2\2\u016e\u016f\7H\2\2\u016f\u0179\7N\2\2\u0170\u0171")
|
| 155 |
|
|
buf.write(u"\7I\2\2\u0171\u0179\7N\2\2\u0172\u0173\7J\2\2\u0173\u0179")
|
| 156 |
|
|
buf.write(u"\7N\2\2\u0174\u0175\7K\2\2\u0175\u0179\7N\2\2\u0176\u0177")
|
| 157 |
|
|
buf.write(u"\7L\2\2\u0177\u0179\7N\2\2\u0178\22\3\2\2\2\u0178\26")
|
| 158 |
|
|
buf.write(u"\3\2\2\2\u0178\32\3\2\2\2\u0178\36\3\2\2\2\u0178$\3\2")
|
| 159 |
|
|
buf.write(u"\2\2\u0178,\3\2\2\2\u0178\62\3\2\2\2\u0178:\3\2\2\2\u0178")
|
| 160 |
|
|
buf.write(u"@\3\2\2\2\u0178H\3\2\2\2\u0178N\3\2\2\2\u0178V\3\2\2")
|
| 161 |
|
|
buf.write(u"\2\u0178\\\3\2\2\2\u0178d\3\2\2\2\u0178j\3\2\2\2\u0178")
|
| 162 |
|
|
buf.write(u"r\3\2\2\2\u0178x\3\2\2\2\u0178\u0080\3\2\2\2\u0178\u0084")
|
| 163 |
|
|
buf.write(u"\3\2\2\2\u0178\u0088\3\2\2\2\u0178\u008a\3\2\2\2\u0178")
|
| 164 |
|
|
buf.write(u"\u008c\3\2\2\2\u0178\u0090\3\2\2\2\u0178\u0094\3\2\2")
|
| 165 |
|
|
buf.write(u"\2\u0178\u0098\3\2\2\2\u0178\u009c\3\2\2\2\u0178\u00a0")
|
| 166 |
|
|
buf.write(u"\3\2\2\2\u0178\u00a4\3\2\2\2\u0178\u00a8\3\2\2\2\u0178")
|
| 167 |
|
|
buf.write(u"\u00aa\3\2\2\2\u0178\u00ae\3\2\2\2\u0178\u00b2\3\2\2")
|
| 168 |
|
|
buf.write(u"\2\u0178\u00b6\3\2\2\2\u0178\u00ba\3\2\2\2\u0178\u00be")
|
| 169 |
|
|
buf.write(u"\3\2\2\2\u0178\u00c2\3\2\2\2\u0178\u00c6\3\2\2\2\u0178")
|
| 170 |
|
|
buf.write(u"\u00ca\3\2\2\2\u0178\u00ce\3\2\2\2\u0178\u00d2\3\2\2")
|
| 171 |
|
|
buf.write(u"\2\u0178\u00d6\3\2\2\2\u0178\u00da\3\2\2\2\u0178\u00de")
|
| 172 |
|
|
buf.write(u"\3\2\2\2\u0178\u00e2\3\2\2\2\u0178\u00e6\3\2\2\2\u0178")
|
| 173 |
|
|
buf.write(u"\u00ea\3\2\2\2\u0178\u00ee\3\2\2\2\u0178\u00f2\3\2\2")
|
| 174 |
|
|
buf.write(u"\2\u0178\u00f6\3\2\2\2\u0178\u00fa\3\2\2\2\u0178\u00fe")
|
| 175 |
|
|
buf.write(u"\3\2\2\2\u0178\u0102\3\2\2\2\u0178\u0106\3\2\2\2\u0178")
|
| 176 |
|
|
buf.write(u"\u010a\3\2\2\2\u0178\u010e\3\2\2\2\u0178\u0112\3\2\2")
|
| 177 |
|
|
buf.write(u"\2\u0178\u0116\3\2\2\2\u0178\u011a\3\2\2\2\u0178\u011e")
|
| 178 |
|
|
buf.write(u"\3\2\2\2\u0178\u0120\3\2\2\2\u0178\u0121\3\2\2\2\u0178")
|
| 179 |
|
|
buf.write(u"\u0123\3\2\2\2\u0178\u0124\3\2\2\2\u0178\u0128\3\2\2")
|
| 180 |
|
|
buf.write(u"\2\u0178\u012c\3\2\2\2\u0178\u0130\3\2\2\2\u0178\u0131")
|
| 181 |
|
|
buf.write(u"\3\2\2\2\u0178\u0132\3\2\2\2\u0178\u0133\3\2\2\2\u0178")
|
| 182 |
|
|
buf.write(u"\u0134\3\2\2\2\u0178\u0135\3\2\2\2\u0178\u0136\3\2\2")
|
| 183 |
|
|
buf.write(u"\2\u0178\u0137\3\2\2\2\u0178\u0139\3\2\2\2\u0178\u013a")
|
| 184 |
|
|
buf.write(u"\3\2\2\2\u0178\u013e\3\2\2\2\u0178\u0142\3\2\2\2\u0178")
|
| 185 |
|
|
buf.write(u"\u0146\3\2\2\2\u0178\u0147\3\2\2\2\u0178\u0148\3\2\2")
|
| 186 |
|
|
buf.write(u"\2\u0178\u014a\3\2\2\2\u0178\u014c\3\2\2\2\u0178\u014e")
|
| 187 |
|
|
buf.write(u"\3\2\2\2\u0178\u0150\3\2\2\2\u0178\u0152\3\2\2\2\u0178")
|
| 188 |
|
|
buf.write(u"\u0154\3\2\2\2\u0178\u0156\3\2\2\2\u0178\u0158\3\2\2")
|
| 189 |
|
|
buf.write(u"\2\u0178\u015a\3\2\2\2\u0178\u015c\3\2\2\2\u0178\u015e")
|
| 190 |
|
|
buf.write(u"\3\2\2\2\u0178\u0160\3\2\2\2\u0178\u0162\3\2\2\2\u0178")
|
| 191 |
|
|
buf.write(u"\u0164\3\2\2\2\u0178\u0166\3\2\2\2\u0178\u0168\3\2\2")
|
| 192 |
|
|
buf.write(u"\2\u0178\u016a\3\2\2\2\u0178\u016c\3\2\2\2\u0178\u016e")
|
| 193 |
|
|
buf.write(u"\3\2\2\2\u0178\u0170\3\2\2\2\u0178\u0172\3\2\2\2\u0178")
|
| 194 |
|
|
buf.write(u"\u0174\3\2\2\2\u0178\u0176\3\2\2\2\u0179\7\3\2\2\2\5")
|
| 195 |
|
|
buf.write(u"\13\16\u0178")
|
| 196 |
|
|
return buf.getvalue()
|
| 197 |
|
|
|
| 198 |
|
|
|
| 199 |
|
|
class HPC16Parser ( Parser ):
|
| 200 |
|
|
|
| 201 |
|
|
grammarFileName = "HPC16.g4"
|
| 202 |
|
|
|
| 203 |
|
|
atn = ATNDeserializer().deserialize(serializedATN())
|
| 204 |
|
|
|
| 205 |
|
|
decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ]
|
| 206 |
|
|
|
| 207 |
|
|
sharedContextCache = PredictionContextCache()
|
| 208 |
|
|
|
| 209 |
|
|
literalNames = [ u"<INVALID>", u"'mov'", u"','", u"'ld'", u"'('", u"')'",
|
| 210 |
|
|
u"'+'", u"'st'", u"'lbzx'", u"'lbsx'", u"'sb'", u"'li'",
|
| 211 |
|
|
u"'inc'", u"'dec'", u"'sub'", u"'and'", u"'add'", u"'adc'",
|
| 212 |
|
|
u"'sbb'", u"'or'", u"'xor'", u"'not'", u"'cmp'", u"'test'",
|
| 213 |
|
|
u"'sll'", u"'slr'", u"'sal'", u"'sar'", u"'rol'", u"'ror'",
|
| 214 |
|
|
u"'rcl'", u"'rcr'", u"'push'", u"'pushf'", u"'pop'",
|
| 215 |
|
|
u"'popf'", u"'acall'", u"'call'", u"'ret'", u"'iret'",
|
| 216 |
|
|
u"'clc'", u"'stc'", u"'cmc'", u"'cli'", u"'sti'", u"'int'",
|
| 217 |
|
|
u"'into'", u"'ajmp'", u"'jmp'", u"'nop'", u"'hlt'",
|
| 218 |
|
|
u"'jo'", u"'jno'", u"'jb'", u"'jnae'", u"'jnb'", u"'jae'",
|
| 219 |
|
|
u"'je'", u"'jz'", u"'jne'", u"'jnz'", u"'jbe'", u"'jna'",
|
| 220 |
|
|
u"'jnbe'", u"'ja'", u"'js'", u"'jns'", u"'jl'", u"'jnge'",
|
| 221 |
|
|
u"'jnl'", u"'jge'", u"'jle'", u"'jng'", u"'jnle'",
|
| 222 |
|
|
u"'jg'" ]
|
| 223 |
|
|
|
| 224 |
|
|
symbolicNames = [ u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 225 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 226 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 227 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 228 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 229 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 230 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 231 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 232 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 233 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 234 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 235 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 236 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 237 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 238 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 239 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 240 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 241 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>",
|
| 242 |
|
|
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"REG",
|
| 243 |
|
|
u"IMM", u"STK_PTR", u"WS", u"LINE_COMMENT", u"NEWLINE" ]
|
| 244 |
|
|
|
| 245 |
|
|
RULE_prog = 0
|
| 246 |
|
|
RULE_stat = 1
|
| 247 |
|
|
RULE_asm_inst = 2
|
| 248 |
|
|
|
| 249 |
|
|
ruleNames = [ u"prog", u"stat", u"asm_inst" ]
|
| 250 |
|
|
|
| 251 |
|
|
EOF = Token.EOF
|
| 252 |
|
|
T__0=1
|
| 253 |
|
|
T__1=2
|
| 254 |
|
|
T__2=3
|
| 255 |
|
|
T__3=4
|
| 256 |
|
|
T__4=5
|
| 257 |
|
|
T__5=6
|
| 258 |
|
|
T__6=7
|
| 259 |
|
|
T__7=8
|
| 260 |
|
|
T__8=9
|
| 261 |
|
|
T__9=10
|
| 262 |
|
|
T__10=11
|
| 263 |
|
|
T__11=12
|
| 264 |
|
|
T__12=13
|
| 265 |
|
|
T__13=14
|
| 266 |
|
|
T__14=15
|
| 267 |
|
|
T__15=16
|
| 268 |
|
|
T__16=17
|
| 269 |
|
|
T__17=18
|
| 270 |
|
|
T__18=19
|
| 271 |
|
|
T__19=20
|
| 272 |
|
|
T__20=21
|
| 273 |
|
|
T__21=22
|
| 274 |
|
|
T__22=23
|
| 275 |
|
|
T__23=24
|
| 276 |
|
|
T__24=25
|
| 277 |
|
|
T__25=26
|
| 278 |
|
|
T__26=27
|
| 279 |
|
|
T__27=28
|
| 280 |
|
|
T__28=29
|
| 281 |
|
|
T__29=30
|
| 282 |
|
|
T__30=31
|
| 283 |
|
|
T__31=32
|
| 284 |
|
|
T__32=33
|
| 285 |
|
|
T__33=34
|
| 286 |
|
|
T__34=35
|
| 287 |
|
|
T__35=36
|
| 288 |
|
|
T__36=37
|
| 289 |
|
|
T__37=38
|
| 290 |
|
|
T__38=39
|
| 291 |
|
|
T__39=40
|
| 292 |
|
|
T__40=41
|
| 293 |
|
|
T__41=42
|
| 294 |
|
|
T__42=43
|
| 295 |
|
|
T__43=44
|
| 296 |
|
|
T__44=45
|
| 297 |
|
|
T__45=46
|
| 298 |
|
|
T__46=47
|
| 299 |
|
|
T__47=48
|
| 300 |
|
|
T__48=49
|
| 301 |
|
|
T__49=50
|
| 302 |
|
|
T__50=51
|
| 303 |
|
|
T__51=52
|
| 304 |
|
|
T__52=53
|
| 305 |
|
|
T__53=54
|
| 306 |
|
|
T__54=55
|
| 307 |
|
|
T__55=56
|
| 308 |
|
|
T__56=57
|
| 309 |
|
|
T__57=58
|
| 310 |
|
|
T__58=59
|
| 311 |
|
|
T__59=60
|
| 312 |
|
|
T__60=61
|
| 313 |
|
|
T__61=62
|
| 314 |
|
|
T__62=63
|
| 315 |
|
|
T__63=64
|
| 316 |
|
|
T__64=65
|
| 317 |
|
|
T__65=66
|
| 318 |
|
|
T__66=67
|
| 319 |
|
|
T__67=68
|
| 320 |
|
|
T__68=69
|
| 321 |
|
|
T__69=70
|
| 322 |
|
|
T__70=71
|
| 323 |
|
|
T__71=72
|
| 324 |
|
|
T__72=73
|
| 325 |
|
|
T__73=74
|
| 326 |
|
|
REG=75
|
| 327 |
|
|
IMM=76
|
| 328 |
|
|
STK_PTR=77
|
| 329 |
|
|
WS=78
|
| 330 |
|
|
LINE_COMMENT=79
|
| 331 |
|
|
NEWLINE=80
|
| 332 |
|
|
|
| 333 |
|
|
def __init__(self, input):
|
| 334 |
|
|
super(HPC16Parser, self).__init__(input)
|
| 335 |
|
|
self.checkVersion("4.5.1")
|
| 336 |
|
|
self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache)
|
| 337 |
|
|
self._predicates = None
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
|
|
|
| 341 |
|
|
class ProgContext(ParserRuleContext):
|
| 342 |
|
|
|
| 343 |
|
|
def __init__(self, parser, parent=None, invokingState=-1):
|
| 344 |
|
|
super(HPC16Parser.ProgContext, self).__init__(parent, invokingState)
|
| 345 |
|
|
self.parser = parser
|
| 346 |
|
|
|
| 347 |
|
|
def stat(self, i=None):
|
| 348 |
|
|
if i is None:
|
| 349 |
|
|
return self.getTypedRuleContexts(HPC16Parser.StatContext)
|
| 350 |
|
|
else:
|
| 351 |
|
|
return self.getTypedRuleContext(HPC16Parser.StatContext,i)
|
| 352 |
|
|
|
| 353 |
|
|
|
| 354 |
|
|
def getRuleIndex(self):
|
| 355 |
|
|
return HPC16Parser.RULE_prog
|
| 356 |
|
|
|
| 357 |
|
|
def enterRule(self, listener):
|
| 358 |
|
|
if hasattr(listener, "enterProg"):
|
| 359 |
|
|
listener.enterProg(self)
|
| 360 |
|
|
|
| 361 |
|
|
def exitRule(self, listener):
|
| 362 |
|
|
if hasattr(listener, "exitProg"):
|
| 363 |
|
|
listener.exitProg(self)
|
| 364 |
|
|
|
| 365 |
|
|
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
def prog(self):
|
| 369 |
|
|
|
| 370 |
|
|
localctx = HPC16Parser.ProgContext(self, self._ctx, self.state)
|
| 371 |
|
|
self.enterRule(localctx, 0, self.RULE_prog)
|
| 372 |
|
|
self._la = 0 # Token type
|
| 373 |
|
|
try:
|
| 374 |
|
|
self.enterOuterAlt(localctx, 1)
|
| 375 |
|
|
self.state = 7
|
| 376 |
|
|
self._errHandler.sync(self)
|
| 377 |
|
|
_la = self._input.LA(1)
|
| 378 |
|
|
while True:
|
| 379 |
|
|
self.state = 6
|
| 380 |
|
|
self.stat()
|
| 381 |
|
|
self.state = 9
|
| 382 |
|
|
self._errHandler.sync(self)
|
| 383 |
|
|
_la = self._input.LA(1)
|
| 384 |
|
|
if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HPC16Parser.T__0) | (1 << HPC16Parser.T__2) | (1 << HPC16Parser.T__6) | (1 << HPC16Parser.T__7) | (1 << HPC16Parser.T__8) | (1 << HPC16Parser.T__9) | (1 << HPC16Parser.T__10) | (1 << HPC16Parser.T__11) | (1 << HPC16Parser.T__12) | (1 << HPC16Parser.T__13) | (1 << HPC16Parser.T__14) | (1 << HPC16Parser.T__15) | (1 << HPC16Parser.T__16) | (1 << HPC16Parser.T__17) | (1 << HPC16Parser.T__18) | (1 << HPC16Parser.T__19) | (1 << HPC16Parser.T__20) | (1 << HPC16Parser.T__21) | (1 << HPC16Parser.T__22) | (1 << HPC16Parser.T__23) | (1 << HPC16Parser.T__24) | (1 << HPC16Parser.T__25) | (1 << HPC16Parser.T__26) | (1 << HPC16Parser.T__27) | (1 << HPC16Parser.T__28) | (1 << HPC16Parser.T__29) | (1 << HPC16Parser.T__30) | (1 << HPC16Parser.T__31) | (1 << HPC16Parser.T__32) | (1 << HPC16Parser.T__33) | (1 << HPC16Parser.T__34) | (1 << HPC16Parser.T__35) | (1 << HPC16Parser.T__36) | (1 << HPC16Parser.T__37) | (1 << HPC16Parser.T__38) | (1 << HPC16Parser.T__39) | (1 << HPC16Parser.T__40) | (1 << HPC16Parser.T__41) | (1 << HPC16Parser.T__42) | (1 << HPC16Parser.T__43) | (1 << HPC16Parser.T__44) | (1 << HPC16Parser.T__45) | (1 << HPC16Parser.T__46) | (1 << HPC16Parser.T__47) | (1 << HPC16Parser.T__48) | (1 << HPC16Parser.T__49) | (1 << HPC16Parser.T__50) | (1 << HPC16Parser.T__51) | (1 << HPC16Parser.T__52) | (1 << HPC16Parser.T__53) | (1 << HPC16Parser.T__54) | (1 << HPC16Parser.T__55) | (1 << HPC16Parser.T__56) | (1 << HPC16Parser.T__57) | (1 << HPC16Parser.T__58) | (1 << HPC16Parser.T__59) | (1 << HPC16Parser.T__60) | (1 << HPC16Parser.T__61) | (1 << HPC16Parser.T__62))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (HPC16Parser.T__63 - 64)) | (1 << (HPC16Parser.T__64 - 64)) | (1 << (HPC16Parser.T__65 - 64)) | (1 << (HPC16Parser.T__66 - 64)) | (1 << (HPC16Parser.T__67 - 64)) | (1 << (HPC16Parser.T__68 - 64)) | (1 << (HPC16Parser.T__69 - 64)) | (1 << (HPC16Parser.T__70 - 64)) | (1 << (HPC16Parser.T__71 - 64)) | (1 << (HPC16Parser.T__72 - 64)) | (1 << (HPC16Parser.T__73 - 64)) | (1 << (HPC16Parser.NEWLINE - 64)))) != 0)):
|
| 385 |
|
|
break
|
| 386 |
|
|
|
| 387 |
|
|
except RecognitionException as re:
|
| 388 |
|
|
localctx.exception = re
|
| 389 |
|
|
self._errHandler.reportError(self, re)
|
| 390 |
|
|
self._errHandler.recover(self, re)
|
| 391 |
|
|
finally:
|
| 392 |
|
|
self.exitRule()
|
| 393 |
|
|
return localctx
|
| 394 |
|
|
|
| 395 |
|
|
class StatContext(ParserRuleContext):
|
| 396 |
|
|
|
| 397 |
|
|
def __init__(self, parser, parent=None, invokingState=-1):
|
| 398 |
|
|
super(HPC16Parser.StatContext, self).__init__(parent, invokingState)
|
| 399 |
|
|
self.parser = parser
|
| 400 |
|
|
|
| 401 |
|
|
def NEWLINE(self):
|
| 402 |
|
|
return self.getToken(HPC16Parser.NEWLINE, 0)
|
| 403 |
|
|
|
| 404 |
|
|
def asm_inst(self):
|
| 405 |
|
|
return self.getTypedRuleContext(HPC16Parser.Asm_instContext,0)
|
| 406 |
|
|
|
| 407 |
|
|
|
| 408 |
|
|
def getRuleIndex(self):
|
| 409 |
|
|
return HPC16Parser.RULE_stat
|
| 410 |
|
|
|
| 411 |
|
|
def enterRule(self, listener):
|
| 412 |
|
|
if hasattr(listener, "enterStat"):
|
| 413 |
|
|
listener.enterStat(self)
|
| 414 |
|
|
|
| 415 |
|
|
def exitRule(self, listener):
|
| 416 |
|
|
if hasattr(listener, "exitStat"):
|
| 417 |
|
|
listener.exitStat(self)
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
def stat(self):
|
| 423 |
|
|
|
| 424 |
|
|
localctx = HPC16Parser.StatContext(self, self._ctx, self.state)
|
| 425 |
|
|
self.enterRule(localctx, 2, self.RULE_stat)
|
| 426 |
|
|
self._la = 0 # Token type
|
| 427 |
|
|
try:
|
| 428 |
|
|
self.enterOuterAlt(localctx, 1)
|
| 429 |
|
|
self.state = 12
|
| 430 |
|
|
_la = self._input.LA(1)
|
| 431 |
|
|
if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HPC16Parser.T__0) | (1 << HPC16Parser.T__2) | (1 << HPC16Parser.T__6) | (1 << HPC16Parser.T__7) | (1 << HPC16Parser.T__8) | (1 << HPC16Parser.T__9) | (1 << HPC16Parser.T__10) | (1 << HPC16Parser.T__11) | (1 << HPC16Parser.T__12) | (1 << HPC16Parser.T__13) | (1 << HPC16Parser.T__14) | (1 << HPC16Parser.T__15) | (1 << HPC16Parser.T__16) | (1 << HPC16Parser.T__17) | (1 << HPC16Parser.T__18) | (1 << HPC16Parser.T__19) | (1 << HPC16Parser.T__20) | (1 << HPC16Parser.T__21) | (1 << HPC16Parser.T__22) | (1 << HPC16Parser.T__23) | (1 << HPC16Parser.T__24) | (1 << HPC16Parser.T__25) | (1 << HPC16Parser.T__26) | (1 << HPC16Parser.T__27) | (1 << HPC16Parser.T__28) | (1 << HPC16Parser.T__29) | (1 << HPC16Parser.T__30) | (1 << HPC16Parser.T__31) | (1 << HPC16Parser.T__32) | (1 << HPC16Parser.T__33) | (1 << HPC16Parser.T__34) | (1 << HPC16Parser.T__35) | (1 << HPC16Parser.T__36) | (1 << HPC16Parser.T__37) | (1 << HPC16Parser.T__38) | (1 << HPC16Parser.T__39) | (1 << HPC16Parser.T__40) | (1 << HPC16Parser.T__41) | (1 << HPC16Parser.T__42) | (1 << HPC16Parser.T__43) | (1 << HPC16Parser.T__44) | (1 << HPC16Parser.T__45) | (1 << HPC16Parser.T__46) | (1 << HPC16Parser.T__47) | (1 << HPC16Parser.T__48) | (1 << HPC16Parser.T__49) | (1 << HPC16Parser.T__50) | (1 << HPC16Parser.T__51) | (1 << HPC16Parser.T__52) | (1 << HPC16Parser.T__53) | (1 << HPC16Parser.T__54) | (1 << HPC16Parser.T__55) | (1 << HPC16Parser.T__56) | (1 << HPC16Parser.T__57) | (1 << HPC16Parser.T__58) | (1 << HPC16Parser.T__59) | (1 << HPC16Parser.T__60) | (1 << HPC16Parser.T__61) | (1 << HPC16Parser.T__62))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (HPC16Parser.T__63 - 64)) | (1 << (HPC16Parser.T__64 - 64)) | (1 << (HPC16Parser.T__65 - 64)) | (1 << (HPC16Parser.T__66 - 64)) | (1 << (HPC16Parser.T__67 - 64)) | (1 << (HPC16Parser.T__68 - 64)) | (1 << (HPC16Parser.T__69 - 64)) | (1 << (HPC16Parser.T__70 - 64)) | (1 << (HPC16Parser.T__71 - 64)) | (1 << (HPC16Parser.T__72 - 64)) | (1 << (HPC16Parser.T__73 - 64)))) != 0):
|
| 432 |
|
|
self.state = 11
|
| 433 |
|
|
self.asm_inst()
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
self.state = 14
|
| 437 |
|
|
self.match(HPC16Parser.NEWLINE)
|
| 438 |
|
|
except RecognitionException as re:
|
| 439 |
|
|
localctx.exception = re
|
| 440 |
|
|
self._errHandler.reportError(self, re)
|
| 441 |
|
|
self._errHandler.recover(self, re)
|
| 442 |
|
|
finally:
|
| 443 |
|
|
self.exitRule()
|
| 444 |
|
|
return localctx
|
| 445 |
|
|
|
| 446 |
|
|
class Asm_instContext(ParserRuleContext):
|
| 447 |
|
|
|
| 448 |
|
|
def __init__(self, parser, parent=None, invokingState=-1):
|
| 449 |
|
|
super(HPC16Parser.Asm_instContext, self).__init__(parent, invokingState)
|
| 450 |
|
|
self.parser = parser
|
| 451 |
|
|
|
| 452 |
|
|
|
| 453 |
|
|
def getRuleIndex(self):
|
| 454 |
|
|
return HPC16Parser.RULE_asm_inst
|
| 455 |
|
|
|
| 456 |
|
|
|
| 457 |
|
|
def copyFrom(self, ctx):
|
| 458 |
|
|
super(HPC16Parser.Asm_instContext, self).copyFrom(ctx)
|
| 459 |
|
|
|
| 460 |
|
|
|
| 461 |
|
|
|
| 462 |
|
|
class Mov_reg_spContext(Asm_instContext):
|
| 463 |
|
|
|
| 464 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 465 |
|
|
super(HPC16Parser.Mov_reg_spContext, self).__init__(parser)
|
| 466 |
|
|
self.copyFrom(ctx)
|
| 467 |
|
|
|
| 468 |
|
|
def REG(self):
|
| 469 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 470 |
|
|
def STK_PTR(self):
|
| 471 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 472 |
|
|
|
| 473 |
|
|
def enterRule(self, listener):
|
| 474 |
|
|
if hasattr(listener, "enterMov_reg_sp"):
|
| 475 |
|
|
listener.enterMov_reg_sp(self)
|
| 476 |
|
|
|
| 477 |
|
|
def exitRule(self, listener):
|
| 478 |
|
|
if hasattr(listener, "exitMov_reg_sp"):
|
| 479 |
|
|
listener.exitMov_reg_sp(self)
|
| 480 |
|
|
|
| 481 |
|
|
|
| 482 |
|
|
class Sb_reg_regContext(Asm_instContext):
|
| 483 |
|
|
|
| 484 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 485 |
|
|
super(HPC16Parser.Sb_reg_regContext, self).__init__(parser)
|
| 486 |
|
|
self.copyFrom(ctx)
|
| 487 |
|
|
|
| 488 |
|
|
def REG(self, i=None):
|
| 489 |
|
|
if i is None:
|
| 490 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 491 |
|
|
else:
|
| 492 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 493 |
|
|
|
| 494 |
|
|
def enterRule(self, listener):
|
| 495 |
|
|
if hasattr(listener, "enterSb_reg_reg"):
|
| 496 |
|
|
listener.enterSb_reg_reg(self)
|
| 497 |
|
|
|
| 498 |
|
|
def exitRule(self, listener):
|
| 499 |
|
|
if hasattr(listener, "exitSb_reg_reg"):
|
| 500 |
|
|
listener.exitSb_reg_reg(self)
|
| 501 |
|
|
|
| 502 |
|
|
|
| 503 |
|
|
class PopfContext(Asm_instContext):
|
| 504 |
|
|
|
| 505 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 506 |
|
|
super(HPC16Parser.PopfContext, self).__init__(parser)
|
| 507 |
|
|
self.copyFrom(ctx)
|
| 508 |
|
|
|
| 509 |
|
|
|
| 510 |
|
|
def enterRule(self, listener):
|
| 511 |
|
|
if hasattr(listener, "enterPopf"):
|
| 512 |
|
|
listener.enterPopf(self)
|
| 513 |
|
|
|
| 514 |
|
|
def exitRule(self, listener):
|
| 515 |
|
|
if hasattr(listener, "exitPopf"):
|
| 516 |
|
|
listener.exitPopf(self)
|
| 517 |
|
|
|
| 518 |
|
|
|
| 519 |
|
|
class Ld_reg_spContext(Asm_instContext):
|
| 520 |
|
|
|
| 521 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 522 |
|
|
super(HPC16Parser.Ld_reg_spContext, self).__init__(parser)
|
| 523 |
|
|
self.copyFrom(ctx)
|
| 524 |
|
|
|
| 525 |
|
|
def REG(self):
|
| 526 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 527 |
|
|
def STK_PTR(self):
|
| 528 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 529 |
|
|
|
| 530 |
|
|
def enterRule(self, listener):
|
| 531 |
|
|
if hasattr(listener, "enterLd_reg_sp"):
|
| 532 |
|
|
listener.enterLd_reg_sp(self)
|
| 533 |
|
|
|
| 534 |
|
|
def exitRule(self, listener):
|
| 535 |
|
|
if hasattr(listener, "exitLd_reg_sp"):
|
| 536 |
|
|
listener.exitLd_reg_sp(self)
|
| 537 |
|
|
|
| 538 |
|
|
|
| 539 |
|
|
class Call_imm11Context(Asm_instContext):
|
| 540 |
|
|
|
| 541 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 542 |
|
|
super(HPC16Parser.Call_imm11Context, self).__init__(parser)
|
| 543 |
|
|
self.copyFrom(ctx)
|
| 544 |
|
|
|
| 545 |
|
|
def IMM(self):
|
| 546 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 547 |
|
|
|
| 548 |
|
|
def enterRule(self, listener):
|
| 549 |
|
|
if hasattr(listener, "enterCall_imm11"):
|
| 550 |
|
|
listener.enterCall_imm11(self)
|
| 551 |
|
|
|
| 552 |
|
|
def exitRule(self, listener):
|
| 553 |
|
|
if hasattr(listener, "exitCall_imm11"):
|
| 554 |
|
|
listener.exitCall_imm11(self)
|
| 555 |
|
|
|
| 556 |
|
|
|
| 557 |
|
|
class Jge_imm7Context(Asm_instContext):
|
| 558 |
|
|
|
| 559 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 560 |
|
|
super(HPC16Parser.Jge_imm7Context, self).__init__(parser)
|
| 561 |
|
|
self.copyFrom(ctx)
|
| 562 |
|
|
|
| 563 |
|
|
def IMM(self):
|
| 564 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 565 |
|
|
|
| 566 |
|
|
def enterRule(self, listener):
|
| 567 |
|
|
if hasattr(listener, "enterJge_imm7"):
|
| 568 |
|
|
listener.enterJge_imm7(self)
|
| 569 |
|
|
|
| 570 |
|
|
def exitRule(self, listener):
|
| 571 |
|
|
if hasattr(listener, "exitJge_imm7"):
|
| 572 |
|
|
listener.exitJge_imm7(self)
|
| 573 |
|
|
|
| 574 |
|
|
|
| 575 |
|
|
class St_reg_reg_imm16Context(Asm_instContext):
|
| 576 |
|
|
|
| 577 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 578 |
|
|
super(HPC16Parser.St_reg_reg_imm16Context, self).__init__(parser)
|
| 579 |
|
|
self.copyFrom(ctx)
|
| 580 |
|
|
|
| 581 |
|
|
def REG(self, i=None):
|
| 582 |
|
|
if i is None:
|
| 583 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 584 |
|
|
else:
|
| 585 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 586 |
|
|
def IMM(self):
|
| 587 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 588 |
|
|
|
| 589 |
|
|
def enterRule(self, listener):
|
| 590 |
|
|
if hasattr(listener, "enterSt_reg_reg_imm16"):
|
| 591 |
|
|
listener.enterSt_reg_reg_imm16(self)
|
| 592 |
|
|
|
| 593 |
|
|
def exitRule(self, listener):
|
| 594 |
|
|
if hasattr(listener, "exitSt_reg_reg_imm16"):
|
| 595 |
|
|
listener.exitSt_reg_reg_imm16(self)
|
| 596 |
|
|
|
| 597 |
|
|
|
| 598 |
|
|
class Li_reg_imm16Context(Asm_instContext):
|
| 599 |
|
|
|
| 600 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 601 |
|
|
super(HPC16Parser.Li_reg_imm16Context, self).__init__(parser)
|
| 602 |
|
|
self.copyFrom(ctx)
|
| 603 |
|
|
|
| 604 |
|
|
def REG(self):
|
| 605 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 606 |
|
|
def IMM(self):
|
| 607 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 608 |
|
|
|
| 609 |
|
|
def enterRule(self, listener):
|
| 610 |
|
|
if hasattr(listener, "enterLi_reg_imm16"):
|
| 611 |
|
|
listener.enterLi_reg_imm16(self)
|
| 612 |
|
|
|
| 613 |
|
|
def exitRule(self, listener):
|
| 614 |
|
|
if hasattr(listener, "exitLi_reg_imm16"):
|
| 615 |
|
|
listener.exitLi_reg_imm16(self)
|
| 616 |
|
|
|
| 617 |
|
|
|
| 618 |
|
|
class Je_imm7Context(Asm_instContext):
|
| 619 |
|
|
|
| 620 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 621 |
|
|
super(HPC16Parser.Je_imm7Context, self).__init__(parser)
|
| 622 |
|
|
self.copyFrom(ctx)
|
| 623 |
|
|
|
| 624 |
|
|
def IMM(self):
|
| 625 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 626 |
|
|
|
| 627 |
|
|
def enterRule(self, listener):
|
| 628 |
|
|
if hasattr(listener, "enterJe_imm7"):
|
| 629 |
|
|
listener.enterJe_imm7(self)
|
| 630 |
|
|
|
| 631 |
|
|
def exitRule(self, listener):
|
| 632 |
|
|
if hasattr(listener, "exitJe_imm7"):
|
| 633 |
|
|
listener.exitJe_imm7(self)
|
| 634 |
|
|
|
| 635 |
|
|
|
| 636 |
|
|
class Push_regContext(Asm_instContext):
|
| 637 |
|
|
|
| 638 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 639 |
|
|
super(HPC16Parser.Push_regContext, self).__init__(parser)
|
| 640 |
|
|
self.copyFrom(ctx)
|
| 641 |
|
|
|
| 642 |
|
|
def REG(self):
|
| 643 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 644 |
|
|
|
| 645 |
|
|
def enterRule(self, listener):
|
| 646 |
|
|
if hasattr(listener, "enterPush_reg"):
|
| 647 |
|
|
listener.enterPush_reg(self)
|
| 648 |
|
|
|
| 649 |
|
|
def exitRule(self, listener):
|
| 650 |
|
|
if hasattr(listener, "exitPush_reg"):
|
| 651 |
|
|
listener.exitPush_reg(self)
|
| 652 |
|
|
|
| 653 |
|
|
|
| 654 |
|
|
class Sll_reg_imm4Context(Asm_instContext):
|
| 655 |
|
|
|
| 656 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 657 |
|
|
super(HPC16Parser.Sll_reg_imm4Context, self).__init__(parser)
|
| 658 |
|
|
self.copyFrom(ctx)
|
| 659 |
|
|
|
| 660 |
|
|
def REG(self):
|
| 661 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 662 |
|
|
def IMM(self):
|
| 663 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 664 |
|
|
|
| 665 |
|
|
def enterRule(self, listener):
|
| 666 |
|
|
if hasattr(listener, "enterSll_reg_imm4"):
|
| 667 |
|
|
listener.enterSll_reg_imm4(self)
|
| 668 |
|
|
|
| 669 |
|
|
def exitRule(self, listener):
|
| 670 |
|
|
if hasattr(listener, "exitSll_reg_imm4"):
|
| 671 |
|
|
listener.exitSll_reg_imm4(self)
|
| 672 |
|
|
|
| 673 |
|
|
|
| 674 |
|
|
class Slr_reg_regContext(Asm_instContext):
|
| 675 |
|
|
|
| 676 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 677 |
|
|
super(HPC16Parser.Slr_reg_regContext, self).__init__(parser)
|
| 678 |
|
|
self.copyFrom(ctx)
|
| 679 |
|
|
|
| 680 |
|
|
def REG(self, i=None):
|
| 681 |
|
|
if i is None:
|
| 682 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 683 |
|
|
else:
|
| 684 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 685 |
|
|
|
| 686 |
|
|
def enterRule(self, listener):
|
| 687 |
|
|
if hasattr(listener, "enterSlr_reg_reg"):
|
| 688 |
|
|
listener.enterSlr_reg_reg(self)
|
| 689 |
|
|
|
| 690 |
|
|
def exitRule(self, listener):
|
| 691 |
|
|
if hasattr(listener, "exitSlr_reg_reg"):
|
| 692 |
|
|
listener.exitSlr_reg_reg(self)
|
| 693 |
|
|
|
| 694 |
|
|
|
| 695 |
|
|
class ClcContext(Asm_instContext):
|
| 696 |
|
|
|
| 697 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 698 |
|
|
super(HPC16Parser.ClcContext, self).__init__(parser)
|
| 699 |
|
|
self.copyFrom(ctx)
|
| 700 |
|
|
|
| 701 |
|
|
|
| 702 |
|
|
def enterRule(self, listener):
|
| 703 |
|
|
if hasattr(listener, "enterClc"):
|
| 704 |
|
|
listener.enterClc(self)
|
| 705 |
|
|
|
| 706 |
|
|
def exitRule(self, listener):
|
| 707 |
|
|
if hasattr(listener, "exitClc"):
|
| 708 |
|
|
listener.exitClc(self)
|
| 709 |
|
|
|
| 710 |
|
|
|
| 711 |
|
|
class Jnae_imm7Context(Asm_instContext):
|
| 712 |
|
|
|
| 713 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 714 |
|
|
super(HPC16Parser.Jnae_imm7Context, self).__init__(parser)
|
| 715 |
|
|
self.copyFrom(ctx)
|
| 716 |
|
|
|
| 717 |
|
|
def IMM(self):
|
| 718 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 719 |
|
|
|
| 720 |
|
|
def enterRule(self, listener):
|
| 721 |
|
|
if hasattr(listener, "enterJnae_imm7"):
|
| 722 |
|
|
listener.enterJnae_imm7(self)
|
| 723 |
|
|
|
| 724 |
|
|
def exitRule(self, listener):
|
| 725 |
|
|
if hasattr(listener, "exitJnae_imm7"):
|
| 726 |
|
|
listener.exitJnae_imm7(self)
|
| 727 |
|
|
|
| 728 |
|
|
|
| 729 |
|
|
class CliContext(Asm_instContext):
|
| 730 |
|
|
|
| 731 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 732 |
|
|
super(HPC16Parser.CliContext, self).__init__(parser)
|
| 733 |
|
|
self.copyFrom(ctx)
|
| 734 |
|
|
|
| 735 |
|
|
|
| 736 |
|
|
def enterRule(self, listener):
|
| 737 |
|
|
if hasattr(listener, "enterCli"):
|
| 738 |
|
|
listener.enterCli(self)
|
| 739 |
|
|
|
| 740 |
|
|
def exitRule(self, listener):
|
| 741 |
|
|
if hasattr(listener, "exitCli"):
|
| 742 |
|
|
listener.exitCli(self)
|
| 743 |
|
|
|
| 744 |
|
|
|
| 745 |
|
|
class Jae_imm7Context(Asm_instContext):
|
| 746 |
|
|
|
| 747 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 748 |
|
|
super(HPC16Parser.Jae_imm7Context, self).__init__(parser)
|
| 749 |
|
|
self.copyFrom(ctx)
|
| 750 |
|
|
|
| 751 |
|
|
def IMM(self):
|
| 752 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 753 |
|
|
|
| 754 |
|
|
def enterRule(self, listener):
|
| 755 |
|
|
if hasattr(listener, "enterJae_imm7"):
|
| 756 |
|
|
listener.enterJae_imm7(self)
|
| 757 |
|
|
|
| 758 |
|
|
def exitRule(self, listener):
|
| 759 |
|
|
if hasattr(listener, "exitJae_imm7"):
|
| 760 |
|
|
listener.exitJae_imm7(self)
|
| 761 |
|
|
|
| 762 |
|
|
|
| 763 |
|
|
class StcContext(Asm_instContext):
|
| 764 |
|
|
|
| 765 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 766 |
|
|
super(HPC16Parser.StcContext, self).__init__(parser)
|
| 767 |
|
|
self.copyFrom(ctx)
|
| 768 |
|
|
|
| 769 |
|
|
|
| 770 |
|
|
def enterRule(self, listener):
|
| 771 |
|
|
if hasattr(listener, "enterStc"):
|
| 772 |
|
|
listener.enterStc(self)
|
| 773 |
|
|
|
| 774 |
|
|
def exitRule(self, listener):
|
| 775 |
|
|
if hasattr(listener, "exitStc"):
|
| 776 |
|
|
listener.exitStc(self)
|
| 777 |
|
|
|
| 778 |
|
|
|
| 779 |
|
|
class Jnl_imm7Context(Asm_instContext):
|
| 780 |
|
|
|
| 781 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 782 |
|
|
super(HPC16Parser.Jnl_imm7Context, self).__init__(parser)
|
| 783 |
|
|
self.copyFrom(ctx)
|
| 784 |
|
|
|
| 785 |
|
|
def IMM(self):
|
| 786 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 787 |
|
|
|
| 788 |
|
|
def enterRule(self, listener):
|
| 789 |
|
|
if hasattr(listener, "enterJnl_imm7"):
|
| 790 |
|
|
listener.enterJnl_imm7(self)
|
| 791 |
|
|
|
| 792 |
|
|
def exitRule(self, listener):
|
| 793 |
|
|
if hasattr(listener, "exitJnl_imm7"):
|
| 794 |
|
|
listener.exitJnl_imm7(self)
|
| 795 |
|
|
|
| 796 |
|
|
|
| 797 |
|
|
class Ror_reg_imm4Context(Asm_instContext):
|
| 798 |
|
|
|
| 799 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 800 |
|
|
super(HPC16Parser.Ror_reg_imm4Context, self).__init__(parser)
|
| 801 |
|
|
self.copyFrom(ctx)
|
| 802 |
|
|
|
| 803 |
|
|
def REG(self):
|
| 804 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 805 |
|
|
def IMM(self):
|
| 806 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 807 |
|
|
|
| 808 |
|
|
def enterRule(self, listener):
|
| 809 |
|
|
if hasattr(listener, "enterRor_reg_imm4"):
|
| 810 |
|
|
listener.enterRor_reg_imm4(self)
|
| 811 |
|
|
|
| 812 |
|
|
def exitRule(self, listener):
|
| 813 |
|
|
if hasattr(listener, "exitRor_reg_imm4"):
|
| 814 |
|
|
listener.exitRor_reg_imm4(self)
|
| 815 |
|
|
|
| 816 |
|
|
|
| 817 |
|
|
class StiContext(Asm_instContext):
|
| 818 |
|
|
|
| 819 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 820 |
|
|
super(HPC16Parser.StiContext, self).__init__(parser)
|
| 821 |
|
|
self.copyFrom(ctx)
|
| 822 |
|
|
|
| 823 |
|
|
|
| 824 |
|
|
def enterRule(self, listener):
|
| 825 |
|
|
if hasattr(listener, "enterSti"):
|
| 826 |
|
|
listener.enterSti(self)
|
| 827 |
|
|
|
| 828 |
|
|
def exitRule(self, listener):
|
| 829 |
|
|
if hasattr(listener, "exitSti"):
|
| 830 |
|
|
listener.exitSti(self)
|
| 831 |
|
|
|
| 832 |
|
|
|
| 833 |
|
|
class Cmp_reg_imm16Context(Asm_instContext):
|
| 834 |
|
|
|
| 835 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 836 |
|
|
super(HPC16Parser.Cmp_reg_imm16Context, self).__init__(parser)
|
| 837 |
|
|
self.copyFrom(ctx)
|
| 838 |
|
|
|
| 839 |
|
|
def REG(self):
|
| 840 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 841 |
|
|
def IMM(self):
|
| 842 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 843 |
|
|
|
| 844 |
|
|
def enterRule(self, listener):
|
| 845 |
|
|
if hasattr(listener, "enterCmp_reg_imm16"):
|
| 846 |
|
|
listener.enterCmp_reg_imm16(self)
|
| 847 |
|
|
|
| 848 |
|
|
def exitRule(self, listener):
|
| 849 |
|
|
if hasattr(listener, "exitCmp_reg_imm16"):
|
| 850 |
|
|
listener.exitCmp_reg_imm16(self)
|
| 851 |
|
|
|
| 852 |
|
|
|
| 853 |
|
|
class Jnle_imm7Context(Asm_instContext):
|
| 854 |
|
|
|
| 855 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 856 |
|
|
super(HPC16Parser.Jnle_imm7Context, self).__init__(parser)
|
| 857 |
|
|
self.copyFrom(ctx)
|
| 858 |
|
|
|
| 859 |
|
|
def IMM(self):
|
| 860 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 861 |
|
|
|
| 862 |
|
|
def enterRule(self, listener):
|
| 863 |
|
|
if hasattr(listener, "enterJnle_imm7"):
|
| 864 |
|
|
listener.enterJnle_imm7(self)
|
| 865 |
|
|
|
| 866 |
|
|
def exitRule(self, listener):
|
| 867 |
|
|
if hasattr(listener, "exitJnle_imm7"):
|
| 868 |
|
|
listener.exitJnle_imm7(self)
|
| 869 |
|
|
|
| 870 |
|
|
|
| 871 |
|
|
class Rol_reg_regContext(Asm_instContext):
|
| 872 |
|
|
|
| 873 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 874 |
|
|
super(HPC16Parser.Rol_reg_regContext, self).__init__(parser)
|
| 875 |
|
|
self.copyFrom(ctx)
|
| 876 |
|
|
|
| 877 |
|
|
def REG(self, i=None):
|
| 878 |
|
|
if i is None:
|
| 879 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 880 |
|
|
else:
|
| 881 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 882 |
|
|
|
| 883 |
|
|
def enterRule(self, listener):
|
| 884 |
|
|
if hasattr(listener, "enterRol_reg_reg"):
|
| 885 |
|
|
listener.enterRol_reg_reg(self)
|
| 886 |
|
|
|
| 887 |
|
|
def exitRule(self, listener):
|
| 888 |
|
|
if hasattr(listener, "exitRol_reg_reg"):
|
| 889 |
|
|
listener.exitRol_reg_reg(self)
|
| 890 |
|
|
|
| 891 |
|
|
|
| 892 |
|
|
class Slr_reg_imm4Context(Asm_instContext):
|
| 893 |
|
|
|
| 894 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 895 |
|
|
super(HPC16Parser.Slr_reg_imm4Context, self).__init__(parser)
|
| 896 |
|
|
self.copyFrom(ctx)
|
| 897 |
|
|
|
| 898 |
|
|
def REG(self):
|
| 899 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 900 |
|
|
def IMM(self):
|
| 901 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 902 |
|
|
|
| 903 |
|
|
def enterRule(self, listener):
|
| 904 |
|
|
if hasattr(listener, "enterSlr_reg_imm4"):
|
| 905 |
|
|
listener.enterSlr_reg_imm4(self)
|
| 906 |
|
|
|
| 907 |
|
|
def exitRule(self, listener):
|
| 908 |
|
|
if hasattr(listener, "exitSlr_reg_imm4"):
|
| 909 |
|
|
listener.exitSlr_reg_imm4(self)
|
| 910 |
|
|
|
| 911 |
|
|
|
| 912 |
|
|
class Mov_reg_regContext(Asm_instContext):
|
| 913 |
|
|
|
| 914 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 915 |
|
|
super(HPC16Parser.Mov_reg_regContext, self).__init__(parser)
|
| 916 |
|
|
self.copyFrom(ctx)
|
| 917 |
|
|
|
| 918 |
|
|
def REG(self, i=None):
|
| 919 |
|
|
if i is None:
|
| 920 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 921 |
|
|
else:
|
| 922 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 923 |
|
|
|
| 924 |
|
|
def enterRule(self, listener):
|
| 925 |
|
|
if hasattr(listener, "enterMov_reg_reg"):
|
| 926 |
|
|
listener.enterMov_reg_reg(self)
|
| 927 |
|
|
|
| 928 |
|
|
def exitRule(self, listener):
|
| 929 |
|
|
if hasattr(listener, "exitMov_reg_reg"):
|
| 930 |
|
|
listener.exitMov_reg_reg(self)
|
| 931 |
|
|
|
| 932 |
|
|
|
| 933 |
|
|
class Li_sp_imm16Context(Asm_instContext):
|
| 934 |
|
|
|
| 935 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 936 |
|
|
super(HPC16Parser.Li_sp_imm16Context, self).__init__(parser)
|
| 937 |
|
|
self.copyFrom(ctx)
|
| 938 |
|
|
|
| 939 |
|
|
def STK_PTR(self):
|
| 940 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 941 |
|
|
def IMM(self):
|
| 942 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 943 |
|
|
|
| 944 |
|
|
def enterRule(self, listener):
|
| 945 |
|
|
if hasattr(listener, "enterLi_sp_imm16"):
|
| 946 |
|
|
listener.enterLi_sp_imm16(self)
|
| 947 |
|
|
|
| 948 |
|
|
def exitRule(self, listener):
|
| 949 |
|
|
if hasattr(listener, "exitLi_sp_imm16"):
|
| 950 |
|
|
listener.exitLi_sp_imm16(self)
|
| 951 |
|
|
|
| 952 |
|
|
|
| 953 |
|
|
class Rol_reg_imm4Context(Asm_instContext):
|
| 954 |
|
|
|
| 955 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 956 |
|
|
super(HPC16Parser.Rol_reg_imm4Context, self).__init__(parser)
|
| 957 |
|
|
self.copyFrom(ctx)
|
| 958 |
|
|
|
| 959 |
|
|
def REG(self):
|
| 960 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 961 |
|
|
def IMM(self):
|
| 962 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 963 |
|
|
|
| 964 |
|
|
def enterRule(self, listener):
|
| 965 |
|
|
if hasattr(listener, "enterRol_reg_imm4"):
|
| 966 |
|
|
listener.enterRol_reg_imm4(self)
|
| 967 |
|
|
|
| 968 |
|
|
def exitRule(self, listener):
|
| 969 |
|
|
if hasattr(listener, "exitRol_reg_imm4"):
|
| 970 |
|
|
listener.exitRol_reg_imm4(self)
|
| 971 |
|
|
|
| 972 |
|
|
|
| 973 |
|
|
class And_reg_regContext(Asm_instContext):
|
| 974 |
|
|
|
| 975 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 976 |
|
|
super(HPC16Parser.And_reg_regContext, self).__init__(parser)
|
| 977 |
|
|
self.copyFrom(ctx)
|
| 978 |
|
|
|
| 979 |
|
|
def REG(self, i=None):
|
| 980 |
|
|
if i is None:
|
| 981 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 982 |
|
|
else:
|
| 983 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 984 |
|
|
|
| 985 |
|
|
def enterRule(self, listener):
|
| 986 |
|
|
if hasattr(listener, "enterAnd_reg_reg"):
|
| 987 |
|
|
listener.enterAnd_reg_reg(self)
|
| 988 |
|
|
|
| 989 |
|
|
def exitRule(self, listener):
|
| 990 |
|
|
if hasattr(listener, "exitAnd_reg_reg"):
|
| 991 |
|
|
listener.exitAnd_reg_reg(self)
|
| 992 |
|
|
|
| 993 |
|
|
|
| 994 |
|
|
class CmcContext(Asm_instContext):
|
| 995 |
|
|
|
| 996 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 997 |
|
|
super(HPC16Parser.CmcContext, self).__init__(parser)
|
| 998 |
|
|
self.copyFrom(ctx)
|
| 999 |
|
|
|
| 1000 |
|
|
|
| 1001 |
|
|
def enterRule(self, listener):
|
| 1002 |
|
|
if hasattr(listener, "enterCmc"):
|
| 1003 |
|
|
listener.enterCmc(self)
|
| 1004 |
|
|
|
| 1005 |
|
|
def exitRule(self, listener):
|
| 1006 |
|
|
if hasattr(listener, "exitCmc"):
|
| 1007 |
|
|
listener.exitCmc(self)
|
| 1008 |
|
|
|
| 1009 |
|
|
|
| 1010 |
|
|
class Js_imm7Context(Asm_instContext):
|
| 1011 |
|
|
|
| 1012 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1013 |
|
|
super(HPC16Parser.Js_imm7Context, self).__init__(parser)
|
| 1014 |
|
|
self.copyFrom(ctx)
|
| 1015 |
|
|
|
| 1016 |
|
|
def IMM(self):
|
| 1017 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1018 |
|
|
|
| 1019 |
|
|
def enterRule(self, listener):
|
| 1020 |
|
|
if hasattr(listener, "enterJs_imm7"):
|
| 1021 |
|
|
listener.enterJs_imm7(self)
|
| 1022 |
|
|
|
| 1023 |
|
|
def exitRule(self, listener):
|
| 1024 |
|
|
if hasattr(listener, "exitJs_imm7"):
|
| 1025 |
|
|
listener.exitJs_imm7(self)
|
| 1026 |
|
|
|
| 1027 |
|
|
|
| 1028 |
|
|
class Acall_regContext(Asm_instContext):
|
| 1029 |
|
|
|
| 1030 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1031 |
|
|
super(HPC16Parser.Acall_regContext, self).__init__(parser)
|
| 1032 |
|
|
self.copyFrom(ctx)
|
| 1033 |
|
|
|
| 1034 |
|
|
def REG(self):
|
| 1035 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1036 |
|
|
|
| 1037 |
|
|
def enterRule(self, listener):
|
| 1038 |
|
|
if hasattr(listener, "enterAcall_reg"):
|
| 1039 |
|
|
listener.enterAcall_reg(self)
|
| 1040 |
|
|
|
| 1041 |
|
|
def exitRule(self, listener):
|
| 1042 |
|
|
if hasattr(listener, "exitAcall_reg"):
|
| 1043 |
|
|
listener.exitAcall_reg(self)
|
| 1044 |
|
|
|
| 1045 |
|
|
|
| 1046 |
|
|
class Dec_regContext(Asm_instContext):
|
| 1047 |
|
|
|
| 1048 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1049 |
|
|
super(HPC16Parser.Dec_regContext, self).__init__(parser)
|
| 1050 |
|
|
self.copyFrom(ctx)
|
| 1051 |
|
|
|
| 1052 |
|
|
def REG(self):
|
| 1053 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1054 |
|
|
|
| 1055 |
|
|
def enterRule(self, listener):
|
| 1056 |
|
|
if hasattr(listener, "enterDec_reg"):
|
| 1057 |
|
|
listener.enterDec_reg(self)
|
| 1058 |
|
|
|
| 1059 |
|
|
def exitRule(self, listener):
|
| 1060 |
|
|
if hasattr(listener, "exitDec_reg"):
|
| 1061 |
|
|
listener.exitDec_reg(self)
|
| 1062 |
|
|
|
| 1063 |
|
|
|
| 1064 |
|
|
class Test_reg_imm16Context(Asm_instContext):
|
| 1065 |
|
|
|
| 1066 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1067 |
|
|
super(HPC16Parser.Test_reg_imm16Context, self).__init__(parser)
|
| 1068 |
|
|
self.copyFrom(ctx)
|
| 1069 |
|
|
|
| 1070 |
|
|
def REG(self):
|
| 1071 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1072 |
|
|
def IMM(self):
|
| 1073 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1074 |
|
|
|
| 1075 |
|
|
def enterRule(self, listener):
|
| 1076 |
|
|
if hasattr(listener, "enterTest_reg_imm16"):
|
| 1077 |
|
|
listener.enterTest_reg_imm16(self)
|
| 1078 |
|
|
|
| 1079 |
|
|
def exitRule(self, listener):
|
| 1080 |
|
|
if hasattr(listener, "exitTest_reg_imm16"):
|
| 1081 |
|
|
listener.exitTest_reg_imm16(self)
|
| 1082 |
|
|
|
| 1083 |
|
|
|
| 1084 |
|
|
class And_reg_imm16Context(Asm_instContext):
|
| 1085 |
|
|
|
| 1086 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1087 |
|
|
super(HPC16Parser.And_reg_imm16Context, self).__init__(parser)
|
| 1088 |
|
|
self.copyFrom(ctx)
|
| 1089 |
|
|
|
| 1090 |
|
|
def REG(self):
|
| 1091 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1092 |
|
|
def IMM(self):
|
| 1093 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1094 |
|
|
|
| 1095 |
|
|
def enterRule(self, listener):
|
| 1096 |
|
|
if hasattr(listener, "enterAnd_reg_imm16"):
|
| 1097 |
|
|
listener.enterAnd_reg_imm16(self)
|
| 1098 |
|
|
|
| 1099 |
|
|
def exitRule(self, listener):
|
| 1100 |
|
|
if hasattr(listener, "exitAnd_reg_imm16"):
|
| 1101 |
|
|
listener.exitAnd_reg_imm16(self)
|
| 1102 |
|
|
|
| 1103 |
|
|
|
| 1104 |
|
|
class Sbb_reg_imm16Context(Asm_instContext):
|
| 1105 |
|
|
|
| 1106 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1107 |
|
|
super(HPC16Parser.Sbb_reg_imm16Context, self).__init__(parser)
|
| 1108 |
|
|
self.copyFrom(ctx)
|
| 1109 |
|
|
|
| 1110 |
|
|
def REG(self):
|
| 1111 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1112 |
|
|
def IMM(self):
|
| 1113 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1114 |
|
|
|
| 1115 |
|
|
def enterRule(self, listener):
|
| 1116 |
|
|
if hasattr(listener, "enterSbb_reg_imm16"):
|
| 1117 |
|
|
listener.enterSbb_reg_imm16(self)
|
| 1118 |
|
|
|
| 1119 |
|
|
def exitRule(self, listener):
|
| 1120 |
|
|
if hasattr(listener, "exitSbb_reg_imm16"):
|
| 1121 |
|
|
listener.exitSbb_reg_imm16(self)
|
| 1122 |
|
|
|
| 1123 |
|
|
|
| 1124 |
|
|
class Jbe_imm7Context(Asm_instContext):
|
| 1125 |
|
|
|
| 1126 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1127 |
|
|
super(HPC16Parser.Jbe_imm7Context, self).__init__(parser)
|
| 1128 |
|
|
self.copyFrom(ctx)
|
| 1129 |
|
|
|
| 1130 |
|
|
def IMM(self):
|
| 1131 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1132 |
|
|
|
| 1133 |
|
|
def enterRule(self, listener):
|
| 1134 |
|
|
if hasattr(listener, "enterJbe_imm7"):
|
| 1135 |
|
|
listener.enterJbe_imm7(self)
|
| 1136 |
|
|
|
| 1137 |
|
|
def exitRule(self, listener):
|
| 1138 |
|
|
if hasattr(listener, "exitJbe_imm7"):
|
| 1139 |
|
|
listener.exitJbe_imm7(self)
|
| 1140 |
|
|
|
| 1141 |
|
|
|
| 1142 |
|
|
class Xor_reg_regContext(Asm_instContext):
|
| 1143 |
|
|
|
| 1144 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1145 |
|
|
super(HPC16Parser.Xor_reg_regContext, self).__init__(parser)
|
| 1146 |
|
|
self.copyFrom(ctx)
|
| 1147 |
|
|
|
| 1148 |
|
|
def REG(self, i=None):
|
| 1149 |
|
|
if i is None:
|
| 1150 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1151 |
|
|
else:
|
| 1152 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1153 |
|
|
|
| 1154 |
|
|
def enterRule(self, listener):
|
| 1155 |
|
|
if hasattr(listener, "enterXor_reg_reg"):
|
| 1156 |
|
|
listener.enterXor_reg_reg(self)
|
| 1157 |
|
|
|
| 1158 |
|
|
def exitRule(self, listener):
|
| 1159 |
|
|
if hasattr(listener, "exitXor_reg_reg"):
|
| 1160 |
|
|
listener.exitXor_reg_reg(self)
|
| 1161 |
|
|
|
| 1162 |
|
|
|
| 1163 |
|
|
class Jmp_regContext(Asm_instContext):
|
| 1164 |
|
|
|
| 1165 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1166 |
|
|
super(HPC16Parser.Jmp_regContext, self).__init__(parser)
|
| 1167 |
|
|
self.copyFrom(ctx)
|
| 1168 |
|
|
|
| 1169 |
|
|
def REG(self):
|
| 1170 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1171 |
|
|
|
| 1172 |
|
|
def enterRule(self, listener):
|
| 1173 |
|
|
if hasattr(listener, "enterJmp_reg"):
|
| 1174 |
|
|
listener.enterJmp_reg(self)
|
| 1175 |
|
|
|
| 1176 |
|
|
def exitRule(self, listener):
|
| 1177 |
|
|
if hasattr(listener, "exitJmp_reg"):
|
| 1178 |
|
|
listener.exitJmp_reg(self)
|
| 1179 |
|
|
|
| 1180 |
|
|
|
| 1181 |
|
|
class Sbb_reg_regContext(Asm_instContext):
|
| 1182 |
|
|
|
| 1183 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1184 |
|
|
super(HPC16Parser.Sbb_reg_regContext, self).__init__(parser)
|
| 1185 |
|
|
self.copyFrom(ctx)
|
| 1186 |
|
|
|
| 1187 |
|
|
def REG(self, i=None):
|
| 1188 |
|
|
if i is None:
|
| 1189 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1190 |
|
|
else:
|
| 1191 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1192 |
|
|
|
| 1193 |
|
|
def enterRule(self, listener):
|
| 1194 |
|
|
if hasattr(listener, "enterSbb_reg_reg"):
|
| 1195 |
|
|
listener.enterSbb_reg_reg(self)
|
| 1196 |
|
|
|
| 1197 |
|
|
def exitRule(self, listener):
|
| 1198 |
|
|
if hasattr(listener, "exitSbb_reg_reg"):
|
| 1199 |
|
|
listener.exitSbb_reg_reg(self)
|
| 1200 |
|
|
|
| 1201 |
|
|
|
| 1202 |
|
|
class IntoContext(Asm_instContext):
|
| 1203 |
|
|
|
| 1204 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1205 |
|
|
super(HPC16Parser.IntoContext, self).__init__(parser)
|
| 1206 |
|
|
self.copyFrom(ctx)
|
| 1207 |
|
|
|
| 1208 |
|
|
|
| 1209 |
|
|
def enterRule(self, listener):
|
| 1210 |
|
|
if hasattr(listener, "enterInto"):
|
| 1211 |
|
|
listener.enterInto(self)
|
| 1212 |
|
|
|
| 1213 |
|
|
def exitRule(self, listener):
|
| 1214 |
|
|
if hasattr(listener, "exitInto"):
|
| 1215 |
|
|
listener.exitInto(self)
|
| 1216 |
|
|
|
| 1217 |
|
|
|
| 1218 |
|
|
class Lbsx_reg_regContext(Asm_instContext):
|
| 1219 |
|
|
|
| 1220 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1221 |
|
|
super(HPC16Parser.Lbsx_reg_regContext, self).__init__(parser)
|
| 1222 |
|
|
self.copyFrom(ctx)
|
| 1223 |
|
|
|
| 1224 |
|
|
def REG(self, i=None):
|
| 1225 |
|
|
if i is None:
|
| 1226 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1227 |
|
|
else:
|
| 1228 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1229 |
|
|
|
| 1230 |
|
|
def enterRule(self, listener):
|
| 1231 |
|
|
if hasattr(listener, "enterLbsx_reg_reg"):
|
| 1232 |
|
|
listener.enterLbsx_reg_reg(self)
|
| 1233 |
|
|
|
| 1234 |
|
|
def exitRule(self, listener):
|
| 1235 |
|
|
if hasattr(listener, "exitLbsx_reg_reg"):
|
| 1236 |
|
|
listener.exitLbsx_reg_reg(self)
|
| 1237 |
|
|
|
| 1238 |
|
|
|
| 1239 |
|
|
class St_reg_sp_imm16Context(Asm_instContext):
|
| 1240 |
|
|
|
| 1241 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1242 |
|
|
super(HPC16Parser.St_reg_sp_imm16Context, self).__init__(parser)
|
| 1243 |
|
|
self.copyFrom(ctx)
|
| 1244 |
|
|
|
| 1245 |
|
|
def REG(self):
|
| 1246 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1247 |
|
|
def STK_PTR(self):
|
| 1248 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 1249 |
|
|
def IMM(self):
|
| 1250 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1251 |
|
|
|
| 1252 |
|
|
def enterRule(self, listener):
|
| 1253 |
|
|
if hasattr(listener, "enterSt_reg_sp_imm16"):
|
| 1254 |
|
|
listener.enterSt_reg_sp_imm16(self)
|
| 1255 |
|
|
|
| 1256 |
|
|
def exitRule(self, listener):
|
| 1257 |
|
|
if hasattr(listener, "exitSt_reg_sp_imm16"):
|
| 1258 |
|
|
listener.exitSt_reg_sp_imm16(self)
|
| 1259 |
|
|
|
| 1260 |
|
|
|
| 1261 |
|
|
class Ld_reg_regContext(Asm_instContext):
|
| 1262 |
|
|
|
| 1263 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1264 |
|
|
super(HPC16Parser.Ld_reg_regContext, self).__init__(parser)
|
| 1265 |
|
|
self.copyFrom(ctx)
|
| 1266 |
|
|
|
| 1267 |
|
|
def REG(self, i=None):
|
| 1268 |
|
|
if i is None:
|
| 1269 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1270 |
|
|
else:
|
| 1271 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1272 |
|
|
|
| 1273 |
|
|
def enterRule(self, listener):
|
| 1274 |
|
|
if hasattr(listener, "enterLd_reg_reg"):
|
| 1275 |
|
|
listener.enterLd_reg_reg(self)
|
| 1276 |
|
|
|
| 1277 |
|
|
def exitRule(self, listener):
|
| 1278 |
|
|
if hasattr(listener, "exitLd_reg_reg"):
|
| 1279 |
|
|
listener.exitLd_reg_reg(self)
|
| 1280 |
|
|
|
| 1281 |
|
|
|
| 1282 |
|
|
class Jnb_imm7Context(Asm_instContext):
|
| 1283 |
|
|
|
| 1284 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1285 |
|
|
super(HPC16Parser.Jnb_imm7Context, self).__init__(parser)
|
| 1286 |
|
|
self.copyFrom(ctx)
|
| 1287 |
|
|
|
| 1288 |
|
|
def IMM(self):
|
| 1289 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1290 |
|
|
|
| 1291 |
|
|
def enterRule(self, listener):
|
| 1292 |
|
|
if hasattr(listener, "enterJnb_imm7"):
|
| 1293 |
|
|
listener.enterJnb_imm7(self)
|
| 1294 |
|
|
|
| 1295 |
|
|
def exitRule(self, listener):
|
| 1296 |
|
|
if hasattr(listener, "exitJnb_imm7"):
|
| 1297 |
|
|
listener.exitJnb_imm7(self)
|
| 1298 |
|
|
|
| 1299 |
|
|
|
| 1300 |
|
|
class Sar_reg_regContext(Asm_instContext):
|
| 1301 |
|
|
|
| 1302 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1303 |
|
|
super(HPC16Parser.Sar_reg_regContext, self).__init__(parser)
|
| 1304 |
|
|
self.copyFrom(ctx)
|
| 1305 |
|
|
|
| 1306 |
|
|
def REG(self, i=None):
|
| 1307 |
|
|
if i is None:
|
| 1308 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1309 |
|
|
else:
|
| 1310 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1311 |
|
|
|
| 1312 |
|
|
def enterRule(self, listener):
|
| 1313 |
|
|
if hasattr(listener, "enterSar_reg_reg"):
|
| 1314 |
|
|
listener.enterSar_reg_reg(self)
|
| 1315 |
|
|
|
| 1316 |
|
|
def exitRule(self, listener):
|
| 1317 |
|
|
if hasattr(listener, "exitSar_reg_reg"):
|
| 1318 |
|
|
listener.exitSar_reg_reg(self)
|
| 1319 |
|
|
|
| 1320 |
|
|
|
| 1321 |
|
|
class Jo_imm7Context(Asm_instContext):
|
| 1322 |
|
|
|
| 1323 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1324 |
|
|
super(HPC16Parser.Jo_imm7Context, self).__init__(parser)
|
| 1325 |
|
|
self.copyFrom(ctx)
|
| 1326 |
|
|
|
| 1327 |
|
|
def IMM(self):
|
| 1328 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1329 |
|
|
|
| 1330 |
|
|
def enterRule(self, listener):
|
| 1331 |
|
|
if hasattr(listener, "enterJo_imm7"):
|
| 1332 |
|
|
listener.enterJo_imm7(self)
|
| 1333 |
|
|
|
| 1334 |
|
|
def exitRule(self, listener):
|
| 1335 |
|
|
if hasattr(listener, "exitJo_imm7"):
|
| 1336 |
|
|
listener.exitJo_imm7(self)
|
| 1337 |
|
|
|
| 1338 |
|
|
|
| 1339 |
|
|
class Jl_imm7Context(Asm_instContext):
|
| 1340 |
|
|
|
| 1341 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1342 |
|
|
super(HPC16Parser.Jl_imm7Context, self).__init__(parser)
|
| 1343 |
|
|
self.copyFrom(ctx)
|
| 1344 |
|
|
|
| 1345 |
|
|
def IMM(self):
|
| 1346 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1347 |
|
|
|
| 1348 |
|
|
def enterRule(self, listener):
|
| 1349 |
|
|
if hasattr(listener, "enterJl_imm7"):
|
| 1350 |
|
|
listener.enterJl_imm7(self)
|
| 1351 |
|
|
|
| 1352 |
|
|
def exitRule(self, listener):
|
| 1353 |
|
|
if hasattr(listener, "exitJl_imm7"):
|
| 1354 |
|
|
listener.exitJl_imm7(self)
|
| 1355 |
|
|
|
| 1356 |
|
|
|
| 1357 |
|
|
class Inc_regContext(Asm_instContext):
|
| 1358 |
|
|
|
| 1359 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1360 |
|
|
super(HPC16Parser.Inc_regContext, self).__init__(parser)
|
| 1361 |
|
|
self.copyFrom(ctx)
|
| 1362 |
|
|
|
| 1363 |
|
|
def REG(self):
|
| 1364 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1365 |
|
|
|
| 1366 |
|
|
def enterRule(self, listener):
|
| 1367 |
|
|
if hasattr(listener, "enterInc_reg"):
|
| 1368 |
|
|
listener.enterInc_reg(self)
|
| 1369 |
|
|
|
| 1370 |
|
|
def exitRule(self, listener):
|
| 1371 |
|
|
if hasattr(listener, "exitInc_reg"):
|
| 1372 |
|
|
listener.exitInc_reg(self)
|
| 1373 |
|
|
|
| 1374 |
|
|
|
| 1375 |
|
|
class Jmp_imm11Context(Asm_instContext):
|
| 1376 |
|
|
|
| 1377 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1378 |
|
|
super(HPC16Parser.Jmp_imm11Context, self).__init__(parser)
|
| 1379 |
|
|
self.copyFrom(ctx)
|
| 1380 |
|
|
|
| 1381 |
|
|
def IMM(self):
|
| 1382 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1383 |
|
|
|
| 1384 |
|
|
def enterRule(self, listener):
|
| 1385 |
|
|
if hasattr(listener, "enterJmp_imm11"):
|
| 1386 |
|
|
listener.enterJmp_imm11(self)
|
| 1387 |
|
|
|
| 1388 |
|
|
def exitRule(self, listener):
|
| 1389 |
|
|
if hasattr(listener, "exitJmp_imm11"):
|
| 1390 |
|
|
listener.exitJmp_imm11(self)
|
| 1391 |
|
|
|
| 1392 |
|
|
|
| 1393 |
|
|
class HaltContext(Asm_instContext):
|
| 1394 |
|
|
|
| 1395 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1396 |
|
|
super(HPC16Parser.HaltContext, self).__init__(parser)
|
| 1397 |
|
|
self.copyFrom(ctx)
|
| 1398 |
|
|
|
| 1399 |
|
|
|
| 1400 |
|
|
def enterRule(self, listener):
|
| 1401 |
|
|
if hasattr(listener, "enterHalt"):
|
| 1402 |
|
|
listener.enterHalt(self)
|
| 1403 |
|
|
|
| 1404 |
|
|
def exitRule(self, listener):
|
| 1405 |
|
|
if hasattr(listener, "exitHalt"):
|
| 1406 |
|
|
listener.exitHalt(self)
|
| 1407 |
|
|
|
| 1408 |
|
|
|
| 1409 |
|
|
class Rcr_reg_regContext(Asm_instContext):
|
| 1410 |
|
|
|
| 1411 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1412 |
|
|
super(HPC16Parser.Rcr_reg_regContext, self).__init__(parser)
|
| 1413 |
|
|
self.copyFrom(ctx)
|
| 1414 |
|
|
|
| 1415 |
|
|
def REG(self, i=None):
|
| 1416 |
|
|
if i is None:
|
| 1417 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1418 |
|
|
else:
|
| 1419 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1420 |
|
|
|
| 1421 |
|
|
def enterRule(self, listener):
|
| 1422 |
|
|
if hasattr(listener, "enterRcr_reg_reg"):
|
| 1423 |
|
|
listener.enterRcr_reg_reg(self)
|
| 1424 |
|
|
|
| 1425 |
|
|
def exitRule(self, listener):
|
| 1426 |
|
|
if hasattr(listener, "exitRcr_reg_reg"):
|
| 1427 |
|
|
listener.exitRcr_reg_reg(self)
|
| 1428 |
|
|
|
| 1429 |
|
|
|
| 1430 |
|
|
class Lbzx_reg_reg_imm16Context(Asm_instContext):
|
| 1431 |
|
|
|
| 1432 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1433 |
|
|
super(HPC16Parser.Lbzx_reg_reg_imm16Context, self).__init__(parser)
|
| 1434 |
|
|
self.copyFrom(ctx)
|
| 1435 |
|
|
|
| 1436 |
|
|
def REG(self, i=None):
|
| 1437 |
|
|
if i is None:
|
| 1438 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1439 |
|
|
else:
|
| 1440 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1441 |
|
|
def IMM(self):
|
| 1442 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1443 |
|
|
|
| 1444 |
|
|
def enterRule(self, listener):
|
| 1445 |
|
|
if hasattr(listener, "enterLbzx_reg_reg_imm16"):
|
| 1446 |
|
|
listener.enterLbzx_reg_reg_imm16(self)
|
| 1447 |
|
|
|
| 1448 |
|
|
def exitRule(self, listener):
|
| 1449 |
|
|
if hasattr(listener, "exitLbzx_reg_reg_imm16"):
|
| 1450 |
|
|
listener.exitLbzx_reg_reg_imm16(self)
|
| 1451 |
|
|
|
| 1452 |
|
|
|
| 1453 |
|
|
class Int_imm4Context(Asm_instContext):
|
| 1454 |
|
|
|
| 1455 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1456 |
|
|
super(HPC16Parser.Int_imm4Context, self).__init__(parser)
|
| 1457 |
|
|
self.copyFrom(ctx)
|
| 1458 |
|
|
|
| 1459 |
|
|
def IMM(self):
|
| 1460 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1461 |
|
|
|
| 1462 |
|
|
def enterRule(self, listener):
|
| 1463 |
|
|
if hasattr(listener, "enterInt_imm4"):
|
| 1464 |
|
|
listener.enterInt_imm4(self)
|
| 1465 |
|
|
|
| 1466 |
|
|
def exitRule(self, listener):
|
| 1467 |
|
|
if hasattr(listener, "exitInt_imm4"):
|
| 1468 |
|
|
listener.exitInt_imm4(self)
|
| 1469 |
|
|
|
| 1470 |
|
|
|
| 1471 |
|
|
class Rcl_reg_imm4Context(Asm_instContext):
|
| 1472 |
|
|
|
| 1473 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1474 |
|
|
super(HPC16Parser.Rcl_reg_imm4Context, self).__init__(parser)
|
| 1475 |
|
|
self.copyFrom(ctx)
|
| 1476 |
|
|
|
| 1477 |
|
|
def REG(self):
|
| 1478 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1479 |
|
|
def IMM(self):
|
| 1480 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1481 |
|
|
|
| 1482 |
|
|
def enterRule(self, listener):
|
| 1483 |
|
|
if hasattr(listener, "enterRcl_reg_imm4"):
|
| 1484 |
|
|
listener.enterRcl_reg_imm4(self)
|
| 1485 |
|
|
|
| 1486 |
|
|
def exitRule(self, listener):
|
| 1487 |
|
|
if hasattr(listener, "exitRcl_reg_imm4"):
|
| 1488 |
|
|
listener.exitRcl_reg_imm4(self)
|
| 1489 |
|
|
|
| 1490 |
|
|
|
| 1491 |
|
|
class Sll_reg_regContext(Asm_instContext):
|
| 1492 |
|
|
|
| 1493 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1494 |
|
|
super(HPC16Parser.Sll_reg_regContext, self).__init__(parser)
|
| 1495 |
|
|
self.copyFrom(ctx)
|
| 1496 |
|
|
|
| 1497 |
|
|
def REG(self, i=None):
|
| 1498 |
|
|
if i is None:
|
| 1499 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1500 |
|
|
else:
|
| 1501 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1502 |
|
|
|
| 1503 |
|
|
def enterRule(self, listener):
|
| 1504 |
|
|
if hasattr(listener, "enterSll_reg_reg"):
|
| 1505 |
|
|
listener.enterSll_reg_reg(self)
|
| 1506 |
|
|
|
| 1507 |
|
|
def exitRule(self, listener):
|
| 1508 |
|
|
if hasattr(listener, "exitSll_reg_reg"):
|
| 1509 |
|
|
listener.exitSll_reg_reg(self)
|
| 1510 |
|
|
|
| 1511 |
|
|
|
| 1512 |
|
|
class Jne_imm7Context(Asm_instContext):
|
| 1513 |
|
|
|
| 1514 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1515 |
|
|
super(HPC16Parser.Jne_imm7Context, self).__init__(parser)
|
| 1516 |
|
|
self.copyFrom(ctx)
|
| 1517 |
|
|
|
| 1518 |
|
|
def IMM(self):
|
| 1519 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1520 |
|
|
|
| 1521 |
|
|
def enterRule(self, listener):
|
| 1522 |
|
|
if hasattr(listener, "enterJne_imm7"):
|
| 1523 |
|
|
listener.enterJne_imm7(self)
|
| 1524 |
|
|
|
| 1525 |
|
|
def exitRule(self, listener):
|
| 1526 |
|
|
if hasattr(listener, "exitJne_imm7"):
|
| 1527 |
|
|
listener.exitJne_imm7(self)
|
| 1528 |
|
|
|
| 1529 |
|
|
|
| 1530 |
|
|
class Lbzx_reg_regContext(Asm_instContext):
|
| 1531 |
|
|
|
| 1532 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1533 |
|
|
super(HPC16Parser.Lbzx_reg_regContext, self).__init__(parser)
|
| 1534 |
|
|
self.copyFrom(ctx)
|
| 1535 |
|
|
|
| 1536 |
|
|
def REG(self, i=None):
|
| 1537 |
|
|
if i is None:
|
| 1538 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1539 |
|
|
else:
|
| 1540 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1541 |
|
|
|
| 1542 |
|
|
def enterRule(self, listener):
|
| 1543 |
|
|
if hasattr(listener, "enterLbzx_reg_reg"):
|
| 1544 |
|
|
listener.enterLbzx_reg_reg(self)
|
| 1545 |
|
|
|
| 1546 |
|
|
def exitRule(self, listener):
|
| 1547 |
|
|
if hasattr(listener, "exitLbzx_reg_reg"):
|
| 1548 |
|
|
listener.exitLbzx_reg_reg(self)
|
| 1549 |
|
|
|
| 1550 |
|
|
|
| 1551 |
|
|
class Rcr_reg_imm4Context(Asm_instContext):
|
| 1552 |
|
|
|
| 1553 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1554 |
|
|
super(HPC16Parser.Rcr_reg_imm4Context, self).__init__(parser)
|
| 1555 |
|
|
self.copyFrom(ctx)
|
| 1556 |
|
|
|
| 1557 |
|
|
def REG(self):
|
| 1558 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1559 |
|
|
def IMM(self):
|
| 1560 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1561 |
|
|
|
| 1562 |
|
|
def enterRule(self, listener):
|
| 1563 |
|
|
if hasattr(listener, "enterRcr_reg_imm4"):
|
| 1564 |
|
|
listener.enterRcr_reg_imm4(self)
|
| 1565 |
|
|
|
| 1566 |
|
|
def exitRule(self, listener):
|
| 1567 |
|
|
if hasattr(listener, "exitRcr_reg_imm4"):
|
| 1568 |
|
|
listener.exitRcr_reg_imm4(self)
|
| 1569 |
|
|
|
| 1570 |
|
|
|
| 1571 |
|
|
class Sar_reg_imm4Context(Asm_instContext):
|
| 1572 |
|
|
|
| 1573 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1574 |
|
|
super(HPC16Parser.Sar_reg_imm4Context, self).__init__(parser)
|
| 1575 |
|
|
self.copyFrom(ctx)
|
| 1576 |
|
|
|
| 1577 |
|
|
def REG(self):
|
| 1578 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1579 |
|
|
def IMM(self):
|
| 1580 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1581 |
|
|
|
| 1582 |
|
|
def enterRule(self, listener):
|
| 1583 |
|
|
if hasattr(listener, "enterSar_reg_imm4"):
|
| 1584 |
|
|
listener.enterSar_reg_imm4(self)
|
| 1585 |
|
|
|
| 1586 |
|
|
def exitRule(self, listener):
|
| 1587 |
|
|
if hasattr(listener, "exitSar_reg_imm4"):
|
| 1588 |
|
|
listener.exitSar_reg_imm4(self)
|
| 1589 |
|
|
|
| 1590 |
|
|
|
| 1591 |
|
|
class Call_regContext(Asm_instContext):
|
| 1592 |
|
|
|
| 1593 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1594 |
|
|
super(HPC16Parser.Call_regContext, self).__init__(parser)
|
| 1595 |
|
|
self.copyFrom(ctx)
|
| 1596 |
|
|
|
| 1597 |
|
|
def REG(self):
|
| 1598 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1599 |
|
|
|
| 1600 |
|
|
def enterRule(self, listener):
|
| 1601 |
|
|
if hasattr(listener, "enterCall_reg"):
|
| 1602 |
|
|
listener.enterCall_reg(self)
|
| 1603 |
|
|
|
| 1604 |
|
|
def exitRule(self, listener):
|
| 1605 |
|
|
if hasattr(listener, "exitCall_reg"):
|
| 1606 |
|
|
listener.exitCall_reg(self)
|
| 1607 |
|
|
|
| 1608 |
|
|
|
| 1609 |
|
|
class Lbsx_reg_reg_imm16Context(Asm_instContext):
|
| 1610 |
|
|
|
| 1611 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1612 |
|
|
super(HPC16Parser.Lbsx_reg_reg_imm16Context, self).__init__(parser)
|
| 1613 |
|
|
self.copyFrom(ctx)
|
| 1614 |
|
|
|
| 1615 |
|
|
def REG(self, i=None):
|
| 1616 |
|
|
if i is None:
|
| 1617 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1618 |
|
|
else:
|
| 1619 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1620 |
|
|
def IMM(self):
|
| 1621 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1622 |
|
|
|
| 1623 |
|
|
def enterRule(self, listener):
|
| 1624 |
|
|
if hasattr(listener, "enterLbsx_reg_reg_imm16"):
|
| 1625 |
|
|
listener.enterLbsx_reg_reg_imm16(self)
|
| 1626 |
|
|
|
| 1627 |
|
|
def exitRule(self, listener):
|
| 1628 |
|
|
if hasattr(listener, "exitLbsx_reg_reg_imm16"):
|
| 1629 |
|
|
listener.exitLbsx_reg_reg_imm16(self)
|
| 1630 |
|
|
|
| 1631 |
|
|
|
| 1632 |
|
|
class Add_reg_imm16Context(Asm_instContext):
|
| 1633 |
|
|
|
| 1634 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1635 |
|
|
super(HPC16Parser.Add_reg_imm16Context, self).__init__(parser)
|
| 1636 |
|
|
self.copyFrom(ctx)
|
| 1637 |
|
|
|
| 1638 |
|
|
def REG(self):
|
| 1639 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1640 |
|
|
def IMM(self):
|
| 1641 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1642 |
|
|
|
| 1643 |
|
|
def enterRule(self, listener):
|
| 1644 |
|
|
if hasattr(listener, "enterAdd_reg_imm16"):
|
| 1645 |
|
|
listener.enterAdd_reg_imm16(self)
|
| 1646 |
|
|
|
| 1647 |
|
|
def exitRule(self, listener):
|
| 1648 |
|
|
if hasattr(listener, "exitAdd_reg_imm16"):
|
| 1649 |
|
|
listener.exitAdd_reg_imm16(self)
|
| 1650 |
|
|
|
| 1651 |
|
|
|
| 1652 |
|
|
class Ror_reg_regContext(Asm_instContext):
|
| 1653 |
|
|
|
| 1654 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1655 |
|
|
super(HPC16Parser.Ror_reg_regContext, self).__init__(parser)
|
| 1656 |
|
|
self.copyFrom(ctx)
|
| 1657 |
|
|
|
| 1658 |
|
|
def REG(self, i=None):
|
| 1659 |
|
|
if i is None:
|
| 1660 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1661 |
|
|
else:
|
| 1662 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1663 |
|
|
|
| 1664 |
|
|
def enterRule(self, listener):
|
| 1665 |
|
|
if hasattr(listener, "enterRor_reg_reg"):
|
| 1666 |
|
|
listener.enterRor_reg_reg(self)
|
| 1667 |
|
|
|
| 1668 |
|
|
def exitRule(self, listener):
|
| 1669 |
|
|
if hasattr(listener, "exitRor_reg_reg"):
|
| 1670 |
|
|
listener.exitRor_reg_reg(self)
|
| 1671 |
|
|
|
| 1672 |
|
|
|
| 1673 |
|
|
class Add_reg_regContext(Asm_instContext):
|
| 1674 |
|
|
|
| 1675 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1676 |
|
|
super(HPC16Parser.Add_reg_regContext, self).__init__(parser)
|
| 1677 |
|
|
self.copyFrom(ctx)
|
| 1678 |
|
|
|
| 1679 |
|
|
def REG(self, i=None):
|
| 1680 |
|
|
if i is None:
|
| 1681 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1682 |
|
|
else:
|
| 1683 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1684 |
|
|
|
| 1685 |
|
|
def enterRule(self, listener):
|
| 1686 |
|
|
if hasattr(listener, "enterAdd_reg_reg"):
|
| 1687 |
|
|
listener.enterAdd_reg_reg(self)
|
| 1688 |
|
|
|
| 1689 |
|
|
def exitRule(self, listener):
|
| 1690 |
|
|
if hasattr(listener, "exitAdd_reg_reg"):
|
| 1691 |
|
|
listener.exitAdd_reg_reg(self)
|
| 1692 |
|
|
|
| 1693 |
|
|
|
| 1694 |
|
|
class Or_reg_regContext(Asm_instContext):
|
| 1695 |
|
|
|
| 1696 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1697 |
|
|
super(HPC16Parser.Or_reg_regContext, self).__init__(parser)
|
| 1698 |
|
|
self.copyFrom(ctx)
|
| 1699 |
|
|
|
| 1700 |
|
|
def REG(self, i=None):
|
| 1701 |
|
|
if i is None:
|
| 1702 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1703 |
|
|
else:
|
| 1704 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1705 |
|
|
|
| 1706 |
|
|
def enterRule(self, listener):
|
| 1707 |
|
|
if hasattr(listener, "enterOr_reg_reg"):
|
| 1708 |
|
|
listener.enterOr_reg_reg(self)
|
| 1709 |
|
|
|
| 1710 |
|
|
def exitRule(self, listener):
|
| 1711 |
|
|
if hasattr(listener, "exitOr_reg_reg"):
|
| 1712 |
|
|
listener.exitOr_reg_reg(self)
|
| 1713 |
|
|
|
| 1714 |
|
|
|
| 1715 |
|
|
class Add_sp_imm16Context(Asm_instContext):
|
| 1716 |
|
|
|
| 1717 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1718 |
|
|
super(HPC16Parser.Add_sp_imm16Context, self).__init__(parser)
|
| 1719 |
|
|
self.copyFrom(ctx)
|
| 1720 |
|
|
|
| 1721 |
|
|
def STK_PTR(self):
|
| 1722 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 1723 |
|
|
def IMM(self):
|
| 1724 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1725 |
|
|
|
| 1726 |
|
|
def enterRule(self, listener):
|
| 1727 |
|
|
if hasattr(listener, "enterAdd_sp_imm16"):
|
| 1728 |
|
|
listener.enterAdd_sp_imm16(self)
|
| 1729 |
|
|
|
| 1730 |
|
|
def exitRule(self, listener):
|
| 1731 |
|
|
if hasattr(listener, "exitAdd_sp_imm16"):
|
| 1732 |
|
|
listener.exitAdd_sp_imm16(self)
|
| 1733 |
|
|
|
| 1734 |
|
|
|
| 1735 |
|
|
class Ld_reg_reg_imm16Context(Asm_instContext):
|
| 1736 |
|
|
|
| 1737 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1738 |
|
|
super(HPC16Parser.Ld_reg_reg_imm16Context, self).__init__(parser)
|
| 1739 |
|
|
self.copyFrom(ctx)
|
| 1740 |
|
|
|
| 1741 |
|
|
def REG(self, i=None):
|
| 1742 |
|
|
if i is None:
|
| 1743 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1744 |
|
|
else:
|
| 1745 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1746 |
|
|
def IMM(self):
|
| 1747 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1748 |
|
|
|
| 1749 |
|
|
def enterRule(self, listener):
|
| 1750 |
|
|
if hasattr(listener, "enterLd_reg_reg_imm16"):
|
| 1751 |
|
|
listener.enterLd_reg_reg_imm16(self)
|
| 1752 |
|
|
|
| 1753 |
|
|
def exitRule(self, listener):
|
| 1754 |
|
|
if hasattr(listener, "exitLd_reg_reg_imm16"):
|
| 1755 |
|
|
listener.exitLd_reg_reg_imm16(self)
|
| 1756 |
|
|
|
| 1757 |
|
|
|
| 1758 |
|
|
class Cmp_reg_regContext(Asm_instContext):
|
| 1759 |
|
|
|
| 1760 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1761 |
|
|
super(HPC16Parser.Cmp_reg_regContext, self).__init__(parser)
|
| 1762 |
|
|
self.copyFrom(ctx)
|
| 1763 |
|
|
|
| 1764 |
|
|
def REG(self, i=None):
|
| 1765 |
|
|
if i is None:
|
| 1766 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1767 |
|
|
else:
|
| 1768 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1769 |
|
|
|
| 1770 |
|
|
def enterRule(self, listener):
|
| 1771 |
|
|
if hasattr(listener, "enterCmp_reg_reg"):
|
| 1772 |
|
|
listener.enterCmp_reg_reg(self)
|
| 1773 |
|
|
|
| 1774 |
|
|
def exitRule(self, listener):
|
| 1775 |
|
|
if hasattr(listener, "exitCmp_reg_reg"):
|
| 1776 |
|
|
listener.exitCmp_reg_reg(self)
|
| 1777 |
|
|
|
| 1778 |
|
|
|
| 1779 |
|
|
class RetContext(Asm_instContext):
|
| 1780 |
|
|
|
| 1781 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1782 |
|
|
super(HPC16Parser.RetContext, self).__init__(parser)
|
| 1783 |
|
|
self.copyFrom(ctx)
|
| 1784 |
|
|
|
| 1785 |
|
|
|
| 1786 |
|
|
def enterRule(self, listener):
|
| 1787 |
|
|
if hasattr(listener, "enterRet"):
|
| 1788 |
|
|
listener.enterRet(self)
|
| 1789 |
|
|
|
| 1790 |
|
|
def exitRule(self, listener):
|
| 1791 |
|
|
if hasattr(listener, "exitRet"):
|
| 1792 |
|
|
listener.exitRet(self)
|
| 1793 |
|
|
|
| 1794 |
|
|
|
| 1795 |
|
|
class Adc_reg_imm16Context(Asm_instContext):
|
| 1796 |
|
|
|
| 1797 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1798 |
|
|
super(HPC16Parser.Adc_reg_imm16Context, self).__init__(parser)
|
| 1799 |
|
|
self.copyFrom(ctx)
|
| 1800 |
|
|
|
| 1801 |
|
|
def REG(self):
|
| 1802 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1803 |
|
|
def IMM(self):
|
| 1804 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1805 |
|
|
|
| 1806 |
|
|
def enterRule(self, listener):
|
| 1807 |
|
|
if hasattr(listener, "enterAdc_reg_imm16"):
|
| 1808 |
|
|
listener.enterAdc_reg_imm16(self)
|
| 1809 |
|
|
|
| 1810 |
|
|
def exitRule(self, listener):
|
| 1811 |
|
|
if hasattr(listener, "exitAdc_reg_imm16"):
|
| 1812 |
|
|
listener.exitAdc_reg_imm16(self)
|
| 1813 |
|
|
|
| 1814 |
|
|
|
| 1815 |
|
|
class AjmpContext(Asm_instContext):
|
| 1816 |
|
|
|
| 1817 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1818 |
|
|
super(HPC16Parser.AjmpContext, self).__init__(parser)
|
| 1819 |
|
|
self.copyFrom(ctx)
|
| 1820 |
|
|
|
| 1821 |
|
|
def REG(self):
|
| 1822 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1823 |
|
|
|
| 1824 |
|
|
def enterRule(self, listener):
|
| 1825 |
|
|
if hasattr(listener, "enterAjmp"):
|
| 1826 |
|
|
listener.enterAjmp(self)
|
| 1827 |
|
|
|
| 1828 |
|
|
def exitRule(self, listener):
|
| 1829 |
|
|
if hasattr(listener, "exitAjmp"):
|
| 1830 |
|
|
listener.exitAjmp(self)
|
| 1831 |
|
|
|
| 1832 |
|
|
|
| 1833 |
|
|
class Jno_imm7Context(Asm_instContext):
|
| 1834 |
|
|
|
| 1835 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1836 |
|
|
super(HPC16Parser.Jno_imm7Context, self).__init__(parser)
|
| 1837 |
|
|
self.copyFrom(ctx)
|
| 1838 |
|
|
|
| 1839 |
|
|
def IMM(self):
|
| 1840 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1841 |
|
|
|
| 1842 |
|
|
def enterRule(self, listener):
|
| 1843 |
|
|
if hasattr(listener, "enterJno_imm7"):
|
| 1844 |
|
|
listener.enterJno_imm7(self)
|
| 1845 |
|
|
|
| 1846 |
|
|
def exitRule(self, listener):
|
| 1847 |
|
|
if hasattr(listener, "exitJno_imm7"):
|
| 1848 |
|
|
listener.exitJno_imm7(self)
|
| 1849 |
|
|
|
| 1850 |
|
|
|
| 1851 |
|
|
class Sub_sp_imm16Context(Asm_instContext):
|
| 1852 |
|
|
|
| 1853 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1854 |
|
|
super(HPC16Parser.Sub_sp_imm16Context, self).__init__(parser)
|
| 1855 |
|
|
self.copyFrom(ctx)
|
| 1856 |
|
|
|
| 1857 |
|
|
def STK_PTR(self):
|
| 1858 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 1859 |
|
|
def IMM(self):
|
| 1860 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1861 |
|
|
|
| 1862 |
|
|
def enterRule(self, listener):
|
| 1863 |
|
|
if hasattr(listener, "enterSub_sp_imm16"):
|
| 1864 |
|
|
listener.enterSub_sp_imm16(self)
|
| 1865 |
|
|
|
| 1866 |
|
|
def exitRule(self, listener):
|
| 1867 |
|
|
if hasattr(listener, "exitSub_sp_imm16"):
|
| 1868 |
|
|
listener.exitSub_sp_imm16(self)
|
| 1869 |
|
|
|
| 1870 |
|
|
|
| 1871 |
|
|
class IretContext(Asm_instContext):
|
| 1872 |
|
|
|
| 1873 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1874 |
|
|
super(HPC16Parser.IretContext, self).__init__(parser)
|
| 1875 |
|
|
self.copyFrom(ctx)
|
| 1876 |
|
|
|
| 1877 |
|
|
|
| 1878 |
|
|
def enterRule(self, listener):
|
| 1879 |
|
|
if hasattr(listener, "enterIret"):
|
| 1880 |
|
|
listener.enterIret(self)
|
| 1881 |
|
|
|
| 1882 |
|
|
def exitRule(self, listener):
|
| 1883 |
|
|
if hasattr(listener, "exitIret"):
|
| 1884 |
|
|
listener.exitIret(self)
|
| 1885 |
|
|
|
| 1886 |
|
|
|
| 1887 |
|
|
class Sub_reg_regContext(Asm_instContext):
|
| 1888 |
|
|
|
| 1889 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1890 |
|
|
super(HPC16Parser.Sub_reg_regContext, self).__init__(parser)
|
| 1891 |
|
|
self.copyFrom(ctx)
|
| 1892 |
|
|
|
| 1893 |
|
|
def REG(self, i=None):
|
| 1894 |
|
|
if i is None:
|
| 1895 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1896 |
|
|
else:
|
| 1897 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1898 |
|
|
|
| 1899 |
|
|
def enterRule(self, listener):
|
| 1900 |
|
|
if hasattr(listener, "enterSub_reg_reg"):
|
| 1901 |
|
|
listener.enterSub_reg_reg(self)
|
| 1902 |
|
|
|
| 1903 |
|
|
def exitRule(self, listener):
|
| 1904 |
|
|
if hasattr(listener, "exitSub_reg_reg"):
|
| 1905 |
|
|
listener.exitSub_reg_reg(self)
|
| 1906 |
|
|
|
| 1907 |
|
|
|
| 1908 |
|
|
class Jnz_imm7Context(Asm_instContext):
|
| 1909 |
|
|
|
| 1910 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1911 |
|
|
super(HPC16Parser.Jnz_imm7Context, self).__init__(parser)
|
| 1912 |
|
|
self.copyFrom(ctx)
|
| 1913 |
|
|
|
| 1914 |
|
|
def IMM(self):
|
| 1915 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1916 |
|
|
|
| 1917 |
|
|
def enterRule(self, listener):
|
| 1918 |
|
|
if hasattr(listener, "enterJnz_imm7"):
|
| 1919 |
|
|
listener.enterJnz_imm7(self)
|
| 1920 |
|
|
|
| 1921 |
|
|
def exitRule(self, listener):
|
| 1922 |
|
|
if hasattr(listener, "exitJnz_imm7"):
|
| 1923 |
|
|
listener.exitJnz_imm7(self)
|
| 1924 |
|
|
|
| 1925 |
|
|
|
| 1926 |
|
|
class Sal_reg_imm4Context(Asm_instContext):
|
| 1927 |
|
|
|
| 1928 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1929 |
|
|
super(HPC16Parser.Sal_reg_imm4Context, self).__init__(parser)
|
| 1930 |
|
|
self.copyFrom(ctx)
|
| 1931 |
|
|
|
| 1932 |
|
|
def REG(self):
|
| 1933 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 1934 |
|
|
def IMM(self):
|
| 1935 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1936 |
|
|
|
| 1937 |
|
|
def enterRule(self, listener):
|
| 1938 |
|
|
if hasattr(listener, "enterSal_reg_imm4"):
|
| 1939 |
|
|
listener.enterSal_reg_imm4(self)
|
| 1940 |
|
|
|
| 1941 |
|
|
def exitRule(self, listener):
|
| 1942 |
|
|
if hasattr(listener, "exitSal_reg_imm4"):
|
| 1943 |
|
|
listener.exitSal_reg_imm4(self)
|
| 1944 |
|
|
|
| 1945 |
|
|
|
| 1946 |
|
|
class Jnbe_imm7Context(Asm_instContext):
|
| 1947 |
|
|
|
| 1948 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1949 |
|
|
super(HPC16Parser.Jnbe_imm7Context, self).__init__(parser)
|
| 1950 |
|
|
self.copyFrom(ctx)
|
| 1951 |
|
|
|
| 1952 |
|
|
def IMM(self):
|
| 1953 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 1954 |
|
|
|
| 1955 |
|
|
def enterRule(self, listener):
|
| 1956 |
|
|
if hasattr(listener, "enterJnbe_imm7"):
|
| 1957 |
|
|
listener.enterJnbe_imm7(self)
|
| 1958 |
|
|
|
| 1959 |
|
|
def exitRule(self, listener):
|
| 1960 |
|
|
if hasattr(listener, "exitJnbe_imm7"):
|
| 1961 |
|
|
listener.exitJnbe_imm7(self)
|
| 1962 |
|
|
|
| 1963 |
|
|
|
| 1964 |
|
|
class Test_reg_regContext(Asm_instContext):
|
| 1965 |
|
|
|
| 1966 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1967 |
|
|
super(HPC16Parser.Test_reg_regContext, self).__init__(parser)
|
| 1968 |
|
|
self.copyFrom(ctx)
|
| 1969 |
|
|
|
| 1970 |
|
|
def REG(self, i=None):
|
| 1971 |
|
|
if i is None:
|
| 1972 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1973 |
|
|
else:
|
| 1974 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1975 |
|
|
|
| 1976 |
|
|
def enterRule(self, listener):
|
| 1977 |
|
|
if hasattr(listener, "enterTest_reg_reg"):
|
| 1978 |
|
|
listener.enterTest_reg_reg(self)
|
| 1979 |
|
|
|
| 1980 |
|
|
def exitRule(self, listener):
|
| 1981 |
|
|
if hasattr(listener, "exitTest_reg_reg"):
|
| 1982 |
|
|
listener.exitTest_reg_reg(self)
|
| 1983 |
|
|
|
| 1984 |
|
|
|
| 1985 |
|
|
class Sal_reg_regContext(Asm_instContext):
|
| 1986 |
|
|
|
| 1987 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 1988 |
|
|
super(HPC16Parser.Sal_reg_regContext, self).__init__(parser)
|
| 1989 |
|
|
self.copyFrom(ctx)
|
| 1990 |
|
|
|
| 1991 |
|
|
def REG(self, i=None):
|
| 1992 |
|
|
if i is None:
|
| 1993 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 1994 |
|
|
else:
|
| 1995 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 1996 |
|
|
|
| 1997 |
|
|
def enterRule(self, listener):
|
| 1998 |
|
|
if hasattr(listener, "enterSal_reg_reg"):
|
| 1999 |
|
|
listener.enterSal_reg_reg(self)
|
| 2000 |
|
|
|
| 2001 |
|
|
def exitRule(self, listener):
|
| 2002 |
|
|
if hasattr(listener, "exitSal_reg_reg"):
|
| 2003 |
|
|
listener.exitSal_reg_reg(self)
|
| 2004 |
|
|
|
| 2005 |
|
|
|
| 2006 |
|
|
class Jle_imm7Context(Asm_instContext):
|
| 2007 |
|
|
|
| 2008 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2009 |
|
|
super(HPC16Parser.Jle_imm7Context, self).__init__(parser)
|
| 2010 |
|
|
self.copyFrom(ctx)
|
| 2011 |
|
|
|
| 2012 |
|
|
def IMM(self):
|
| 2013 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2014 |
|
|
|
| 2015 |
|
|
def enterRule(self, listener):
|
| 2016 |
|
|
if hasattr(listener, "enterJle_imm7"):
|
| 2017 |
|
|
listener.enterJle_imm7(self)
|
| 2018 |
|
|
|
| 2019 |
|
|
def exitRule(self, listener):
|
| 2020 |
|
|
if hasattr(listener, "exitJle_imm7"):
|
| 2021 |
|
|
listener.exitJle_imm7(self)
|
| 2022 |
|
|
|
| 2023 |
|
|
|
| 2024 |
|
|
class St_reg_regContext(Asm_instContext):
|
| 2025 |
|
|
|
| 2026 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2027 |
|
|
super(HPC16Parser.St_reg_regContext, self).__init__(parser)
|
| 2028 |
|
|
self.copyFrom(ctx)
|
| 2029 |
|
|
|
| 2030 |
|
|
def REG(self, i=None):
|
| 2031 |
|
|
if i is None:
|
| 2032 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 2033 |
|
|
else:
|
| 2034 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 2035 |
|
|
|
| 2036 |
|
|
def enterRule(self, listener):
|
| 2037 |
|
|
if hasattr(listener, "enterSt_reg_reg"):
|
| 2038 |
|
|
listener.enterSt_reg_reg(self)
|
| 2039 |
|
|
|
| 2040 |
|
|
def exitRule(self, listener):
|
| 2041 |
|
|
if hasattr(listener, "exitSt_reg_reg"):
|
| 2042 |
|
|
listener.exitSt_reg_reg(self)
|
| 2043 |
|
|
|
| 2044 |
|
|
|
| 2045 |
|
|
class Xor_reg_imm16Context(Asm_instContext):
|
| 2046 |
|
|
|
| 2047 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2048 |
|
|
super(HPC16Parser.Xor_reg_imm16Context, self).__init__(parser)
|
| 2049 |
|
|
self.copyFrom(ctx)
|
| 2050 |
|
|
|
| 2051 |
|
|
def REG(self):
|
| 2052 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 2053 |
|
|
def IMM(self):
|
| 2054 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2055 |
|
|
|
| 2056 |
|
|
def enterRule(self, listener):
|
| 2057 |
|
|
if hasattr(listener, "enterXor_reg_imm16"):
|
| 2058 |
|
|
listener.enterXor_reg_imm16(self)
|
| 2059 |
|
|
|
| 2060 |
|
|
def exitRule(self, listener):
|
| 2061 |
|
|
if hasattr(listener, "exitXor_reg_imm16"):
|
| 2062 |
|
|
listener.exitXor_reg_imm16(self)
|
| 2063 |
|
|
|
| 2064 |
|
|
|
| 2065 |
|
|
class Jns_imm7Context(Asm_instContext):
|
| 2066 |
|
|
|
| 2067 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2068 |
|
|
super(HPC16Parser.Jns_imm7Context, self).__init__(parser)
|
| 2069 |
|
|
self.copyFrom(ctx)
|
| 2070 |
|
|
|
| 2071 |
|
|
def IMM(self):
|
| 2072 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2073 |
|
|
|
| 2074 |
|
|
def enterRule(self, listener):
|
| 2075 |
|
|
if hasattr(listener, "enterJns_imm7"):
|
| 2076 |
|
|
listener.enterJns_imm7(self)
|
| 2077 |
|
|
|
| 2078 |
|
|
def exitRule(self, listener):
|
| 2079 |
|
|
if hasattr(listener, "exitJns_imm7"):
|
| 2080 |
|
|
listener.exitJns_imm7(self)
|
| 2081 |
|
|
|
| 2082 |
|
|
|
| 2083 |
|
|
class Not_regContext(Asm_instContext):
|
| 2084 |
|
|
|
| 2085 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2086 |
|
|
super(HPC16Parser.Not_regContext, self).__init__(parser)
|
| 2087 |
|
|
self.copyFrom(ctx)
|
| 2088 |
|
|
|
| 2089 |
|
|
def REG(self):
|
| 2090 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 2091 |
|
|
|
| 2092 |
|
|
def enterRule(self, listener):
|
| 2093 |
|
|
if hasattr(listener, "enterNot_reg"):
|
| 2094 |
|
|
listener.enterNot_reg(self)
|
| 2095 |
|
|
|
| 2096 |
|
|
def exitRule(self, listener):
|
| 2097 |
|
|
if hasattr(listener, "exitNot_reg"):
|
| 2098 |
|
|
listener.exitNot_reg(self)
|
| 2099 |
|
|
|
| 2100 |
|
|
|
| 2101 |
|
|
class NopContext(Asm_instContext):
|
| 2102 |
|
|
|
| 2103 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2104 |
|
|
super(HPC16Parser.NopContext, self).__init__(parser)
|
| 2105 |
|
|
self.copyFrom(ctx)
|
| 2106 |
|
|
|
| 2107 |
|
|
|
| 2108 |
|
|
def enterRule(self, listener):
|
| 2109 |
|
|
if hasattr(listener, "enterNop"):
|
| 2110 |
|
|
listener.enterNop(self)
|
| 2111 |
|
|
|
| 2112 |
|
|
def exitRule(self, listener):
|
| 2113 |
|
|
if hasattr(listener, "exitNop"):
|
| 2114 |
|
|
listener.exitNop(self)
|
| 2115 |
|
|
|
| 2116 |
|
|
|
| 2117 |
|
|
class Jb_imm7Context(Asm_instContext):
|
| 2118 |
|
|
|
| 2119 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2120 |
|
|
super(HPC16Parser.Jb_imm7Context, self).__init__(parser)
|
| 2121 |
|
|
self.copyFrom(ctx)
|
| 2122 |
|
|
|
| 2123 |
|
|
def IMM(self):
|
| 2124 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2125 |
|
|
|
| 2126 |
|
|
def enterRule(self, listener):
|
| 2127 |
|
|
if hasattr(listener, "enterJb_imm7"):
|
| 2128 |
|
|
listener.enterJb_imm7(self)
|
| 2129 |
|
|
|
| 2130 |
|
|
def exitRule(self, listener):
|
| 2131 |
|
|
if hasattr(listener, "exitJb_imm7"):
|
| 2132 |
|
|
listener.exitJb_imm7(self)
|
| 2133 |
|
|
|
| 2134 |
|
|
|
| 2135 |
|
|
class Or_reg_imm16Context(Asm_instContext):
|
| 2136 |
|
|
|
| 2137 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2138 |
|
|
super(HPC16Parser.Or_reg_imm16Context, self).__init__(parser)
|
| 2139 |
|
|
self.copyFrom(ctx)
|
| 2140 |
|
|
|
| 2141 |
|
|
def REG(self):
|
| 2142 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 2143 |
|
|
def IMM(self):
|
| 2144 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2145 |
|
|
|
| 2146 |
|
|
def enterRule(self, listener):
|
| 2147 |
|
|
if hasattr(listener, "enterOr_reg_imm16"):
|
| 2148 |
|
|
listener.enterOr_reg_imm16(self)
|
| 2149 |
|
|
|
| 2150 |
|
|
def exitRule(self, listener):
|
| 2151 |
|
|
if hasattr(listener, "exitOr_reg_imm16"):
|
| 2152 |
|
|
listener.exitOr_reg_imm16(self)
|
| 2153 |
|
|
|
| 2154 |
|
|
|
| 2155 |
|
|
class Ja_imm7Context(Asm_instContext):
|
| 2156 |
|
|
|
| 2157 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2158 |
|
|
super(HPC16Parser.Ja_imm7Context, self).__init__(parser)
|
| 2159 |
|
|
self.copyFrom(ctx)
|
| 2160 |
|
|
|
| 2161 |
|
|
def IMM(self):
|
| 2162 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2163 |
|
|
|
| 2164 |
|
|
def enterRule(self, listener):
|
| 2165 |
|
|
if hasattr(listener, "enterJa_imm7"):
|
| 2166 |
|
|
listener.enterJa_imm7(self)
|
| 2167 |
|
|
|
| 2168 |
|
|
def exitRule(self, listener):
|
| 2169 |
|
|
if hasattr(listener, "exitJa_imm7"):
|
| 2170 |
|
|
listener.exitJa_imm7(self)
|
| 2171 |
|
|
|
| 2172 |
|
|
|
| 2173 |
|
|
class Jg_imm7Context(Asm_instContext):
|
| 2174 |
|
|
|
| 2175 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2176 |
|
|
super(HPC16Parser.Jg_imm7Context, self).__init__(parser)
|
| 2177 |
|
|
self.copyFrom(ctx)
|
| 2178 |
|
|
|
| 2179 |
|
|
def IMM(self):
|
| 2180 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2181 |
|
|
|
| 2182 |
|
|
def enterRule(self, listener):
|
| 2183 |
|
|
if hasattr(listener, "enterJg_imm7"):
|
| 2184 |
|
|
listener.enterJg_imm7(self)
|
| 2185 |
|
|
|
| 2186 |
|
|
def exitRule(self, listener):
|
| 2187 |
|
|
if hasattr(listener, "exitJg_imm7"):
|
| 2188 |
|
|
listener.exitJg_imm7(self)
|
| 2189 |
|
|
|
| 2190 |
|
|
|
| 2191 |
|
|
class Adc_reg_regContext(Asm_instContext):
|
| 2192 |
|
|
|
| 2193 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2194 |
|
|
super(HPC16Parser.Adc_reg_regContext, self).__init__(parser)
|
| 2195 |
|
|
self.copyFrom(ctx)
|
| 2196 |
|
|
|
| 2197 |
|
|
def REG(self, i=None):
|
| 2198 |
|
|
if i is None:
|
| 2199 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 2200 |
|
|
else:
|
| 2201 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 2202 |
|
|
|
| 2203 |
|
|
def enterRule(self, listener):
|
| 2204 |
|
|
if hasattr(listener, "enterAdc_reg_reg"):
|
| 2205 |
|
|
listener.enterAdc_reg_reg(self)
|
| 2206 |
|
|
|
| 2207 |
|
|
def exitRule(self, listener):
|
| 2208 |
|
|
if hasattr(listener, "exitAdc_reg_reg"):
|
| 2209 |
|
|
listener.exitAdc_reg_reg(self)
|
| 2210 |
|
|
|
| 2211 |
|
|
|
| 2212 |
|
|
class Pop_regContext(Asm_instContext):
|
| 2213 |
|
|
|
| 2214 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2215 |
|
|
super(HPC16Parser.Pop_regContext, self).__init__(parser)
|
| 2216 |
|
|
self.copyFrom(ctx)
|
| 2217 |
|
|
|
| 2218 |
|
|
def REG(self):
|
| 2219 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 2220 |
|
|
|
| 2221 |
|
|
def enterRule(self, listener):
|
| 2222 |
|
|
if hasattr(listener, "enterPop_reg"):
|
| 2223 |
|
|
listener.enterPop_reg(self)
|
| 2224 |
|
|
|
| 2225 |
|
|
def exitRule(self, listener):
|
| 2226 |
|
|
if hasattr(listener, "exitPop_reg"):
|
| 2227 |
|
|
listener.exitPop_reg(self)
|
| 2228 |
|
|
|
| 2229 |
|
|
|
| 2230 |
|
|
class Rcl_reg_regContext(Asm_instContext):
|
| 2231 |
|
|
|
| 2232 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2233 |
|
|
super(HPC16Parser.Rcl_reg_regContext, self).__init__(parser)
|
| 2234 |
|
|
self.copyFrom(ctx)
|
| 2235 |
|
|
|
| 2236 |
|
|
def REG(self, i=None):
|
| 2237 |
|
|
if i is None:
|
| 2238 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 2239 |
|
|
else:
|
| 2240 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 2241 |
|
|
|
| 2242 |
|
|
def enterRule(self, listener):
|
| 2243 |
|
|
if hasattr(listener, "enterRcl_reg_reg"):
|
| 2244 |
|
|
listener.enterRcl_reg_reg(self)
|
| 2245 |
|
|
|
| 2246 |
|
|
def exitRule(self, listener):
|
| 2247 |
|
|
if hasattr(listener, "exitRcl_reg_reg"):
|
| 2248 |
|
|
listener.exitRcl_reg_reg(self)
|
| 2249 |
|
|
|
| 2250 |
|
|
|
| 2251 |
|
|
class Sub_reg_imm16Context(Asm_instContext):
|
| 2252 |
|
|
|
| 2253 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2254 |
|
|
super(HPC16Parser.Sub_reg_imm16Context, self).__init__(parser)
|
| 2255 |
|
|
self.copyFrom(ctx)
|
| 2256 |
|
|
|
| 2257 |
|
|
def REG(self):
|
| 2258 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 2259 |
|
|
def IMM(self):
|
| 2260 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2261 |
|
|
|
| 2262 |
|
|
def enterRule(self, listener):
|
| 2263 |
|
|
if hasattr(listener, "enterSub_reg_imm16"):
|
| 2264 |
|
|
listener.enterSub_reg_imm16(self)
|
| 2265 |
|
|
|
| 2266 |
|
|
def exitRule(self, listener):
|
| 2267 |
|
|
if hasattr(listener, "exitSub_reg_imm16"):
|
| 2268 |
|
|
listener.exitSub_reg_imm16(self)
|
| 2269 |
|
|
|
| 2270 |
|
|
|
| 2271 |
|
|
class Jna_imm7Context(Asm_instContext):
|
| 2272 |
|
|
|
| 2273 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2274 |
|
|
super(HPC16Parser.Jna_imm7Context, self).__init__(parser)
|
| 2275 |
|
|
self.copyFrom(ctx)
|
| 2276 |
|
|
|
| 2277 |
|
|
def IMM(self):
|
| 2278 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2279 |
|
|
|
| 2280 |
|
|
def enterRule(self, listener):
|
| 2281 |
|
|
if hasattr(listener, "enterJna_imm7"):
|
| 2282 |
|
|
listener.enterJna_imm7(self)
|
| 2283 |
|
|
|
| 2284 |
|
|
def exitRule(self, listener):
|
| 2285 |
|
|
if hasattr(listener, "exitJna_imm7"):
|
| 2286 |
|
|
listener.exitJna_imm7(self)
|
| 2287 |
|
|
|
| 2288 |
|
|
|
| 2289 |
|
|
class Ld_reg_sp_imm16Context(Asm_instContext):
|
| 2290 |
|
|
|
| 2291 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2292 |
|
|
super(HPC16Parser.Ld_reg_sp_imm16Context, self).__init__(parser)
|
| 2293 |
|
|
self.copyFrom(ctx)
|
| 2294 |
|
|
|
| 2295 |
|
|
def REG(self):
|
| 2296 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 2297 |
|
|
def STK_PTR(self):
|
| 2298 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 2299 |
|
|
def IMM(self):
|
| 2300 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2301 |
|
|
|
| 2302 |
|
|
def enterRule(self, listener):
|
| 2303 |
|
|
if hasattr(listener, "enterLd_reg_sp_imm16"):
|
| 2304 |
|
|
listener.enterLd_reg_sp_imm16(self)
|
| 2305 |
|
|
|
| 2306 |
|
|
def exitRule(self, listener):
|
| 2307 |
|
|
if hasattr(listener, "exitLd_reg_sp_imm16"):
|
| 2308 |
|
|
listener.exitLd_reg_sp_imm16(self)
|
| 2309 |
|
|
|
| 2310 |
|
|
|
| 2311 |
|
|
class PushfContext(Asm_instContext):
|
| 2312 |
|
|
|
| 2313 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2314 |
|
|
super(HPC16Parser.PushfContext, self).__init__(parser)
|
| 2315 |
|
|
self.copyFrom(ctx)
|
| 2316 |
|
|
|
| 2317 |
|
|
|
| 2318 |
|
|
def enterRule(self, listener):
|
| 2319 |
|
|
if hasattr(listener, "enterPushf"):
|
| 2320 |
|
|
listener.enterPushf(self)
|
| 2321 |
|
|
|
| 2322 |
|
|
def exitRule(self, listener):
|
| 2323 |
|
|
if hasattr(listener, "exitPushf"):
|
| 2324 |
|
|
listener.exitPushf(self)
|
| 2325 |
|
|
|
| 2326 |
|
|
|
| 2327 |
|
|
class Jz_imm7Context(Asm_instContext):
|
| 2328 |
|
|
|
| 2329 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2330 |
|
|
super(HPC16Parser.Jz_imm7Context, self).__init__(parser)
|
| 2331 |
|
|
self.copyFrom(ctx)
|
| 2332 |
|
|
|
| 2333 |
|
|
def IMM(self):
|
| 2334 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2335 |
|
|
|
| 2336 |
|
|
def enterRule(self, listener):
|
| 2337 |
|
|
if hasattr(listener, "enterJz_imm7"):
|
| 2338 |
|
|
listener.enterJz_imm7(self)
|
| 2339 |
|
|
|
| 2340 |
|
|
def exitRule(self, listener):
|
| 2341 |
|
|
if hasattr(listener, "exitJz_imm7"):
|
| 2342 |
|
|
listener.exitJz_imm7(self)
|
| 2343 |
|
|
|
| 2344 |
|
|
|
| 2345 |
|
|
class Jng_imm7Context(Asm_instContext):
|
| 2346 |
|
|
|
| 2347 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2348 |
|
|
super(HPC16Parser.Jng_imm7Context, self).__init__(parser)
|
| 2349 |
|
|
self.copyFrom(ctx)
|
| 2350 |
|
|
|
| 2351 |
|
|
def IMM(self):
|
| 2352 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2353 |
|
|
|
| 2354 |
|
|
def enterRule(self, listener):
|
| 2355 |
|
|
if hasattr(listener, "enterJng_imm7"):
|
| 2356 |
|
|
listener.enterJng_imm7(self)
|
| 2357 |
|
|
|
| 2358 |
|
|
def exitRule(self, listener):
|
| 2359 |
|
|
if hasattr(listener, "exitJng_imm7"):
|
| 2360 |
|
|
listener.exitJng_imm7(self)
|
| 2361 |
|
|
|
| 2362 |
|
|
|
| 2363 |
|
|
class Jnge_imm7Context(Asm_instContext):
|
| 2364 |
|
|
|
| 2365 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2366 |
|
|
super(HPC16Parser.Jnge_imm7Context, self).__init__(parser)
|
| 2367 |
|
|
self.copyFrom(ctx)
|
| 2368 |
|
|
|
| 2369 |
|
|
def IMM(self):
|
| 2370 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2371 |
|
|
|
| 2372 |
|
|
def enterRule(self, listener):
|
| 2373 |
|
|
if hasattr(listener, "enterJnge_imm7"):
|
| 2374 |
|
|
listener.enterJnge_imm7(self)
|
| 2375 |
|
|
|
| 2376 |
|
|
def exitRule(self, listener):
|
| 2377 |
|
|
if hasattr(listener, "exitJnge_imm7"):
|
| 2378 |
|
|
listener.exitJnge_imm7(self)
|
| 2379 |
|
|
|
| 2380 |
|
|
|
| 2381 |
|
|
class St_reg_spContext(Asm_instContext):
|
| 2382 |
|
|
|
| 2383 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2384 |
|
|
super(HPC16Parser.St_reg_spContext, self).__init__(parser)
|
| 2385 |
|
|
self.copyFrom(ctx)
|
| 2386 |
|
|
|
| 2387 |
|
|
def REG(self):
|
| 2388 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 2389 |
|
|
def STK_PTR(self):
|
| 2390 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 2391 |
|
|
|
| 2392 |
|
|
def enterRule(self, listener):
|
| 2393 |
|
|
if hasattr(listener, "enterSt_reg_sp"):
|
| 2394 |
|
|
listener.enterSt_reg_sp(self)
|
| 2395 |
|
|
|
| 2396 |
|
|
def exitRule(self, listener):
|
| 2397 |
|
|
if hasattr(listener, "exitSt_reg_sp"):
|
| 2398 |
|
|
listener.exitSt_reg_sp(self)
|
| 2399 |
|
|
|
| 2400 |
|
|
|
| 2401 |
|
|
class Sb_reg_reg_imm16Context(Asm_instContext):
|
| 2402 |
|
|
|
| 2403 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2404 |
|
|
super(HPC16Parser.Sb_reg_reg_imm16Context, self).__init__(parser)
|
| 2405 |
|
|
self.copyFrom(ctx)
|
| 2406 |
|
|
|
| 2407 |
|
|
def REG(self, i=None):
|
| 2408 |
|
|
if i is None:
|
| 2409 |
|
|
return self.getTokens(HPC16Parser.REG)
|
| 2410 |
|
|
else:
|
| 2411 |
|
|
return self.getToken(HPC16Parser.REG, i)
|
| 2412 |
|
|
def IMM(self):
|
| 2413 |
|
|
return self.getToken(HPC16Parser.IMM, 0)
|
| 2414 |
|
|
|
| 2415 |
|
|
def enterRule(self, listener):
|
| 2416 |
|
|
if hasattr(listener, "enterSb_reg_reg_imm16"):
|
| 2417 |
|
|
listener.enterSb_reg_reg_imm16(self)
|
| 2418 |
|
|
|
| 2419 |
|
|
def exitRule(self, listener):
|
| 2420 |
|
|
if hasattr(listener, "exitSb_reg_reg_imm16"):
|
| 2421 |
|
|
listener.exitSb_reg_reg_imm16(self)
|
| 2422 |
|
|
|
| 2423 |
|
|
|
| 2424 |
|
|
class Mov_sp_regContext(Asm_instContext):
|
| 2425 |
|
|
|
| 2426 |
|
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext)
|
| 2427 |
|
|
super(HPC16Parser.Mov_sp_regContext, self).__init__(parser)
|
| 2428 |
|
|
self.copyFrom(ctx)
|
| 2429 |
|
|
|
| 2430 |
|
|
def STK_PTR(self):
|
| 2431 |
|
|
return self.getToken(HPC16Parser.STK_PTR, 0)
|
| 2432 |
|
|
def REG(self):
|
| 2433 |
|
|
return self.getToken(HPC16Parser.REG, 0)
|
| 2434 |
|
|
|
| 2435 |
|
|
def enterRule(self, listener):
|
| 2436 |
|
|
if hasattr(listener, "enterMov_sp_reg"):
|
| 2437 |
|
|
listener.enterMov_sp_reg(self)
|
| 2438 |
|
|
|
| 2439 |
|
|
def exitRule(self, listener):
|
| 2440 |
|
|
if hasattr(listener, "exitMov_sp_reg"):
|
| 2441 |
|
|
listener.exitMov_sp_reg(self)
|
| 2442 |
|
|
|
| 2443 |
|
|
|
| 2444 |
|
|
|
| 2445 |
|
|
def asm_inst(self):
|
| 2446 |
|
|
|
| 2447 |
|
|
localctx = HPC16Parser.Asm_instContext(self, self._ctx, self.state)
|
| 2448 |
|
|
self.enterRule(localctx, 4, self.RULE_asm_inst)
|
| 2449 |
|
|
try:
|
| 2450 |
|
|
self.state = 374
|
| 2451 |
|
|
la_ = self._interp.adaptivePredict(self._input,2,self._ctx)
|
| 2452 |
|
|
if la_ == 1:
|
| 2453 |
|
|
localctx = HPC16Parser.Mov_reg_regContext(self, localctx)
|
| 2454 |
|
|
self.enterOuterAlt(localctx, 1)
|
| 2455 |
|
|
self.state = 16
|
| 2456 |
|
|
self.match(HPC16Parser.T__0)
|
| 2457 |
|
|
self.state = 17
|
| 2458 |
|
|
self.match(HPC16Parser.REG)
|
| 2459 |
|
|
self.state = 18
|
| 2460 |
|
|
self.match(HPC16Parser.T__1)
|
| 2461 |
|
|
self.state = 19
|
| 2462 |
|
|
self.match(HPC16Parser.REG)
|
| 2463 |
|
|
pass
|
| 2464 |
|
|
|
| 2465 |
|
|
elif la_ == 2:
|
| 2466 |
|
|
localctx = HPC16Parser.Mov_sp_regContext(self, localctx)
|
| 2467 |
|
|
self.enterOuterAlt(localctx, 2)
|
| 2468 |
|
|
self.state = 20
|
| 2469 |
|
|
self.match(HPC16Parser.T__0)
|
| 2470 |
|
|
self.state = 21
|
| 2471 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 2472 |
|
|
self.state = 22
|
| 2473 |
|
|
self.match(HPC16Parser.T__1)
|
| 2474 |
|
|
self.state = 23
|
| 2475 |
|
|
self.match(HPC16Parser.REG)
|
| 2476 |
|
|
pass
|
| 2477 |
|
|
|
| 2478 |
|
|
elif la_ == 3:
|
| 2479 |
|
|
localctx = HPC16Parser.Mov_reg_spContext(self, localctx)
|
| 2480 |
|
|
self.enterOuterAlt(localctx, 3)
|
| 2481 |
|
|
self.state = 24
|
| 2482 |
|
|
self.match(HPC16Parser.T__0)
|
| 2483 |
|
|
self.state = 25
|
| 2484 |
|
|
self.match(HPC16Parser.REG)
|
| 2485 |
|
|
self.state = 26
|
| 2486 |
|
|
self.match(HPC16Parser.T__1)
|
| 2487 |
|
|
self.state = 27
|
| 2488 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 2489 |
|
|
pass
|
| 2490 |
|
|
|
| 2491 |
|
|
elif la_ == 4:
|
| 2492 |
|
|
localctx = HPC16Parser.Ld_reg_regContext(self, localctx)
|
| 2493 |
|
|
self.enterOuterAlt(localctx, 4)
|
| 2494 |
|
|
self.state = 28
|
| 2495 |
|
|
self.match(HPC16Parser.T__2)
|
| 2496 |
|
|
self.state = 29
|
| 2497 |
|
|
self.match(HPC16Parser.REG)
|
| 2498 |
|
|
self.state = 30
|
| 2499 |
|
|
self.match(HPC16Parser.T__1)
|
| 2500 |
|
|
self.state = 31
|
| 2501 |
|
|
self.match(HPC16Parser.T__3)
|
| 2502 |
|
|
self.state = 32
|
| 2503 |
|
|
self.match(HPC16Parser.REG)
|
| 2504 |
|
|
self.state = 33
|
| 2505 |
|
|
self.match(HPC16Parser.T__4)
|
| 2506 |
|
|
pass
|
| 2507 |
|
|
|
| 2508 |
|
|
elif la_ == 5:
|
| 2509 |
|
|
localctx = HPC16Parser.Ld_reg_reg_imm16Context(self, localctx)
|
| 2510 |
|
|
self.enterOuterAlt(localctx, 5)
|
| 2511 |
|
|
self.state = 34
|
| 2512 |
|
|
self.match(HPC16Parser.T__2)
|
| 2513 |
|
|
self.state = 35
|
| 2514 |
|
|
self.match(HPC16Parser.REG)
|
| 2515 |
|
|
self.state = 36
|
| 2516 |
|
|
self.match(HPC16Parser.T__1)
|
| 2517 |
|
|
self.state = 37
|
| 2518 |
|
|
self.match(HPC16Parser.T__3)
|
| 2519 |
|
|
self.state = 38
|
| 2520 |
|
|
self.match(HPC16Parser.REG)
|
| 2521 |
|
|
self.state = 39
|
| 2522 |
|
|
self.match(HPC16Parser.T__5)
|
| 2523 |
|
|
self.state = 40
|
| 2524 |
|
|
self.match(HPC16Parser.IMM)
|
| 2525 |
|
|
self.state = 41
|
| 2526 |
|
|
self.match(HPC16Parser.T__4)
|
| 2527 |
|
|
pass
|
| 2528 |
|
|
|
| 2529 |
|
|
elif la_ == 6:
|
| 2530 |
|
|
localctx = HPC16Parser.Ld_reg_spContext(self, localctx)
|
| 2531 |
|
|
self.enterOuterAlt(localctx, 6)
|
| 2532 |
|
|
self.state = 42
|
| 2533 |
|
|
self.match(HPC16Parser.T__2)
|
| 2534 |
|
|
self.state = 43
|
| 2535 |
|
|
self.match(HPC16Parser.REG)
|
| 2536 |
|
|
self.state = 44
|
| 2537 |
|
|
self.match(HPC16Parser.T__1)
|
| 2538 |
|
|
self.state = 45
|
| 2539 |
|
|
self.match(HPC16Parser.T__3)
|
| 2540 |
|
|
self.state = 46
|
| 2541 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 2542 |
|
|
self.state = 47
|
| 2543 |
|
|
self.match(HPC16Parser.T__4)
|
| 2544 |
|
|
pass
|
| 2545 |
|
|
|
| 2546 |
|
|
elif la_ == 7:
|
| 2547 |
|
|
localctx = HPC16Parser.Ld_reg_sp_imm16Context(self, localctx)
|
| 2548 |
|
|
self.enterOuterAlt(localctx, 7)
|
| 2549 |
|
|
self.state = 48
|
| 2550 |
|
|
self.match(HPC16Parser.T__2)
|
| 2551 |
|
|
self.state = 49
|
| 2552 |
|
|
self.match(HPC16Parser.REG)
|
| 2553 |
|
|
self.state = 50
|
| 2554 |
|
|
self.match(HPC16Parser.T__1)
|
| 2555 |
|
|
self.state = 51
|
| 2556 |
|
|
self.match(HPC16Parser.T__3)
|
| 2557 |
|
|
self.state = 52
|
| 2558 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 2559 |
|
|
self.state = 53
|
| 2560 |
|
|
self.match(HPC16Parser.T__5)
|
| 2561 |
|
|
self.state = 54
|
| 2562 |
|
|
self.match(HPC16Parser.IMM)
|
| 2563 |
|
|
self.state = 55
|
| 2564 |
|
|
self.match(HPC16Parser.T__4)
|
| 2565 |
|
|
pass
|
| 2566 |
|
|
|
| 2567 |
|
|
elif la_ == 8:
|
| 2568 |
|
|
localctx = HPC16Parser.St_reg_regContext(self, localctx)
|
| 2569 |
|
|
self.enterOuterAlt(localctx, 8)
|
| 2570 |
|
|
self.state = 56
|
| 2571 |
|
|
self.match(HPC16Parser.T__6)
|
| 2572 |
|
|
self.state = 57
|
| 2573 |
|
|
self.match(HPC16Parser.REG)
|
| 2574 |
|
|
self.state = 58
|
| 2575 |
|
|
self.match(HPC16Parser.T__1)
|
| 2576 |
|
|
self.state = 59
|
| 2577 |
|
|
self.match(HPC16Parser.T__3)
|
| 2578 |
|
|
self.state = 60
|
| 2579 |
|
|
self.match(HPC16Parser.REG)
|
| 2580 |
|
|
self.state = 61
|
| 2581 |
|
|
self.match(HPC16Parser.T__4)
|
| 2582 |
|
|
pass
|
| 2583 |
|
|
|
| 2584 |
|
|
elif la_ == 9:
|
| 2585 |
|
|
localctx = HPC16Parser.St_reg_reg_imm16Context(self, localctx)
|
| 2586 |
|
|
self.enterOuterAlt(localctx, 9)
|
| 2587 |
|
|
self.state = 62
|
| 2588 |
|
|
self.match(HPC16Parser.T__6)
|
| 2589 |
|
|
self.state = 63
|
| 2590 |
|
|
self.match(HPC16Parser.REG)
|
| 2591 |
|
|
self.state = 64
|
| 2592 |
|
|
self.match(HPC16Parser.T__1)
|
| 2593 |
|
|
self.state = 65
|
| 2594 |
|
|
self.match(HPC16Parser.T__3)
|
| 2595 |
|
|
self.state = 66
|
| 2596 |
|
|
self.match(HPC16Parser.REG)
|
| 2597 |
|
|
self.state = 67
|
| 2598 |
|
|
self.match(HPC16Parser.T__5)
|
| 2599 |
|
|
self.state = 68
|
| 2600 |
|
|
self.match(HPC16Parser.IMM)
|
| 2601 |
|
|
self.state = 69
|
| 2602 |
|
|
self.match(HPC16Parser.T__4)
|
| 2603 |
|
|
pass
|
| 2604 |
|
|
|
| 2605 |
|
|
elif la_ == 10:
|
| 2606 |
|
|
localctx = HPC16Parser.St_reg_spContext(self, localctx)
|
| 2607 |
|
|
self.enterOuterAlt(localctx, 10)
|
| 2608 |
|
|
self.state = 70
|
| 2609 |
|
|
self.match(HPC16Parser.T__6)
|
| 2610 |
|
|
self.state = 71
|
| 2611 |
|
|
self.match(HPC16Parser.REG)
|
| 2612 |
|
|
self.state = 72
|
| 2613 |
|
|
self.match(HPC16Parser.T__1)
|
| 2614 |
|
|
self.state = 73
|
| 2615 |
|
|
self.match(HPC16Parser.T__3)
|
| 2616 |
|
|
self.state = 74
|
| 2617 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 2618 |
|
|
self.state = 75
|
| 2619 |
|
|
self.match(HPC16Parser.T__4)
|
| 2620 |
|
|
pass
|
| 2621 |
|
|
|
| 2622 |
|
|
elif la_ == 11:
|
| 2623 |
|
|
localctx = HPC16Parser.St_reg_sp_imm16Context(self, localctx)
|
| 2624 |
|
|
self.enterOuterAlt(localctx, 11)
|
| 2625 |
|
|
self.state = 76
|
| 2626 |
|
|
self.match(HPC16Parser.T__6)
|
| 2627 |
|
|
self.state = 77
|
| 2628 |
|
|
self.match(HPC16Parser.REG)
|
| 2629 |
|
|
self.state = 78
|
| 2630 |
|
|
self.match(HPC16Parser.T__1)
|
| 2631 |
|
|
self.state = 79
|
| 2632 |
|
|
self.match(HPC16Parser.T__3)
|
| 2633 |
|
|
self.state = 80
|
| 2634 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 2635 |
|
|
self.state = 81
|
| 2636 |
|
|
self.match(HPC16Parser.T__5)
|
| 2637 |
|
|
self.state = 82
|
| 2638 |
|
|
self.match(HPC16Parser.IMM)
|
| 2639 |
|
|
self.state = 83
|
| 2640 |
|
|
self.match(HPC16Parser.T__4)
|
| 2641 |
|
|
pass
|
| 2642 |
|
|
|
| 2643 |
|
|
elif la_ == 12:
|
| 2644 |
|
|
localctx = HPC16Parser.Lbzx_reg_regContext(self, localctx)
|
| 2645 |
|
|
self.enterOuterAlt(localctx, 12)
|
| 2646 |
|
|
self.state = 84
|
| 2647 |
|
|
self.match(HPC16Parser.T__7)
|
| 2648 |
|
|
self.state = 85
|
| 2649 |
|
|
self.match(HPC16Parser.REG)
|
| 2650 |
|
|
self.state = 86
|
| 2651 |
|
|
self.match(HPC16Parser.T__1)
|
| 2652 |
|
|
self.state = 87
|
| 2653 |
|
|
self.match(HPC16Parser.T__3)
|
| 2654 |
|
|
self.state = 88
|
| 2655 |
|
|
self.match(HPC16Parser.REG)
|
| 2656 |
|
|
self.state = 89
|
| 2657 |
|
|
self.match(HPC16Parser.T__4)
|
| 2658 |
|
|
pass
|
| 2659 |
|
|
|
| 2660 |
|
|
elif la_ == 13:
|
| 2661 |
|
|
localctx = HPC16Parser.Lbzx_reg_reg_imm16Context(self, localctx)
|
| 2662 |
|
|
self.enterOuterAlt(localctx, 13)
|
| 2663 |
|
|
self.state = 90
|
| 2664 |
|
|
self.match(HPC16Parser.T__7)
|
| 2665 |
|
|
self.state = 91
|
| 2666 |
|
|
self.match(HPC16Parser.REG)
|
| 2667 |
|
|
self.state = 92
|
| 2668 |
|
|
self.match(HPC16Parser.T__1)
|
| 2669 |
|
|
self.state = 93
|
| 2670 |
|
|
self.match(HPC16Parser.T__3)
|
| 2671 |
|
|
self.state = 94
|
| 2672 |
|
|
self.match(HPC16Parser.REG)
|
| 2673 |
|
|
self.state = 95
|
| 2674 |
|
|
self.match(HPC16Parser.T__5)
|
| 2675 |
|
|
self.state = 96
|
| 2676 |
|
|
self.match(HPC16Parser.IMM)
|
| 2677 |
|
|
self.state = 97
|
| 2678 |
|
|
self.match(HPC16Parser.T__4)
|
| 2679 |
|
|
pass
|
| 2680 |
|
|
|
| 2681 |
|
|
elif la_ == 14:
|
| 2682 |
|
|
localctx = HPC16Parser.Lbsx_reg_regContext(self, localctx)
|
| 2683 |
|
|
self.enterOuterAlt(localctx, 14)
|
| 2684 |
|
|
self.state = 98
|
| 2685 |
|
|
self.match(HPC16Parser.T__8)
|
| 2686 |
|
|
self.state = 99
|
| 2687 |
|
|
self.match(HPC16Parser.REG)
|
| 2688 |
|
|
self.state = 100
|
| 2689 |
|
|
self.match(HPC16Parser.T__1)
|
| 2690 |
|
|
self.state = 101
|
| 2691 |
|
|
self.match(HPC16Parser.T__3)
|
| 2692 |
|
|
self.state = 102
|
| 2693 |
|
|
self.match(HPC16Parser.REG)
|
| 2694 |
|
|
self.state = 103
|
| 2695 |
|
|
self.match(HPC16Parser.T__4)
|
| 2696 |
|
|
pass
|
| 2697 |
|
|
|
| 2698 |
|
|
elif la_ == 15:
|
| 2699 |
|
|
localctx = HPC16Parser.Lbsx_reg_reg_imm16Context(self, localctx)
|
| 2700 |
|
|
self.enterOuterAlt(localctx, 15)
|
| 2701 |
|
|
self.state = 104
|
| 2702 |
|
|
self.match(HPC16Parser.T__8)
|
| 2703 |
|
|
self.state = 105
|
| 2704 |
|
|
self.match(HPC16Parser.REG)
|
| 2705 |
|
|
self.state = 106
|
| 2706 |
|
|
self.match(HPC16Parser.T__1)
|
| 2707 |
|
|
self.state = 107
|
| 2708 |
|
|
self.match(HPC16Parser.T__3)
|
| 2709 |
|
|
self.state = 108
|
| 2710 |
|
|
self.match(HPC16Parser.REG)
|
| 2711 |
|
|
self.state = 109
|
| 2712 |
|
|
self.match(HPC16Parser.T__5)
|
| 2713 |
|
|
self.state = 110
|
| 2714 |
|
|
self.match(HPC16Parser.IMM)
|
| 2715 |
|
|
self.state = 111
|
| 2716 |
|
|
self.match(HPC16Parser.T__4)
|
| 2717 |
|
|
pass
|
| 2718 |
|
|
|
| 2719 |
|
|
elif la_ == 16:
|
| 2720 |
|
|
localctx = HPC16Parser.Sb_reg_regContext(self, localctx)
|
| 2721 |
|
|
self.enterOuterAlt(localctx, 16)
|
| 2722 |
|
|
self.state = 112
|
| 2723 |
|
|
self.match(HPC16Parser.T__9)
|
| 2724 |
|
|
self.state = 113
|
| 2725 |
|
|
self.match(HPC16Parser.REG)
|
| 2726 |
|
|
self.state = 114
|
| 2727 |
|
|
self.match(HPC16Parser.T__1)
|
| 2728 |
|
|
self.state = 115
|
| 2729 |
|
|
self.match(HPC16Parser.T__3)
|
| 2730 |
|
|
self.state = 116
|
| 2731 |
|
|
self.match(HPC16Parser.REG)
|
| 2732 |
|
|
self.state = 117
|
| 2733 |
|
|
self.match(HPC16Parser.T__4)
|
| 2734 |
|
|
pass
|
| 2735 |
|
|
|
| 2736 |
|
|
elif la_ == 17:
|
| 2737 |
|
|
localctx = HPC16Parser.Sb_reg_reg_imm16Context(self, localctx)
|
| 2738 |
|
|
self.enterOuterAlt(localctx, 17)
|
| 2739 |
|
|
self.state = 118
|
| 2740 |
|
|
self.match(HPC16Parser.T__9)
|
| 2741 |
|
|
self.state = 119
|
| 2742 |
|
|
self.match(HPC16Parser.REG)
|
| 2743 |
|
|
self.state = 120
|
| 2744 |
|
|
self.match(HPC16Parser.T__1)
|
| 2745 |
|
|
self.state = 121
|
| 2746 |
|
|
self.match(HPC16Parser.T__3)
|
| 2747 |
|
|
self.state = 122
|
| 2748 |
|
|
self.match(HPC16Parser.REG)
|
| 2749 |
|
|
self.state = 123
|
| 2750 |
|
|
self.match(HPC16Parser.T__5)
|
| 2751 |
|
|
self.state = 124
|
| 2752 |
|
|
self.match(HPC16Parser.IMM)
|
| 2753 |
|
|
self.state = 125
|
| 2754 |
|
|
self.match(HPC16Parser.T__4)
|
| 2755 |
|
|
pass
|
| 2756 |
|
|
|
| 2757 |
|
|
elif la_ == 18:
|
| 2758 |
|
|
localctx = HPC16Parser.Li_reg_imm16Context(self, localctx)
|
| 2759 |
|
|
self.enterOuterAlt(localctx, 18)
|
| 2760 |
|
|
self.state = 126
|
| 2761 |
|
|
self.match(HPC16Parser.T__10)
|
| 2762 |
|
|
self.state = 127
|
| 2763 |
|
|
self.match(HPC16Parser.REG)
|
| 2764 |
|
|
self.state = 128
|
| 2765 |
|
|
self.match(HPC16Parser.T__1)
|
| 2766 |
|
|
self.state = 129
|
| 2767 |
|
|
self.match(HPC16Parser.IMM)
|
| 2768 |
|
|
pass
|
| 2769 |
|
|
|
| 2770 |
|
|
elif la_ == 19:
|
| 2771 |
|
|
localctx = HPC16Parser.Li_sp_imm16Context(self, localctx)
|
| 2772 |
|
|
self.enterOuterAlt(localctx, 19)
|
| 2773 |
|
|
self.state = 130
|
| 2774 |
|
|
self.match(HPC16Parser.T__10)
|
| 2775 |
|
|
self.state = 131
|
| 2776 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 2777 |
|
|
self.state = 132
|
| 2778 |
|
|
self.match(HPC16Parser.T__1)
|
| 2779 |
|
|
self.state = 133
|
| 2780 |
|
|
self.match(HPC16Parser.IMM)
|
| 2781 |
|
|
pass
|
| 2782 |
|
|
|
| 2783 |
|
|
elif la_ == 20:
|
| 2784 |
|
|
localctx = HPC16Parser.Inc_regContext(self, localctx)
|
| 2785 |
|
|
self.enterOuterAlt(localctx, 20)
|
| 2786 |
|
|
self.state = 134
|
| 2787 |
|
|
self.match(HPC16Parser.T__11)
|
| 2788 |
|
|
self.state = 135
|
| 2789 |
|
|
self.match(HPC16Parser.REG)
|
| 2790 |
|
|
pass
|
| 2791 |
|
|
|
| 2792 |
|
|
elif la_ == 21:
|
| 2793 |
|
|
localctx = HPC16Parser.Dec_regContext(self, localctx)
|
| 2794 |
|
|
self.enterOuterAlt(localctx, 21)
|
| 2795 |
|
|
self.state = 136
|
| 2796 |
|
|
self.match(HPC16Parser.T__12)
|
| 2797 |
|
|
self.state = 137
|
| 2798 |
|
|
self.match(HPC16Parser.REG)
|
| 2799 |
|
|
pass
|
| 2800 |
|
|
|
| 2801 |
|
|
elif la_ == 22:
|
| 2802 |
|
|
localctx = HPC16Parser.Sub_reg_regContext(self, localctx)
|
| 2803 |
|
|
self.enterOuterAlt(localctx, 22)
|
| 2804 |
|
|
self.state = 138
|
| 2805 |
|
|
self.match(HPC16Parser.T__13)
|
| 2806 |
|
|
self.state = 139
|
| 2807 |
|
|
self.match(HPC16Parser.REG)
|
| 2808 |
|
|
self.state = 140
|
| 2809 |
|
|
self.match(HPC16Parser.T__1)
|
| 2810 |
|
|
self.state = 141
|
| 2811 |
|
|
self.match(HPC16Parser.REG)
|
| 2812 |
|
|
pass
|
| 2813 |
|
|
|
| 2814 |
|
|
elif la_ == 23:
|
| 2815 |
|
|
localctx = HPC16Parser.And_reg_regContext(self, localctx)
|
| 2816 |
|
|
self.enterOuterAlt(localctx, 23)
|
| 2817 |
|
|
self.state = 142
|
| 2818 |
|
|
self.match(HPC16Parser.T__14)
|
| 2819 |
|
|
self.state = 143
|
| 2820 |
|
|
self.match(HPC16Parser.REG)
|
| 2821 |
|
|
self.state = 144
|
| 2822 |
|
|
self.match(HPC16Parser.T__1)
|
| 2823 |
|
|
self.state = 145
|
| 2824 |
|
|
self.match(HPC16Parser.REG)
|
| 2825 |
|
|
pass
|
| 2826 |
|
|
|
| 2827 |
|
|
elif la_ == 24:
|
| 2828 |
|
|
localctx = HPC16Parser.Add_reg_regContext(self, localctx)
|
| 2829 |
|
|
self.enterOuterAlt(localctx, 24)
|
| 2830 |
|
|
self.state = 146
|
| 2831 |
|
|
self.match(HPC16Parser.T__15)
|
| 2832 |
|
|
self.state = 147
|
| 2833 |
|
|
self.match(HPC16Parser.REG)
|
| 2834 |
|
|
self.state = 148
|
| 2835 |
|
|
self.match(HPC16Parser.T__1)
|
| 2836 |
|
|
self.state = 149
|
| 2837 |
|
|
self.match(HPC16Parser.REG)
|
| 2838 |
|
|
pass
|
| 2839 |
|
|
|
| 2840 |
|
|
elif la_ == 25:
|
| 2841 |
|
|
localctx = HPC16Parser.Adc_reg_regContext(self, localctx)
|
| 2842 |
|
|
self.enterOuterAlt(localctx, 25)
|
| 2843 |
|
|
self.state = 150
|
| 2844 |
|
|
self.match(HPC16Parser.T__16)
|
| 2845 |
|
|
self.state = 151
|
| 2846 |
|
|
self.match(HPC16Parser.REG)
|
| 2847 |
|
|
self.state = 152
|
| 2848 |
|
|
self.match(HPC16Parser.T__1)
|
| 2849 |
|
|
self.state = 153
|
| 2850 |
|
|
self.match(HPC16Parser.REG)
|
| 2851 |
|
|
pass
|
| 2852 |
|
|
|
| 2853 |
|
|
elif la_ == 26:
|
| 2854 |
|
|
localctx = HPC16Parser.Sbb_reg_regContext(self, localctx)
|
| 2855 |
|
|
self.enterOuterAlt(localctx, 26)
|
| 2856 |
|
|
self.state = 154
|
| 2857 |
|
|
self.match(HPC16Parser.T__17)
|
| 2858 |
|
|
self.state = 155
|
| 2859 |
|
|
self.match(HPC16Parser.REG)
|
| 2860 |
|
|
self.state = 156
|
| 2861 |
|
|
self.match(HPC16Parser.T__1)
|
| 2862 |
|
|
self.state = 157
|
| 2863 |
|
|
self.match(HPC16Parser.REG)
|
| 2864 |
|
|
pass
|
| 2865 |
|
|
|
| 2866 |
|
|
elif la_ == 27:
|
| 2867 |
|
|
localctx = HPC16Parser.Or_reg_regContext(self, localctx)
|
| 2868 |
|
|
self.enterOuterAlt(localctx, 27)
|
| 2869 |
|
|
self.state = 158
|
| 2870 |
|
|
self.match(HPC16Parser.T__18)
|
| 2871 |
|
|
self.state = 159
|
| 2872 |
|
|
self.match(HPC16Parser.REG)
|
| 2873 |
|
|
self.state = 160
|
| 2874 |
|
|
self.match(HPC16Parser.T__1)
|
| 2875 |
|
|
self.state = 161
|
| 2876 |
|
|
self.match(HPC16Parser.REG)
|
| 2877 |
|
|
pass
|
| 2878 |
|
|
|
| 2879 |
|
|
elif la_ == 28:
|
| 2880 |
|
|
localctx = HPC16Parser.Xor_reg_regContext(self, localctx)
|
| 2881 |
|
|
self.enterOuterAlt(localctx, 28)
|
| 2882 |
|
|
self.state = 162
|
| 2883 |
|
|
self.match(HPC16Parser.T__19)
|
| 2884 |
|
|
self.state = 163
|
| 2885 |
|
|
self.match(HPC16Parser.REG)
|
| 2886 |
|
|
self.state = 164
|
| 2887 |
|
|
self.match(HPC16Parser.T__1)
|
| 2888 |
|
|
self.state = 165
|
| 2889 |
|
|
self.match(HPC16Parser.REG)
|
| 2890 |
|
|
pass
|
| 2891 |
|
|
|
| 2892 |
|
|
elif la_ == 29:
|
| 2893 |
|
|
localctx = HPC16Parser.Not_regContext(self, localctx)
|
| 2894 |
|
|
self.enterOuterAlt(localctx, 29)
|
| 2895 |
|
|
self.state = 166
|
| 2896 |
|
|
self.match(HPC16Parser.T__20)
|
| 2897 |
|
|
self.state = 167
|
| 2898 |
|
|
self.match(HPC16Parser.REG)
|
| 2899 |
|
|
pass
|
| 2900 |
|
|
|
| 2901 |
|
|
elif la_ == 30:
|
| 2902 |
|
|
localctx = HPC16Parser.Sub_reg_imm16Context(self, localctx)
|
| 2903 |
|
|
self.enterOuterAlt(localctx, 30)
|
| 2904 |
|
|
self.state = 168
|
| 2905 |
|
|
self.match(HPC16Parser.T__13)
|
| 2906 |
|
|
self.state = 169
|
| 2907 |
|
|
self.match(HPC16Parser.REG)
|
| 2908 |
|
|
self.state = 170
|
| 2909 |
|
|
self.match(HPC16Parser.T__1)
|
| 2910 |
|
|
self.state = 171
|
| 2911 |
|
|
self.match(HPC16Parser.IMM)
|
| 2912 |
|
|
pass
|
| 2913 |
|
|
|
| 2914 |
|
|
elif la_ == 31:
|
| 2915 |
|
|
localctx = HPC16Parser.And_reg_imm16Context(self, localctx)
|
| 2916 |
|
|
self.enterOuterAlt(localctx, 31)
|
| 2917 |
|
|
self.state = 172
|
| 2918 |
|
|
self.match(HPC16Parser.T__14)
|
| 2919 |
|
|
self.state = 173
|
| 2920 |
|
|
self.match(HPC16Parser.REG)
|
| 2921 |
|
|
self.state = 174
|
| 2922 |
|
|
self.match(HPC16Parser.T__1)
|
| 2923 |
|
|
self.state = 175
|
| 2924 |
|
|
self.match(HPC16Parser.IMM)
|
| 2925 |
|
|
pass
|
| 2926 |
|
|
|
| 2927 |
|
|
elif la_ == 32:
|
| 2928 |
|
|
localctx = HPC16Parser.Add_reg_imm16Context(self, localctx)
|
| 2929 |
|
|
self.enterOuterAlt(localctx, 32)
|
| 2930 |
|
|
self.state = 176
|
| 2931 |
|
|
self.match(HPC16Parser.T__15)
|
| 2932 |
|
|
self.state = 177
|
| 2933 |
|
|
self.match(HPC16Parser.REG)
|
| 2934 |
|
|
self.state = 178
|
| 2935 |
|
|
self.match(HPC16Parser.T__1)
|
| 2936 |
|
|
self.state = 179
|
| 2937 |
|
|
self.match(HPC16Parser.IMM)
|
| 2938 |
|
|
pass
|
| 2939 |
|
|
|
| 2940 |
|
|
elif la_ == 33:
|
| 2941 |
|
|
localctx = HPC16Parser.Adc_reg_imm16Context(self, localctx)
|
| 2942 |
|
|
self.enterOuterAlt(localctx, 33)
|
| 2943 |
|
|
self.state = 180
|
| 2944 |
|
|
self.match(HPC16Parser.T__16)
|
| 2945 |
|
|
self.state = 181
|
| 2946 |
|
|
self.match(HPC16Parser.REG)
|
| 2947 |
|
|
self.state = 182
|
| 2948 |
|
|
self.match(HPC16Parser.T__1)
|
| 2949 |
|
|
self.state = 183
|
| 2950 |
|
|
self.match(HPC16Parser.IMM)
|
| 2951 |
|
|
pass
|
| 2952 |
|
|
|
| 2953 |
|
|
elif la_ == 34:
|
| 2954 |
|
|
localctx = HPC16Parser.Sbb_reg_imm16Context(self, localctx)
|
| 2955 |
|
|
self.enterOuterAlt(localctx, 34)
|
| 2956 |
|
|
self.state = 184
|
| 2957 |
|
|
self.match(HPC16Parser.T__17)
|
| 2958 |
|
|
self.state = 185
|
| 2959 |
|
|
self.match(HPC16Parser.REG)
|
| 2960 |
|
|
self.state = 186
|
| 2961 |
|
|
self.match(HPC16Parser.T__1)
|
| 2962 |
|
|
self.state = 187
|
| 2963 |
|
|
self.match(HPC16Parser.IMM)
|
| 2964 |
|
|
pass
|
| 2965 |
|
|
|
| 2966 |
|
|
elif la_ == 35:
|
| 2967 |
|
|
localctx = HPC16Parser.Or_reg_imm16Context(self, localctx)
|
| 2968 |
|
|
self.enterOuterAlt(localctx, 35)
|
| 2969 |
|
|
self.state = 188
|
| 2970 |
|
|
self.match(HPC16Parser.T__18)
|
| 2971 |
|
|
self.state = 189
|
| 2972 |
|
|
self.match(HPC16Parser.REG)
|
| 2973 |
|
|
self.state = 190
|
| 2974 |
|
|
self.match(HPC16Parser.T__1)
|
| 2975 |
|
|
self.state = 191
|
| 2976 |
|
|
self.match(HPC16Parser.IMM)
|
| 2977 |
|
|
pass
|
| 2978 |
|
|
|
| 2979 |
|
|
elif la_ == 36:
|
| 2980 |
|
|
localctx = HPC16Parser.Xor_reg_imm16Context(self, localctx)
|
| 2981 |
|
|
self.enterOuterAlt(localctx, 36)
|
| 2982 |
|
|
self.state = 192
|
| 2983 |
|
|
self.match(HPC16Parser.T__19)
|
| 2984 |
|
|
self.state = 193
|
| 2985 |
|
|
self.match(HPC16Parser.REG)
|
| 2986 |
|
|
self.state = 194
|
| 2987 |
|
|
self.match(HPC16Parser.T__1)
|
| 2988 |
|
|
self.state = 195
|
| 2989 |
|
|
self.match(HPC16Parser.IMM)
|
| 2990 |
|
|
pass
|
| 2991 |
|
|
|
| 2992 |
|
|
elif la_ == 37:
|
| 2993 |
|
|
localctx = HPC16Parser.Add_sp_imm16Context(self, localctx)
|
| 2994 |
|
|
self.enterOuterAlt(localctx, 37)
|
| 2995 |
|
|
self.state = 196
|
| 2996 |
|
|
self.match(HPC16Parser.T__15)
|
| 2997 |
|
|
self.state = 197
|
| 2998 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 2999 |
|
|
self.state = 198
|
| 3000 |
|
|
self.match(HPC16Parser.T__1)
|
| 3001 |
|
|
self.state = 199
|
| 3002 |
|
|
self.match(HPC16Parser.IMM)
|
| 3003 |
|
|
pass
|
| 3004 |
|
|
|
| 3005 |
|
|
elif la_ == 38:
|
| 3006 |
|
|
localctx = HPC16Parser.Sub_sp_imm16Context(self, localctx)
|
| 3007 |
|
|
self.enterOuterAlt(localctx, 38)
|
| 3008 |
|
|
self.state = 200
|
| 3009 |
|
|
self.match(HPC16Parser.T__13)
|
| 3010 |
|
|
self.state = 201
|
| 3011 |
|
|
self.match(HPC16Parser.STK_PTR)
|
| 3012 |
|
|
self.state = 202
|
| 3013 |
|
|
self.match(HPC16Parser.T__1)
|
| 3014 |
|
|
self.state = 203
|
| 3015 |
|
|
self.match(HPC16Parser.IMM)
|
| 3016 |
|
|
pass
|
| 3017 |
|
|
|
| 3018 |
|
|
elif la_ == 39:
|
| 3019 |
|
|
localctx = HPC16Parser.Cmp_reg_regContext(self, localctx)
|
| 3020 |
|
|
self.enterOuterAlt(localctx, 39)
|
| 3021 |
|
|
self.state = 204
|
| 3022 |
|
|
self.match(HPC16Parser.T__21)
|
| 3023 |
|
|
self.state = 205
|
| 3024 |
|
|
self.match(HPC16Parser.REG)
|
| 3025 |
|
|
self.state = 206
|
| 3026 |
|
|
self.match(HPC16Parser.T__1)
|
| 3027 |
|
|
self.state = 207
|
| 3028 |
|
|
self.match(HPC16Parser.REG)
|
| 3029 |
|
|
pass
|
| 3030 |
|
|
|
| 3031 |
|
|
elif la_ == 40:
|
| 3032 |
|
|
localctx = HPC16Parser.Test_reg_regContext(self, localctx)
|
| 3033 |
|
|
self.enterOuterAlt(localctx, 40)
|
| 3034 |
|
|
self.state = 208
|
| 3035 |
|
|
self.match(HPC16Parser.T__22)
|
| 3036 |
|
|
self.state = 209
|
| 3037 |
|
|
self.match(HPC16Parser.REG)
|
| 3038 |
|
|
self.state = 210
|
| 3039 |
|
|
self.match(HPC16Parser.T__1)
|
| 3040 |
|
|
self.state = 211
|
| 3041 |
|
|
self.match(HPC16Parser.REG)
|
| 3042 |
|
|
pass
|
| 3043 |
|
|
|
| 3044 |
|
|
elif la_ == 41:
|
| 3045 |
|
|
localctx = HPC16Parser.Cmp_reg_imm16Context(self, localctx)
|
| 3046 |
|
|
self.enterOuterAlt(localctx, 41)
|
| 3047 |
|
|
self.state = 212
|
| 3048 |
|
|
self.match(HPC16Parser.T__21)
|
| 3049 |
|
|
self.state = 213
|
| 3050 |
|
|
self.match(HPC16Parser.REG)
|
| 3051 |
|
|
self.state = 214
|
| 3052 |
|
|
self.match(HPC16Parser.T__1)
|
| 3053 |
|
|
self.state = 215
|
| 3054 |
|
|
self.match(HPC16Parser.IMM)
|
| 3055 |
|
|
pass
|
| 3056 |
|
|
|
| 3057 |
|
|
elif la_ == 42:
|
| 3058 |
|
|
localctx = HPC16Parser.Test_reg_imm16Context(self, localctx)
|
| 3059 |
|
|
self.enterOuterAlt(localctx, 42)
|
| 3060 |
|
|
self.state = 216
|
| 3061 |
|
|
self.match(HPC16Parser.T__22)
|
| 3062 |
|
|
self.state = 217
|
| 3063 |
|
|
self.match(HPC16Parser.REG)
|
| 3064 |
|
|
self.state = 218
|
| 3065 |
|
|
self.match(HPC16Parser.T__1)
|
| 3066 |
|
|
self.state = 219
|
| 3067 |
|
|
self.match(HPC16Parser.IMM)
|
| 3068 |
|
|
pass
|
| 3069 |
|
|
|
| 3070 |
|
|
elif la_ == 43:
|
| 3071 |
|
|
localctx = HPC16Parser.Sll_reg_regContext(self, localctx)
|
| 3072 |
|
|
self.enterOuterAlt(localctx, 43)
|
| 3073 |
|
|
self.state = 220
|
| 3074 |
|
|
self.match(HPC16Parser.T__23)
|
| 3075 |
|
|
self.state = 221
|
| 3076 |
|
|
self.match(HPC16Parser.REG)
|
| 3077 |
|
|
self.state = 222
|
| 3078 |
|
|
self.match(HPC16Parser.T__1)
|
| 3079 |
|
|
self.state = 223
|
| 3080 |
|
|
self.match(HPC16Parser.REG)
|
| 3081 |
|
|
pass
|
| 3082 |
|
|
|
| 3083 |
|
|
elif la_ == 44:
|
| 3084 |
|
|
localctx = HPC16Parser.Slr_reg_regContext(self, localctx)
|
| 3085 |
|
|
self.enterOuterAlt(localctx, 44)
|
| 3086 |
|
|
self.state = 224
|
| 3087 |
|
|
self.match(HPC16Parser.T__24)
|
| 3088 |
|
|
self.state = 225
|
| 3089 |
|
|
self.match(HPC16Parser.REG)
|
| 3090 |
|
|
self.state = 226
|
| 3091 |
|
|
self.match(HPC16Parser.T__1)
|
| 3092 |
|
|
self.state = 227
|
| 3093 |
|
|
self.match(HPC16Parser.REG)
|
| 3094 |
|
|
pass
|
| 3095 |
|
|
|
| 3096 |
|
|
elif la_ == 45:
|
| 3097 |
|
|
localctx = HPC16Parser.Sal_reg_regContext(self, localctx)
|
| 3098 |
|
|
self.enterOuterAlt(localctx, 45)
|
| 3099 |
|
|
self.state = 228
|
| 3100 |
|
|
self.match(HPC16Parser.T__25)
|
| 3101 |
|
|
self.state = 229
|
| 3102 |
|
|
self.match(HPC16Parser.REG)
|
| 3103 |
|
|
self.state = 230
|
| 3104 |
|
|
self.match(HPC16Parser.T__1)
|
| 3105 |
|
|
self.state = 231
|
| 3106 |
|
|
self.match(HPC16Parser.REG)
|
| 3107 |
|
|
pass
|
| 3108 |
|
|
|
| 3109 |
|
|
elif la_ == 46:
|
| 3110 |
|
|
localctx = HPC16Parser.Sar_reg_regContext(self, localctx)
|
| 3111 |
|
|
self.enterOuterAlt(localctx, 46)
|
| 3112 |
|
|
self.state = 232
|
| 3113 |
|
|
self.match(HPC16Parser.T__26)
|
| 3114 |
|
|
self.state = 233
|
| 3115 |
|
|
self.match(HPC16Parser.REG)
|
| 3116 |
|
|
self.state = 234
|
| 3117 |
|
|
self.match(HPC16Parser.T__1)
|
| 3118 |
|
|
self.state = 235
|
| 3119 |
|
|
self.match(HPC16Parser.REG)
|
| 3120 |
|
|
pass
|
| 3121 |
|
|
|
| 3122 |
|
|
elif la_ == 47:
|
| 3123 |
|
|
localctx = HPC16Parser.Rol_reg_regContext(self, localctx)
|
| 3124 |
|
|
self.enterOuterAlt(localctx, 47)
|
| 3125 |
|
|
self.state = 236
|
| 3126 |
|
|
self.match(HPC16Parser.T__27)
|
| 3127 |
|
|
self.state = 237
|
| 3128 |
|
|
self.match(HPC16Parser.REG)
|
| 3129 |
|
|
self.state = 238
|
| 3130 |
|
|
self.match(HPC16Parser.T__1)
|
| 3131 |
|
|
self.state = 239
|
| 3132 |
|
|
self.match(HPC16Parser.REG)
|
| 3133 |
|
|
pass
|
| 3134 |
|
|
|
| 3135 |
|
|
elif la_ == 48:
|
| 3136 |
|
|
localctx = HPC16Parser.Ror_reg_regContext(self, localctx)
|
| 3137 |
|
|
self.enterOuterAlt(localctx, 48)
|
| 3138 |
|
|
self.state = 240
|
| 3139 |
|
|
self.match(HPC16Parser.T__28)
|
| 3140 |
|
|
self.state = 241
|
| 3141 |
|
|
self.match(HPC16Parser.REG)
|
| 3142 |
|
|
self.state = 242
|
| 3143 |
|
|
self.match(HPC16Parser.T__1)
|
| 3144 |
|
|
self.state = 243
|
| 3145 |
|
|
self.match(HPC16Parser.REG)
|
| 3146 |
|
|
pass
|
| 3147 |
|
|
|
| 3148 |
|
|
elif la_ == 49:
|
| 3149 |
|
|
localctx = HPC16Parser.Rcl_reg_regContext(self, localctx)
|
| 3150 |
|
|
self.enterOuterAlt(localctx, 49)
|
| 3151 |
|
|
self.state = 244
|
| 3152 |
|
|
self.match(HPC16Parser.T__29)
|
| 3153 |
|
|
self.state = 245
|
| 3154 |
|
|
self.match(HPC16Parser.REG)
|
| 3155 |
|
|
self.state = 246
|
| 3156 |
|
|
self.match(HPC16Parser.T__1)
|
| 3157 |
|
|
self.state = 247
|
| 3158 |
|
|
self.match(HPC16Parser.REG)
|
| 3159 |
|
|
pass
|
| 3160 |
|
|
|
| 3161 |
|
|
elif la_ == 50:
|
| 3162 |
|
|
localctx = HPC16Parser.Rcr_reg_regContext(self, localctx)
|
| 3163 |
|
|
self.enterOuterAlt(localctx, 50)
|
| 3164 |
|
|
self.state = 248
|
| 3165 |
|
|
self.match(HPC16Parser.T__30)
|
| 3166 |
|
|
self.state = 249
|
| 3167 |
|
|
self.match(HPC16Parser.REG)
|
| 3168 |
|
|
self.state = 250
|
| 3169 |
|
|
self.match(HPC16Parser.T__1)
|
| 3170 |
|
|
self.state = 251
|
| 3171 |
|
|
self.match(HPC16Parser.REG)
|
| 3172 |
|
|
pass
|
| 3173 |
|
|
|
| 3174 |
|
|
elif la_ == 51:
|
| 3175 |
|
|
localctx = HPC16Parser.Sll_reg_imm4Context(self, localctx)
|
| 3176 |
|
|
self.enterOuterAlt(localctx, 51)
|
| 3177 |
|
|
self.state = 252
|
| 3178 |
|
|
self.match(HPC16Parser.T__23)
|
| 3179 |
|
|
self.state = 253
|
| 3180 |
|
|
self.match(HPC16Parser.REG)
|
| 3181 |
|
|
self.state = 254
|
| 3182 |
|
|
self.match(HPC16Parser.T__1)
|
| 3183 |
|
|
self.state = 255
|
| 3184 |
|
|
self.match(HPC16Parser.IMM)
|
| 3185 |
|
|
pass
|
| 3186 |
|
|
|
| 3187 |
|
|
elif la_ == 52:
|
| 3188 |
|
|
localctx = HPC16Parser.Slr_reg_imm4Context(self, localctx)
|
| 3189 |
|
|
self.enterOuterAlt(localctx, 52)
|
| 3190 |
|
|
self.state = 256
|
| 3191 |
|
|
self.match(HPC16Parser.T__24)
|
| 3192 |
|
|
self.state = 257
|
| 3193 |
|
|
self.match(HPC16Parser.REG)
|
| 3194 |
|
|
self.state = 258
|
| 3195 |
|
|
self.match(HPC16Parser.T__1)
|
| 3196 |
|
|
self.state = 259
|
| 3197 |
|
|
self.match(HPC16Parser.IMM)
|
| 3198 |
|
|
pass
|
| 3199 |
|
|
|
| 3200 |
|
|
elif la_ == 53:
|
| 3201 |
|
|
localctx = HPC16Parser.Sal_reg_imm4Context(self, localctx)
|
| 3202 |
|
|
self.enterOuterAlt(localctx, 53)
|
| 3203 |
|
|
self.state = 260
|
| 3204 |
|
|
self.match(HPC16Parser.T__25)
|
| 3205 |
|
|
self.state = 261
|
| 3206 |
|
|
self.match(HPC16Parser.REG)
|
| 3207 |
|
|
self.state = 262
|
| 3208 |
|
|
self.match(HPC16Parser.T__1)
|
| 3209 |
|
|
self.state = 263
|
| 3210 |
|
|
self.match(HPC16Parser.IMM)
|
| 3211 |
|
|
pass
|
| 3212 |
|
|
|
| 3213 |
|
|
elif la_ == 54:
|
| 3214 |
|
|
localctx = HPC16Parser.Sar_reg_imm4Context(self, localctx)
|
| 3215 |
|
|
self.enterOuterAlt(localctx, 54)
|
| 3216 |
|
|
self.state = 264
|
| 3217 |
|
|
self.match(HPC16Parser.T__26)
|
| 3218 |
|
|
self.state = 265
|
| 3219 |
|
|
self.match(HPC16Parser.REG)
|
| 3220 |
|
|
self.state = 266
|
| 3221 |
|
|
self.match(HPC16Parser.T__1)
|
| 3222 |
|
|
self.state = 267
|
| 3223 |
|
|
self.match(HPC16Parser.IMM)
|
| 3224 |
|
|
pass
|
| 3225 |
|
|
|
| 3226 |
|
|
elif la_ == 55:
|
| 3227 |
|
|
localctx = HPC16Parser.Rol_reg_imm4Context(self, localctx)
|
| 3228 |
|
|
self.enterOuterAlt(localctx, 55)
|
| 3229 |
|
|
self.state = 268
|
| 3230 |
|
|
self.match(HPC16Parser.T__27)
|
| 3231 |
|
|
self.state = 269
|
| 3232 |
|
|
self.match(HPC16Parser.REG)
|
| 3233 |
|
|
self.state = 270
|
| 3234 |
|
|
self.match(HPC16Parser.T__1)
|
| 3235 |
|
|
self.state = 271
|
| 3236 |
|
|
self.match(HPC16Parser.IMM)
|
| 3237 |
|
|
pass
|
| 3238 |
|
|
|
| 3239 |
|
|
elif la_ == 56:
|
| 3240 |
|
|
localctx = HPC16Parser.Ror_reg_imm4Context(self, localctx)
|
| 3241 |
|
|
self.enterOuterAlt(localctx, 56)
|
| 3242 |
|
|
self.state = 272
|
| 3243 |
|
|
self.match(HPC16Parser.T__28)
|
| 3244 |
|
|
self.state = 273
|
| 3245 |
|
|
self.match(HPC16Parser.REG)
|
| 3246 |
|
|
self.state = 274
|
| 3247 |
|
|
self.match(HPC16Parser.T__1)
|
| 3248 |
|
|
self.state = 275
|
| 3249 |
|
|
self.match(HPC16Parser.IMM)
|
| 3250 |
|
|
pass
|
| 3251 |
|
|
|
| 3252 |
|
|
elif la_ == 57:
|
| 3253 |
|
|
localctx = HPC16Parser.Rcl_reg_imm4Context(self, localctx)
|
| 3254 |
|
|
self.enterOuterAlt(localctx, 57)
|
| 3255 |
|
|
self.state = 276
|
| 3256 |
|
|
self.match(HPC16Parser.T__29)
|
| 3257 |
|
|
self.state = 277
|
| 3258 |
|
|
self.match(HPC16Parser.REG)
|
| 3259 |
|
|
self.state = 278
|
| 3260 |
|
|
self.match(HPC16Parser.T__1)
|
| 3261 |
|
|
self.state = 279
|
| 3262 |
|
|
self.match(HPC16Parser.IMM)
|
| 3263 |
|
|
pass
|
| 3264 |
|
|
|
| 3265 |
|
|
elif la_ == 58:
|
| 3266 |
|
|
localctx = HPC16Parser.Rcr_reg_imm4Context(self, localctx)
|
| 3267 |
|
|
self.enterOuterAlt(localctx, 58)
|
| 3268 |
|
|
self.state = 280
|
| 3269 |
|
|
self.match(HPC16Parser.T__30)
|
| 3270 |
|
|
self.state = 281
|
| 3271 |
|
|
self.match(HPC16Parser.REG)
|
| 3272 |
|
|
self.state = 282
|
| 3273 |
|
|
self.match(HPC16Parser.T__1)
|
| 3274 |
|
|
self.state = 283
|
| 3275 |
|
|
self.match(HPC16Parser.IMM)
|
| 3276 |
|
|
pass
|
| 3277 |
|
|
|
| 3278 |
|
|
elif la_ == 59:
|
| 3279 |
|
|
localctx = HPC16Parser.Push_regContext(self, localctx)
|
| 3280 |
|
|
self.enterOuterAlt(localctx, 59)
|
| 3281 |
|
|
self.state = 284
|
| 3282 |
|
|
self.match(HPC16Parser.T__31)
|
| 3283 |
|
|
self.state = 285
|
| 3284 |
|
|
self.match(HPC16Parser.REG)
|
| 3285 |
|
|
pass
|
| 3286 |
|
|
|
| 3287 |
|
|
elif la_ == 60:
|
| 3288 |
|
|
localctx = HPC16Parser.PushfContext(self, localctx)
|
| 3289 |
|
|
self.enterOuterAlt(localctx, 60)
|
| 3290 |
|
|
self.state = 286
|
| 3291 |
|
|
self.match(HPC16Parser.T__32)
|
| 3292 |
|
|
pass
|
| 3293 |
|
|
|
| 3294 |
|
|
elif la_ == 61:
|
| 3295 |
|
|
localctx = HPC16Parser.Pop_regContext(self, localctx)
|
| 3296 |
|
|
self.enterOuterAlt(localctx, 61)
|
| 3297 |
|
|
self.state = 287
|
| 3298 |
|
|
self.match(HPC16Parser.T__33)
|
| 3299 |
|
|
self.state = 288
|
| 3300 |
|
|
self.match(HPC16Parser.REG)
|
| 3301 |
|
|
pass
|
| 3302 |
|
|
|
| 3303 |
|
|
elif la_ == 62:
|
| 3304 |
|
|
localctx = HPC16Parser.PopfContext(self, localctx)
|
| 3305 |
|
|
self.enterOuterAlt(localctx, 62)
|
| 3306 |
|
|
self.state = 289
|
| 3307 |
|
|
self.match(HPC16Parser.T__34)
|
| 3308 |
|
|
pass
|
| 3309 |
|
|
|
| 3310 |
|
|
elif la_ == 63:
|
| 3311 |
|
|
localctx = HPC16Parser.Acall_regContext(self, localctx)
|
| 3312 |
|
|
self.enterOuterAlt(localctx, 63)
|
| 3313 |
|
|
self.state = 290
|
| 3314 |
|
|
self.match(HPC16Parser.T__35)
|
| 3315 |
|
|
self.state = 291
|
| 3316 |
|
|
self.match(HPC16Parser.T__3)
|
| 3317 |
|
|
self.state = 292
|
| 3318 |
|
|
self.match(HPC16Parser.REG)
|
| 3319 |
|
|
self.state = 293
|
| 3320 |
|
|
self.match(HPC16Parser.T__4)
|
| 3321 |
|
|
pass
|
| 3322 |
|
|
|
| 3323 |
|
|
elif la_ == 64:
|
| 3324 |
|
|
localctx = HPC16Parser.Call_regContext(self, localctx)
|
| 3325 |
|
|
self.enterOuterAlt(localctx, 64)
|
| 3326 |
|
|
self.state = 294
|
| 3327 |
|
|
self.match(HPC16Parser.T__36)
|
| 3328 |
|
|
self.state = 295
|
| 3329 |
|
|
self.match(HPC16Parser.T__3)
|
| 3330 |
|
|
self.state = 296
|
| 3331 |
|
|
self.match(HPC16Parser.REG)
|
| 3332 |
|
|
self.state = 297
|
| 3333 |
|
|
self.match(HPC16Parser.T__4)
|
| 3334 |
|
|
pass
|
| 3335 |
|
|
|
| 3336 |
|
|
elif la_ == 65:
|
| 3337 |
|
|
localctx = HPC16Parser.Call_imm11Context(self, localctx)
|
| 3338 |
|
|
self.enterOuterAlt(localctx, 65)
|
| 3339 |
|
|
self.state = 298
|
| 3340 |
|
|
self.match(HPC16Parser.T__36)
|
| 3341 |
|
|
self.state = 299
|
| 3342 |
|
|
self.match(HPC16Parser.T__3)
|
| 3343 |
|
|
self.state = 300
|
| 3344 |
|
|
self.match(HPC16Parser.IMM)
|
| 3345 |
|
|
self.state = 301
|
| 3346 |
|
|
self.match(HPC16Parser.T__4)
|
| 3347 |
|
|
pass
|
| 3348 |
|
|
|
| 3349 |
|
|
elif la_ == 66:
|
| 3350 |
|
|
localctx = HPC16Parser.RetContext(self, localctx)
|
| 3351 |
|
|
self.enterOuterAlt(localctx, 66)
|
| 3352 |
|
|
self.state = 302
|
| 3353 |
|
|
self.match(HPC16Parser.T__37)
|
| 3354 |
|
|
pass
|
| 3355 |
|
|
|
| 3356 |
|
|
elif la_ == 67:
|
| 3357 |
|
|
localctx = HPC16Parser.IretContext(self, localctx)
|
| 3358 |
|
|
self.enterOuterAlt(localctx, 67)
|
| 3359 |
|
|
self.state = 303
|
| 3360 |
|
|
self.match(HPC16Parser.T__38)
|
| 3361 |
|
|
pass
|
| 3362 |
|
|
|
| 3363 |
|
|
elif la_ == 68:
|
| 3364 |
|
|
localctx = HPC16Parser.ClcContext(self, localctx)
|
| 3365 |
|
|
self.enterOuterAlt(localctx, 68)
|
| 3366 |
|
|
self.state = 304
|
| 3367 |
|
|
self.match(HPC16Parser.T__39)
|
| 3368 |
|
|
pass
|
| 3369 |
|
|
|
| 3370 |
|
|
elif la_ == 69:
|
| 3371 |
|
|
localctx = HPC16Parser.StcContext(self, localctx)
|
| 3372 |
|
|
self.enterOuterAlt(localctx, 69)
|
| 3373 |
|
|
self.state = 305
|
| 3374 |
|
|
self.match(HPC16Parser.T__40)
|
| 3375 |
|
|
pass
|
| 3376 |
|
|
|
| 3377 |
|
|
elif la_ == 70:
|
| 3378 |
|
|
localctx = HPC16Parser.CmcContext(self, localctx)
|
| 3379 |
|
|
self.enterOuterAlt(localctx, 70)
|
| 3380 |
|
|
self.state = 306
|
| 3381 |
|
|
self.match(HPC16Parser.T__41)
|
| 3382 |
|
|
pass
|
| 3383 |
|
|
|
| 3384 |
|
|
elif la_ == 71:
|
| 3385 |
|
|
localctx = HPC16Parser.CliContext(self, localctx)
|
| 3386 |
|
|
self.enterOuterAlt(localctx, 71)
|
| 3387 |
|
|
self.state = 307
|
| 3388 |
|
|
self.match(HPC16Parser.T__42)
|
| 3389 |
|
|
pass
|
| 3390 |
|
|
|
| 3391 |
|
|
elif la_ == 72:
|
| 3392 |
|
|
localctx = HPC16Parser.StiContext(self, localctx)
|
| 3393 |
|
|
self.enterOuterAlt(localctx, 72)
|
| 3394 |
|
|
self.state = 308
|
| 3395 |
|
|
self.match(HPC16Parser.T__43)
|
| 3396 |
|
|
pass
|
| 3397 |
|
|
|
| 3398 |
|
|
elif la_ == 73:
|
| 3399 |
|
|
localctx = HPC16Parser.Int_imm4Context(self, localctx)
|
| 3400 |
|
|
self.enterOuterAlt(localctx, 73)
|
| 3401 |
|
|
self.state = 309
|
| 3402 |
|
|
self.match(HPC16Parser.T__44)
|
| 3403 |
|
|
self.state = 310
|
| 3404 |
|
|
self.match(HPC16Parser.IMM)
|
| 3405 |
|
|
pass
|
| 3406 |
|
|
|
| 3407 |
|
|
elif la_ == 74:
|
| 3408 |
|
|
localctx = HPC16Parser.IntoContext(self, localctx)
|
| 3409 |
|
|
self.enterOuterAlt(localctx, 74)
|
| 3410 |
|
|
self.state = 311
|
| 3411 |
|
|
self.match(HPC16Parser.T__45)
|
| 3412 |
|
|
pass
|
| 3413 |
|
|
|
| 3414 |
|
|
elif la_ == 75:
|
| 3415 |
|
|
localctx = HPC16Parser.AjmpContext(self, localctx)
|
| 3416 |
|
|
self.enterOuterAlt(localctx, 75)
|
| 3417 |
|
|
self.state = 312
|
| 3418 |
|
|
self.match(HPC16Parser.T__46)
|
| 3419 |
|
|
self.state = 313
|
| 3420 |
|
|
self.match(HPC16Parser.T__3)
|
| 3421 |
|
|
self.state = 314
|
| 3422 |
|
|
self.match(HPC16Parser.REG)
|
| 3423 |
|
|
self.state = 315
|
| 3424 |
|
|
self.match(HPC16Parser.T__4)
|
| 3425 |
|
|
pass
|
| 3426 |
|
|
|
| 3427 |
|
|
elif la_ == 76:
|
| 3428 |
|
|
localctx = HPC16Parser.Jmp_regContext(self, localctx)
|
| 3429 |
|
|
self.enterOuterAlt(localctx, 76)
|
| 3430 |
|
|
self.state = 316
|
| 3431 |
|
|
self.match(HPC16Parser.T__47)
|
| 3432 |
|
|
self.state = 317
|
| 3433 |
|
|
self.match(HPC16Parser.T__3)
|
| 3434 |
|
|
self.state = 318
|
| 3435 |
|
|
self.match(HPC16Parser.REG)
|
| 3436 |
|
|
self.state = 319
|
| 3437 |
|
|
self.match(HPC16Parser.T__4)
|
| 3438 |
|
|
pass
|
| 3439 |
|
|
|
| 3440 |
|
|
elif la_ == 77:
|
| 3441 |
|
|
localctx = HPC16Parser.Jmp_imm11Context(self, localctx)
|
| 3442 |
|
|
self.enterOuterAlt(localctx, 77)
|
| 3443 |
|
|
self.state = 320
|
| 3444 |
|
|
self.match(HPC16Parser.T__47)
|
| 3445 |
|
|
self.state = 321
|
| 3446 |
|
|
self.match(HPC16Parser.T__3)
|
| 3447 |
|
|
self.state = 322
|
| 3448 |
|
|
self.match(HPC16Parser.IMM)
|
| 3449 |
|
|
self.state = 323
|
| 3450 |
|
|
self.match(HPC16Parser.T__4)
|
| 3451 |
|
|
pass
|
| 3452 |
|
|
|
| 3453 |
|
|
elif la_ == 78:
|
| 3454 |
|
|
localctx = HPC16Parser.NopContext(self, localctx)
|
| 3455 |
|
|
self.enterOuterAlt(localctx, 78)
|
| 3456 |
|
|
self.state = 324
|
| 3457 |
|
|
self.match(HPC16Parser.T__48)
|
| 3458 |
|
|
pass
|
| 3459 |
|
|
|
| 3460 |
|
|
elif la_ == 79:
|
| 3461 |
|
|
localctx = HPC16Parser.HaltContext(self, localctx)
|
| 3462 |
|
|
self.enterOuterAlt(localctx, 79)
|
| 3463 |
|
|
self.state = 325
|
| 3464 |
|
|
self.match(HPC16Parser.T__49)
|
| 3465 |
|
|
pass
|
| 3466 |
|
|
|
| 3467 |
|
|
elif la_ == 80:
|
| 3468 |
|
|
localctx = HPC16Parser.Jo_imm7Context(self, localctx)
|
| 3469 |
|
|
self.enterOuterAlt(localctx, 80)
|
| 3470 |
|
|
self.state = 326
|
| 3471 |
|
|
self.match(HPC16Parser.T__50)
|
| 3472 |
|
|
self.state = 327
|
| 3473 |
|
|
self.match(HPC16Parser.IMM)
|
| 3474 |
|
|
pass
|
| 3475 |
|
|
|
| 3476 |
|
|
elif la_ == 81:
|
| 3477 |
|
|
localctx = HPC16Parser.Jno_imm7Context(self, localctx)
|
| 3478 |
|
|
self.enterOuterAlt(localctx, 81)
|
| 3479 |
|
|
self.state = 328
|
| 3480 |
|
|
self.match(HPC16Parser.T__51)
|
| 3481 |
|
|
self.state = 329
|
| 3482 |
|
|
self.match(HPC16Parser.IMM)
|
| 3483 |
|
|
pass
|
| 3484 |
|
|
|
| 3485 |
|
|
elif la_ == 82:
|
| 3486 |
|
|
localctx = HPC16Parser.Jb_imm7Context(self, localctx)
|
| 3487 |
|
|
self.enterOuterAlt(localctx, 82)
|
| 3488 |
|
|
self.state = 330
|
| 3489 |
|
|
self.match(HPC16Parser.T__52)
|
| 3490 |
|
|
self.state = 331
|
| 3491 |
|
|
self.match(HPC16Parser.IMM)
|
| 3492 |
|
|
pass
|
| 3493 |
|
|
|
| 3494 |
|
|
elif la_ == 83:
|
| 3495 |
|
|
localctx = HPC16Parser.Jnae_imm7Context(self, localctx)
|
| 3496 |
|
|
self.enterOuterAlt(localctx, 83)
|
| 3497 |
|
|
self.state = 332
|
| 3498 |
|
|
self.match(HPC16Parser.T__53)
|
| 3499 |
|
|
self.state = 333
|
| 3500 |
|
|
self.match(HPC16Parser.IMM)
|
| 3501 |
|
|
pass
|
| 3502 |
|
|
|
| 3503 |
|
|
elif la_ == 84:
|
| 3504 |
|
|
localctx = HPC16Parser.Jnb_imm7Context(self, localctx)
|
| 3505 |
|
|
self.enterOuterAlt(localctx, 84)
|
| 3506 |
|
|
self.state = 334
|
| 3507 |
|
|
self.match(HPC16Parser.T__54)
|
| 3508 |
|
|
self.state = 335
|
| 3509 |
|
|
self.match(HPC16Parser.IMM)
|
| 3510 |
|
|
pass
|
| 3511 |
|
|
|
| 3512 |
|
|
elif la_ == 85:
|
| 3513 |
|
|
localctx = HPC16Parser.Jae_imm7Context(self, localctx)
|
| 3514 |
|
|
self.enterOuterAlt(localctx, 85)
|
| 3515 |
|
|
self.state = 336
|
| 3516 |
|
|
self.match(HPC16Parser.T__55)
|
| 3517 |
|
|
self.state = 337
|
| 3518 |
|
|
self.match(HPC16Parser.IMM)
|
| 3519 |
|
|
pass
|
| 3520 |
|
|
|
| 3521 |
|
|
elif la_ == 86:
|
| 3522 |
|
|
localctx = HPC16Parser.Je_imm7Context(self, localctx)
|
| 3523 |
|
|
self.enterOuterAlt(localctx, 86)
|
| 3524 |
|
|
self.state = 338
|
| 3525 |
|
|
self.match(HPC16Parser.T__56)
|
| 3526 |
|
|
self.state = 339
|
| 3527 |
|
|
self.match(HPC16Parser.IMM)
|
| 3528 |
|
|
pass
|
| 3529 |
|
|
|
| 3530 |
|
|
elif la_ == 87:
|
| 3531 |
|
|
localctx = HPC16Parser.Jz_imm7Context(self, localctx)
|
| 3532 |
|
|
self.enterOuterAlt(localctx, 87)
|
| 3533 |
|
|
self.state = 340
|
| 3534 |
|
|
self.match(HPC16Parser.T__57)
|
| 3535 |
|
|
self.state = 341
|
| 3536 |
|
|
self.match(HPC16Parser.IMM)
|
| 3537 |
|
|
pass
|
| 3538 |
|
|
|
| 3539 |
|
|
elif la_ == 88:
|
| 3540 |
|
|
localctx = HPC16Parser.Jne_imm7Context(self, localctx)
|
| 3541 |
|
|
self.enterOuterAlt(localctx, 88)
|
| 3542 |
|
|
self.state = 342
|
| 3543 |
|
|
self.match(HPC16Parser.T__58)
|
| 3544 |
|
|
self.state = 343
|
| 3545 |
|
|
self.match(HPC16Parser.IMM)
|
| 3546 |
|
|
pass
|
| 3547 |
|
|
|
| 3548 |
|
|
elif la_ == 89:
|
| 3549 |
|
|
localctx = HPC16Parser.Jnz_imm7Context(self, localctx)
|
| 3550 |
|
|
self.enterOuterAlt(localctx, 89)
|
| 3551 |
|
|
self.state = 344
|
| 3552 |
|
|
self.match(HPC16Parser.T__59)
|
| 3553 |
|
|
self.state = 345
|
| 3554 |
|
|
self.match(HPC16Parser.IMM)
|
| 3555 |
|
|
pass
|
| 3556 |
|
|
|
| 3557 |
|
|
elif la_ == 90:
|
| 3558 |
|
|
localctx = HPC16Parser.Jbe_imm7Context(self, localctx)
|
| 3559 |
|
|
self.enterOuterAlt(localctx, 90)
|
| 3560 |
|
|
self.state = 346
|
| 3561 |
|
|
self.match(HPC16Parser.T__60)
|
| 3562 |
|
|
self.state = 347
|
| 3563 |
|
|
self.match(HPC16Parser.IMM)
|
| 3564 |
|
|
pass
|
| 3565 |
|
|
|
| 3566 |
|
|
elif la_ == 91:
|
| 3567 |
|
|
localctx = HPC16Parser.Jna_imm7Context(self, localctx)
|
| 3568 |
|
|
self.enterOuterAlt(localctx, 91)
|
| 3569 |
|
|
self.state = 348
|
| 3570 |
|
|
self.match(HPC16Parser.T__61)
|
| 3571 |
|
|
self.state = 349
|
| 3572 |
|
|
self.match(HPC16Parser.IMM)
|
| 3573 |
|
|
pass
|
| 3574 |
|
|
|
| 3575 |
|
|
elif la_ == 92:
|
| 3576 |
|
|
localctx = HPC16Parser.Jnbe_imm7Context(self, localctx)
|
| 3577 |
|
|
self.enterOuterAlt(localctx, 92)
|
| 3578 |
|
|
self.state = 350
|
| 3579 |
|
|
self.match(HPC16Parser.T__62)
|
| 3580 |
|
|
self.state = 351
|
| 3581 |
|
|
self.match(HPC16Parser.IMM)
|
| 3582 |
|
|
pass
|
| 3583 |
|
|
|
| 3584 |
|
|
elif la_ == 93:
|
| 3585 |
|
|
localctx = HPC16Parser.Ja_imm7Context(self, localctx)
|
| 3586 |
|
|
self.enterOuterAlt(localctx, 93)
|
| 3587 |
|
|
self.state = 352
|
| 3588 |
|
|
self.match(HPC16Parser.T__63)
|
| 3589 |
|
|
self.state = 353
|
| 3590 |
|
|
self.match(HPC16Parser.IMM)
|
| 3591 |
|
|
pass
|
| 3592 |
|
|
|
| 3593 |
|
|
elif la_ == 94:
|
| 3594 |
|
|
localctx = HPC16Parser.Js_imm7Context(self, localctx)
|
| 3595 |
|
|
self.enterOuterAlt(localctx, 94)
|
| 3596 |
|
|
self.state = 354
|
| 3597 |
|
|
self.match(HPC16Parser.T__64)
|
| 3598 |
|
|
self.state = 355
|
| 3599 |
|
|
self.match(HPC16Parser.IMM)
|
| 3600 |
|
|
pass
|
| 3601 |
|
|
|
| 3602 |
|
|
elif la_ == 95:
|
| 3603 |
|
|
localctx = HPC16Parser.Jns_imm7Context(self, localctx)
|
| 3604 |
|
|
self.enterOuterAlt(localctx, 95)
|
| 3605 |
|
|
self.state = 356
|
| 3606 |
|
|
self.match(HPC16Parser.T__65)
|
| 3607 |
|
|
self.state = 357
|
| 3608 |
|
|
self.match(HPC16Parser.IMM)
|
| 3609 |
|
|
pass
|
| 3610 |
|
|
|
| 3611 |
|
|
elif la_ == 96:
|
| 3612 |
|
|
localctx = HPC16Parser.Jl_imm7Context(self, localctx)
|
| 3613 |
|
|
self.enterOuterAlt(localctx, 96)
|
| 3614 |
|
|
self.state = 358
|
| 3615 |
|
|
self.match(HPC16Parser.T__66)
|
| 3616 |
|
|
self.state = 359
|
| 3617 |
|
|
self.match(HPC16Parser.IMM)
|
| 3618 |
|
|
pass
|
| 3619 |
|
|
|
| 3620 |
|
|
elif la_ == 97:
|
| 3621 |
|
|
localctx = HPC16Parser.Jnge_imm7Context(self, localctx)
|
| 3622 |
|
|
self.enterOuterAlt(localctx, 97)
|
| 3623 |
|
|
self.state = 360
|
| 3624 |
|
|
self.match(HPC16Parser.T__67)
|
| 3625 |
|
|
self.state = 361
|
| 3626 |
|
|
self.match(HPC16Parser.IMM)
|
| 3627 |
|
|
pass
|
| 3628 |
|
|
|
| 3629 |
|
|
elif la_ == 98:
|
| 3630 |
|
|
localctx = HPC16Parser.Jnl_imm7Context(self, localctx)
|
| 3631 |
|
|
self.enterOuterAlt(localctx, 98)
|
| 3632 |
|
|
self.state = 362
|
| 3633 |
|
|
self.match(HPC16Parser.T__68)
|
| 3634 |
|
|
self.state = 363
|
| 3635 |
|
|
self.match(HPC16Parser.IMM)
|
| 3636 |
|
|
pass
|
| 3637 |
|
|
|
| 3638 |
|
|
elif la_ == 99:
|
| 3639 |
|
|
localctx = HPC16Parser.Jge_imm7Context(self, localctx)
|
| 3640 |
|
|
self.enterOuterAlt(localctx, 99)
|
| 3641 |
|
|
self.state = 364
|
| 3642 |
|
|
self.match(HPC16Parser.T__69)
|
| 3643 |
|
|
self.state = 365
|
| 3644 |
|
|
self.match(HPC16Parser.IMM)
|
| 3645 |
|
|
pass
|
| 3646 |
|
|
|
| 3647 |
|
|
elif la_ == 100:
|
| 3648 |
|
|
localctx = HPC16Parser.Jle_imm7Context(self, localctx)
|
| 3649 |
|
|
self.enterOuterAlt(localctx, 100)
|
| 3650 |
|
|
self.state = 366
|
| 3651 |
|
|
self.match(HPC16Parser.T__70)
|
| 3652 |
|
|
self.state = 367
|
| 3653 |
|
|
self.match(HPC16Parser.IMM)
|
| 3654 |
|
|
pass
|
| 3655 |
|
|
|
| 3656 |
|
|
elif la_ == 101:
|
| 3657 |
|
|
localctx = HPC16Parser.Jng_imm7Context(self, localctx)
|
| 3658 |
|
|
self.enterOuterAlt(localctx, 101)
|
| 3659 |
|
|
self.state = 368
|
| 3660 |
|
|
self.match(HPC16Parser.T__71)
|
| 3661 |
|
|
self.state = 369
|
| 3662 |
|
|
self.match(HPC16Parser.IMM)
|
| 3663 |
|
|
pass
|
| 3664 |
|
|
|
| 3665 |
|
|
elif la_ == 102:
|
| 3666 |
|
|
localctx = HPC16Parser.Jnle_imm7Context(self, localctx)
|
| 3667 |
|
|
self.enterOuterAlt(localctx, 102)
|
| 3668 |
|
|
self.state = 370
|
| 3669 |
|
|
self.match(HPC16Parser.T__72)
|
| 3670 |
|
|
self.state = 371
|
| 3671 |
|
|
self.match(HPC16Parser.IMM)
|
| 3672 |
|
|
pass
|
| 3673 |
|
|
|
| 3674 |
|
|
elif la_ == 103:
|
| 3675 |
|
|
localctx = HPC16Parser.Jg_imm7Context(self, localctx)
|
| 3676 |
|
|
self.enterOuterAlt(localctx, 103)
|
| 3677 |
|
|
self.state = 372
|
| 3678 |
|
|
self.match(HPC16Parser.T__73)
|
| 3679 |
|
|
self.state = 373
|
| 3680 |
|
|
self.match(HPC16Parser.IMM)
|
| 3681 |
|
|
pass
|
| 3682 |
|
|
|
| 3683 |
|
|
|
| 3684 |
|
|
except RecognitionException as re:
|
| 3685 |
|
|
localctx.exception = re
|
| 3686 |
|
|
self._errHandler.reportError(self, re)
|
| 3687 |
|
|
self._errHandler.recover(self, re)
|
| 3688 |
|
|
finally:
|
| 3689 |
|
|
self.exitRule()
|
| 3690 |
|
|
return localctx
|
| 3691 |
|
|
|
| 3692 |
|
|
|
| 3693 |
|
|
|
| 3694 |
|
|
|
| 3695 |
|
|
|
