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[/] [i2c_to_wb/] [trunk/] [src/] [i2c_to_wb_fsm.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`include "timescale.v"
 
 
module
  i2c_to_wb_fsm
  (
    input         i2c_data,
    input         i2c_data_rise,
    input         i2c_data_fall,
 
    input         i2c_clk,
    input         i2c_clk_rise,
    input         i2c_clk_fall,
 
    input         i2c_r_w_bit,
    input         i2c_ack_out,
    output        i2c_ack_done,
 
    output        tip_addr_byte,
    output        tip_read_byte,
    output        tip_write_byte,
    output        tip_wr_ack,
    output        tip_rd_ack,
    output        tip_addr_ack,
 
    output  [7:0] state_out,
    output        i2c_error,
 
    input         wb_clk_i,
    input         wb_rst_i
  );
 
  // --------------------------------------------------------------------
  //  wires
  wire xmt_byte_done;
 
  wire tip_ack;
 
 
  // --------------------------------------------------------------------
  //  start & stop & ack
 
  wire start_detected = i2c_data_fall & i2c_clk;
  wire stop_detected  = i2c_data_rise & i2c_clk;
 
 
  // --------------------------------------------------------------------
  //  state machine
 
  localparam   STATE_IDLE       = 8'b00000001;
  localparam   STATE_ADDR_BYTE  = 8'b00000010;
  localparam   STATE_ADDR_ACK   = 8'b00000100;
  localparam   STATE_WRITE      = 8'b00001000;
  localparam   STATE_WR_ACK     = 8'b00010000;
  localparam   STATE_READ       = 8'b00100000;
  localparam   STATE_RD_ACK     = 8'b01000000;
  localparam   STATE_ERROR      = 8'b10000000;
 
  reg [7:0] state;
  reg [7:0] next_state;
 
  always @(posedge wb_clk_i or posedge wb_rst_i)
    if(wb_rst_i)
      state <= STATE_IDLE;
    else
      state <= next_state;
 
  always @(*)
    case( state )
      STATE_IDLE:       if( start_detected )
                          next_state = STATE_ADDR_BYTE;
                        else
                          next_state = STATE_IDLE;
 
      STATE_ADDR_BYTE:  if( xmt_byte_done )
                          next_state = STATE_ADDR_ACK;
                        else if( stop_detected )
                          next_state = STATE_ERROR;
                        else
                          next_state = STATE_ADDR_BYTE;
 
      STATE_ADDR_ACK:   if(i2c_ack_out)
                          next_state = STATE_IDLE;
                        else
                          if( i2c_ack_done )
                            if( i2c_r_w_bit )
                              next_state = STATE_READ;
                            else
                              next_state = STATE_WRITE;
                          else if( start_detected | stop_detected )
                            next_state = STATE_ERROR;
                          else
                            next_state = STATE_ADDR_ACK;
 
      STATE_WRITE:      if( xmt_byte_done )
                          next_state = STATE_WR_ACK;
                        else if( start_detected )
                          next_state = STATE_ADDR_BYTE;
                        else if( stop_detected )
                          next_state = STATE_IDLE;
                        else
                          next_state = STATE_WRITE;
 
      STATE_WR_ACK:     if( i2c_ack_done )
                          next_state = STATE_WRITE;
                        else if( start_detected | stop_detected )
                          next_state = STATE_ERROR;
                        else
                          next_state = STATE_WR_ACK;
 
      STATE_READ:       if( xmt_byte_done )
                          next_state = STATE_RD_ACK;
                        else if( start_detected )
                          next_state = STATE_ADDR_BYTE;
                        else if( stop_detected )
                          next_state = STATE_IDLE;
                        else
                          next_state = STATE_READ;
 
      STATE_RD_ACK:     if( i2c_ack_done )
                          if(i2c_data)
                            next_state = STATE_IDLE;
                          else
                            next_state = STATE_READ;
                        else if( start_detected | stop_detected )
                          next_state = STATE_ERROR;
                        else
                          next_state = STATE_RD_ACK;
 
      STATE_ERROR:      next_state = STATE_IDLE;
 
      default:          next_state = STATE_ERROR;
    endcase
 
 
  // --------------------------------------------------------------------
  //  bit counter
  reg [3:0] bit_count;
 
  assign  xmt_byte_done = (bit_count == 4'h7) & i2c_clk_rise;
  assign  tip_ack       = (bit_count == 4'h8);
  assign  i2c_ack_done  = tip_ack & i2c_clk_rise;
 
  always @(posedge wb_clk_i)
    if( wb_rst_i | i2c_ack_done | start_detected )
      bit_count <= 4'hf;
    else if( i2c_clk_fall )
      bit_count <= bit_count + 1;
 
 
  // --------------------------------------------------------------------
  //  debug
  wire i2c_start_error = (state == STATE_ADDR_BYTE) & start_detected;
 
 
  // --------------------------------------------------------------------
  //  outputs
 
  assign state_out = state;
 
  assign  tip_addr_byte   = (state == STATE_ADDR_BYTE);
  assign  tip_addr_ack    = (state == STATE_ADDR_ACK);
  assign  tip_read_byte   = (state == STATE_READ);
  assign  tip_write_byte  = tip_addr_byte               | (state == STATE_WRITE);
  assign  tip_wr_ack      = tip_addr_ack                | (state == STATE_WR_ACK);
  assign  tip_rd_ack      = (state == STATE_RD_ACK);
 
  assign i2c_error = (state == STATE_ERROR) | i2c_start_error;
 
endmodule
 
 

Line No.	Rev	Author	Line
1	4	qaztronic	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
4			`//// ////`
5			`//// This source file may be used and distributed without ////`
6			`//// restriction provided that this copyright statement is not ////`
7			`//// removed from the file and that any derivative work contains ////`
8			`//// the original copyright notice and the associated disclaimer. ////`
9			`//// ////`
10			`//// This source file is free software; you can redistribute it ////`
11			`//// and/or modify it under the terms of the GNU Lesser General ////`
12			`//// Public License as published by the Free Software Foundation; ////`
13			`//// either version 2.1 of the License, or (at your option) any ////`
14			`//// later version. ////`
15			`//// ////`
16			`//// This source is distributed in the hope that it will be ////`
17			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
18			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
19			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
20			`//// details. ////`
21			`//// ////`
22			`//// You should have received a copy of the GNU Lesser General ////`
23			`//// Public License along with this source; if not, download it ////`
24			`//// from http://www.opencores.org/lgpl.shtml ////`
25			`//// ////`
26			`//////////////////////////////////////////////////////////////////////`
27	3	qaztronic
28
29			`include "timescale.v"
30
31
32			`module`
33			`i2c_to_wb_fsm`
34			`(`
35			`input i2c_data,`
36			`input i2c_data_rise,`
37			`input i2c_data_fall,`
38
39			`input i2c_clk,`
40			`input i2c_clk_rise,`
41			`input i2c_clk_fall,`
42	5	qaztronic
43	4	qaztronic	`input i2c_r_w_bit,`
44			`input i2c_ack_out,`
45	5	qaztronic	`output i2c_ack_done,`
46
47			`output tip_addr_byte,`
48			`output tip_read_byte,`
49			`output tip_write_byte,`
50			`output tip_wr_ack,`
51			`output tip_rd_ack,`
52			`output tip_addr_ack,`
53
54	3	qaztronic	`output [7:0] state_out,`
55	4	qaztronic	`output i2c_error,`
56	5	qaztronic
57			`input wb_clk_i,`
58			`input wb_rst_i`
59	3	qaztronic	`);`
60	5	qaztronic
61	3	qaztronic	`// --------------------------------------------------------------------`
62			`// wires`
63			`wire xmt_byte_done;`
64	5	qaztronic
65	3	qaztronic	`wire tip_ack;`
66
67	5	qaztronic
68	3	qaztronic	`// --------------------------------------------------------------------`
69	4	qaztronic	`// start & stop & ack`
70	5	qaztronic
71	3	qaztronic	`wire start_detected = i2c_data_fall & i2c_clk;`
72			`wire stop_detected = i2c_data_rise & i2c_clk;`
73	5	qaztronic
74
75	3	qaztronic	`// --------------------------------------------------------------------`
76			`// state machine`
77
78			`localparam STATE_IDLE = 8'b00000001;`
79			`localparam STATE_ADDR_BYTE = 8'b00000010;`
80			`localparam STATE_ADDR_ACK = 8'b00000100;`
81			`localparam STATE_WRITE = 8'b00001000;`
82			`localparam STATE_WR_ACK = 8'b00010000;`
83			`localparam STATE_READ = 8'b00100000;`
84			`localparam STATE_RD_ACK = 8'b01000000;`
85			`localparam STATE_ERROR = 8'b10000000;`
86
87			`reg [7:0] state;`
88			`reg [7:0] next_state;`
89	5	qaztronic
90	3	qaztronic	`always @(posedge wb_clk_i or posedge wb_rst_i)`
91			`if(wb_rst_i)`
92			`state <= STATE_IDLE;`
93			`else`
94			`state <= next_state;`
95
96			`always @(*)`
97			`case( state )`
98			`STATE_IDLE: if( start_detected )`
99			`next_state = STATE_ADDR_BYTE;`
100			`else`
101	5	qaztronic	`next_state = STATE_IDLE;`
102
103	3	qaztronic	`STATE_ADDR_BYTE: if( xmt_byte_done )`
104	4	qaztronic	`next_state = STATE_ADDR_ACK;`
105	5	qaztronic	`else if( stop_detected )`
106	3	qaztronic	`next_state = STATE_ERROR;`
107	5	qaztronic	`else`
108	3	qaztronic	`next_state = STATE_ADDR_BYTE;`
109	5	qaztronic
110	4	qaztronic	`STATE_ADDR_ACK: if(i2c_ack_out)`
111			`next_state = STATE_IDLE;`
112	5	qaztronic	`else`
113	4	qaztronic	`if( i2c_ack_done )`
114			`if( i2c_r_w_bit )`
115			`next_state = STATE_READ;`
116			`else`
117			`next_state = STATE_WRITE;`
118			`else if( start_detected \| stop_detected )`
119			`next_state = STATE_ERROR;`
120	3	qaztronic	`else`
121	4	qaztronic	`next_state = STATE_ADDR_ACK;`
122	5	qaztronic
123	3	qaztronic	`STATE_WRITE: if( xmt_byte_done )`
124			`next_state = STATE_WR_ACK;`
125			`else if( start_detected )`
126			`next_state = STATE_ADDR_BYTE;`
127			`else if( stop_detected )`
128			`next_state = STATE_IDLE;`
129			`else`
130			`next_state = STATE_WRITE;`
131	5	qaztronic
132	3	qaztronic	`STATE_WR_ACK: if( i2c_ack_done )`
133	5	qaztronic	`next_state = STATE_WRITE;`
134	3	qaztronic	`else if( start_detected \| stop_detected )`
135			`next_state = STATE_ERROR;`
136			`else`
137			`next_state = STATE_WR_ACK;`
138	5	qaztronic
139	3	qaztronic	`STATE_READ: if( xmt_byte_done )`
140			`next_state = STATE_RD_ACK;`
141			`else if( start_detected )`
142			`next_state = STATE_ADDR_BYTE;`
143			`else if( stop_detected )`
144			`next_state = STATE_IDLE;`
145			`else`
146			`next_state = STATE_READ;`
147	5	qaztronic
148	3	qaztronic	`STATE_RD_ACK: if( i2c_ack_done )`
149	4	qaztronic	`if(i2c_data)`
150	5	qaztronic	`next_state = STATE_IDLE;`
151	4	qaztronic	`else`
152	5	qaztronic	`next_state = STATE_READ;`
153	3	qaztronic	`else if( start_detected \| stop_detected )`
154			`next_state = STATE_ERROR;`
155			`else`
156			`next_state = STATE_RD_ACK;`
157	5	qaztronic
158	3	qaztronic	`STATE_ERROR: next_state = STATE_IDLE;`
159	5	qaztronic
160	3	qaztronic	`default: next_state = STATE_ERROR;`
161			`endcase`
162	5	qaztronic
163
164	3	qaztronic	`// --------------------------------------------------------------------`
165	5	qaztronic	`// bit counter`
166	3	qaztronic	`reg [3:0] bit_count;`
167	5	qaztronic
168			`assign xmt_byte_done = (bit_count == 4'h7) & i2c_clk_rise;`
169	3	qaztronic	`assign tip_ack = (bit_count == 4'h8);`
170			`assign i2c_ack_done = tip_ack & i2c_clk_rise;`
171	5	qaztronic
172	3	qaztronic	`always @(posedge wb_clk_i)`
173			`if( wb_rst_i \| i2c_ack_done \| start_detected )`
174			`bit_count <= 4'hf;`
175			`else if( i2c_clk_fall )`
176			`bit_count <= bit_count + 1;`
177	5	qaztronic
178
179			`// --------------------------------------------------------------------`
180			`// debug`
181			`wire i2c_start_error = (state == STATE_ADDR_BYTE) & start_detected;`
182
183
184			`// --------------------------------------------------------------------`
185			`// outputs`
186
187	3	qaztronic	`assign state_out = state;`
188	5	qaztronic
189	3	qaztronic	`assign tip_addr_byte = (state == STATE_ADDR_BYTE);`
190			`assign tip_addr_ack = (state == STATE_ADDR_ACK);`
191			`assign tip_read_byte = (state == STATE_READ);`
192			`assign tip_write_byte = tip_addr_byte \| (state == STATE_WRITE);`
193			`assign tip_wr_ack = tip_addr_ack \| (state == STATE_WR_ACK);`
194			`assign tip_rd_ack = (state == STATE_RD_ACK);`
195	4	qaztronic
196	5	qaztronic	`assign i2c_error = (state == STATE_ERROR) \| i2c_start_error;`
197
198	3	qaztronic	`endmodule`
199
200	5	qaztronic

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[/] [i2c_to_wb/] [trunk/] [src/] [i2c_to_wb_fsm.v] - Blame information for rev 5