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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity ebu_2_i2s is
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port(spdif_in : in std_logic; -- entree spdif
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nreset : in std_logic; -- remise a 0
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clock,ref_clock : in std_logic; -- a speed clock
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sync_start : out std_ulogic; -- apres detection de preambule B
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preambule_l : out std_ulogic; -- -decoded data
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preambule_r : out std_ulogic; -- -decoded data
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v_ctrl : out std_ulogic; -- -decoded data
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pll_v_setting : OUT std_logic_vector(8 downto 0); -- PLL parameter V
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pll_r_setting : OUT std_logic_vector(6 downto 0); -- PLL parameter R
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pll_s_setting : OUT std_logic_vector(2 downto 0); -- PLL parameter S
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pll_npd : OUT std_logic;
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copie_d : out std_ulogic;
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lr ,scl,serial_out : out std_ulogic; -- -decoded data
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data_v ,fin : out std_ulogic;
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begin_block : out std_ulogic -- -decoded data
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-- sclk : out std_logic_vector(6 downto 0) -- -decoded data
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-- bit_en,demi_bit_en : out std_logic -- -decoded data
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);
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end entity;
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architecture archi of ebu_2_i2s is
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constant v_24_576mhz : std_logic_vector(8 downto 0) := "101111000";
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constant r_24_576mhz : std_logic_vector(6 downto 0) := "0010111";
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constant s_24_576mhz : std_logic_vector(2 downto 0) := "100";
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signal var1,var2,var3,var4,var5,var6,var7,vara,varb,varc,vard,vare,varf,varg : std_ulogic;
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signal sortie : std_ulogic;
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signal high : std_ulogic := '1';
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signal n_spdif_in : std_ulogic;
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signal remise_0,n_remise_0 : std_ulogic ;
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signal s : std_ulogic_vector ( 7 downto 0):= "11111111";
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signal enable : std_ulogic;
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signal level_0,n_level_0 : std_ulogic;
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signal preambule_m,preambule_w : std_ulogic;
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type etat is (value,preamb_b,preamb_w,preamb_m);
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signal status : etat := preamb_b;
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signal entier : integer range 0 to 56 := 0;
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signal register_dat : std_ulogic_vector ( 55 downto 0);
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signal donnee : std_ulogic_vector ( 31 downto 0);
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signal dat : std_ulogic_vector ( 27 downto 0);
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signal end_frame : std_ulogic;
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signal data_valid : std_ulogic;
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signal pair : std_ulogic;
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signal sub_frame : integer range 0 to 384;
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signal echantillon1,echantillon0 : std_ulogic;
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signal i2s_cl,word_sel : std_ulogic:='1';
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signal left_right : std_ulogic:='0';
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signal valid_word : std_ulogic:='0';
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signal copie : std_ulogic:='0';
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signal charge,block_wsel : std_ulogic:='0';
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signal data_i : integer range 0 to 4;
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component dff port ( d,clk,clrn : in std_ulogic;
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q : out std_ulogic);
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end component;
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begin
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pll_v_setting <= v_24_576mhz; -- to programm th pll
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pll_r_setting <= r_24_576mhz; -- to programm th pll
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pll_s_setting <= s_24_576mhz; -- to programm th pll
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pll_npd<='1';
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n_spdif_in <= not spdif_in;
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n_remise_0 <= not remise_0;
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n_level_0 <= not level_0;
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echantillon1 <= var1 and var2 and not var3 ;
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echantillon0 <= vara and varb and not varc ;
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-- les dff pour les echantillonnages
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--------------------------------------------------------------
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dff1 : dff port map ( d => spdif_in,
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clk => clock,
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clrn => n_remise_0,
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q => var1
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);
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dff2 : dff port map ( d => var1,
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clk => clock,
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clrn => n_remise_0,
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q => var2
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);
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dff3 : dff port map ( d => var2,
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clk => clock,
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clrn => n_remise_0,
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q => var3
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);
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dff4 : dff port map ( d => var3,
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clk => clock,
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clrn => n_remise_0,
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q => var4
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);
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dff5 : dff port map ( d => var4,
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clk => clock,
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clrn => n_remise_0,
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q => var5
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);
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dff6 : dff port map ( d => var5,
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clk => clock,
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clrn => n_remise_0,
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q => var6
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);
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dff7 : dff port map ( d => var6,
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clk => clock,
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clrn => n_remise_0,
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q => var7
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);
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dff8 : dff port map ( d => var7,
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clk => clock,
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clrn => n_remise_0,
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q => remise_0
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);
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--------------------------------------------------------------
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dffa : dff port map ( d => n_spdif_in,
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clk => clock,
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clrn => n_level_0,
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q => vara
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);
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dffb : dff port map ( d => vara,
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clk => clock,
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clrn => n_level_0,
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q => varb
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);
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dffc : dff port map ( d => varb,
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clk => clock,
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clrn => n_level_0,
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q => varc
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);
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dffd : dff port map ( d => varc,
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clk => clock,
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clrn => n_level_0,
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q => vard
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);
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dffe : dff port map ( d => vard,
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clk => clock,
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clrn => n_level_0,
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q => vare
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);
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dfff : dff port map ( d => vare,
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clk => clock,
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clrn => n_level_0,
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q => varf
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);
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dffg : dff port map ( d => varf,
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clk => clock,
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clrn => n_level_0,
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q => varg
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);
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dffh : dff port map ( d => varg,
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clk => clock,
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clrn => n_level_0,
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q => level_0
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);
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----------------------------------------------------------------------------+
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-- here I charge a register of 8 bits ,each bit correpsond to the value +
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-- of a haf period in spdif this one is sampled in the middle approximatlly +
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----------------------------------------------------------------------------------------------------------------+
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charge_preambule : process (nreset,clock,var1,var2,var3,vara,varb,varc) -- detection du preambule --+
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begin --+
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if nreset = '0' then s <= (others => '0'); --+
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elsif clock 'event and clock ='1' then if ( echantillon1 = '1' ) then s <= s( 6 downto 0) & '1'; --+
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elsif ( echantillon0 = '1') then s <= s( 6 downto 0) & '0';--+
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end if; --+
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end if; --+
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end process; --+
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--+
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----------------------------------------------------------------------------------------------------------------+
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-- after detection of each preambule we put a signal to a high level
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-- for approximatly a half period of spdif
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--------------------------------------------------------------------------------------------------------------------
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preambule_i : process (nreset,clock,s)
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begin
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if nreset = '0' then enable <= '0' ;preambule_w <= '0'; preambule_m <= '0';
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elsif clock 'event and clock ='0'
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then case s is
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when "11101000" => enable <= '1' ;
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when "00010111" => enable <= '1' ;
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when "11100010" => preambule_m <= '1';
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when "00011101" => preambule_m <= '1';
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when "11100100" => preambule_w <= '1';
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when "00011011" => preambule_w <= '1';
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when others => enable <= '0' ;preambule_w <= '0';
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preambule_m <= '0';
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end case;
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end if;
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end process;
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---------------------------------------------------------------------------------------------------------------
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-- the state machine contains four states three for preambules and one for value
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-- so here we can more serious in respect of synchronism
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state_machine :process(nreset,clock,pair,preambule_w,preambule_m,enable)
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begin
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if nreset ='0' then status <= preamb_b;
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elsif clock 'event and clock = '1' then case status is
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when preamb_b => if enable = '1' then status <= value; end if ;
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when preamb_w => if preambule_w = '1' then status <= value ; end if;
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when preamb_m => if preambule_m ='1' then status <= value; end if;
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when value => if end_frame = '0' then if data_valid ='1' then if pair = '1' then status <= preamb_m;
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else status <= preamb_w; end if;
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end if;
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else if data_valid ='1' then status <= preamb_b;end if;
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end if;
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end case;
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end if;
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end process;
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-- the process here is to determine when finishing on the status value then deteminte o wich
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-- we must go
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-- / preamb_w
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-- value < --- or preamb_b
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-- \ preamb_m
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--------------------------------------------------
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pros :process(nreset,clock,status,echantillon1,echantillon0,entier)
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begin
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if nreset = '0' or status = preamb_b or status = preamb_w or status = preamb_m then entier <= 0;
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elsif clock 'event and clock ='1' then if status = value then if ( echantillon1 ='1' ) then register_dat <= register_dat( 54 downto 0) & '1';
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if entier = 56 then entier <= 0; else entier <= entier +1;end if;
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elsif ( echantillon0 ='1') then register_dat <= register_dat( 54 downto 0) & '0';
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if entier = 56 then entier <= 0; else entier <= entier +1;end if;
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end if;
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end if;
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end if;
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if clock 'event and clock ='1' then if entier = 56 and status = value then data_valid <= '1';
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else data_valid <= '0';end if;
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end if;
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end process;
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--------------------------------------------------------------------------------------
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--end of block one block is 192 frames so 384 sub_frames
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--------------------------------------------------------------------------------------
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end_block :process (data_valid,nreset,entier) -- counts the numbers of sub-frames
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-- variable sub_frame : integer range 0 to 384;
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begin
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if nreset='0' or status = preamb_b then sub_frame<=0;
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elsif data_valid 'event and data_valid='1' then pair <= not pair;
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if sub_frame=384 then sub_frame<=0;
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else sub_frame <=sub_frame +1;end if;
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end if;
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if (sub_frame =383 and entier = 56 ) then end_frame<='1';
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else end_frame<='0'; end if;
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end process;
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-------------------------------------------------------------------------------+
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-- Second entity in the same block code +
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-- why ? for the reason that i will use the status variable to generate signals+
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-- the things that is not possible with two entity +
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-- +
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---------------------------------------------------------------------------------------------------------+
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i2s_clock : process(clock,echantillon1,echantillon0) --+
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-- variable a_bit : integer range 0 to 31; --+
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begin --+
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if nreset ='0' then i2s_cl <= '1'; --+
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elsif clock 'event and clock ='1' then if echantillon1= '1' then i2s_cl <= not i2s_cl;--+
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elsif echantillon0 ='1' then i2s_cl <= not i2s_cl;--+
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end if; --+
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--+
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end if; --+
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end process; --+
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---------------------------------------------------------------------------------------------------------+
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-- this process generates an i2s clock in this case we have 3.072Mhz
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---------------------------------------------------------------------------------------------------------+
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w_valid : process(status,nreset,entier)
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begin
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if nreset ='0' then valid_word <= '0';
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elsif clock 'event and clock = '1' then if status= value and entier = 55 then valid_word <= '1';end if;
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end if;
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end process;
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--------------------------------------------------------
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-- only needed signal for the state machine
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-----------------------------------------------
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number_bits : process(nreset,i2s_cl,status)
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begin
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if nreset ='0' or status = value then data_i <= 0;
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elsif i2s_cl 'event and i2s_cl = '1' then if (status= preamb_b or status = preamb_m or status = preamb_w)
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| 318 |
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then if data_i = 4 then data_i <= 0 ; else data_i <= data_i +1; end if;
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end if; end if;
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end process;
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-------------------------------------------------------
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-- only needed signal for the state machine
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| 326 |
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-----------------------------------------------
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| 327 |
|
|
decal_dat : process(nreset,i2s_cl,status)
|
| 328 |
|
|
begin
|
| 329 |
|
|
if nreset ='0' then charge <= '0';
|
| 330 |
|
|
elsif i2s_cl 'event and i2s_cl = '1' then case status is
|
| 331 |
|
|
when value => charge <= '0';block_wsel<='0';
|
| 332 |
|
|
when preamb_b => if data_i = 3 then charge <= '1' ; end if;
|
| 333 |
|
|
if data_i = 4 then block_wsel <= '1' ; end if;
|
| 334 |
|
|
when preamb_w => if data_i = 3 then charge <= '1' ; end if;
|
| 335 |
|
|
if data_i = 4 then block_wsel <= '1' ; end if;
|
| 336 |
|
|
when preamb_m => if data_i = 3 then charge <= '1' ; end if;
|
| 337 |
|
|
if data_i = 4 then block_wsel <= '1' ; end if;
|
| 338 |
|
|
end case;
|
| 339 |
|
|
end if;
|
| 340 |
|
|
end process;
|
| 341 |
|
|
-------------------------------------------------------
|
| 342 |
|
|
-- in each sub-frames a send 32 bit so we complete these bits with
|
| 343 |
|
|
-- zeros and the first zero in only for the reason that I implemented
|
| 344 |
|
|
-- a left justified protocol
|
| 345 |
|
|
-- so to change the i2s format change this process only
|
| 346 |
|
|
-----------------------------------------------------------
|
| 347 |
|
|
datas : process (nreset,i2s_cl,charge) --les datas a sortir
|
| 348 |
|
|
begin
|
| 349 |
|
|
if nreset = '0' then donnee <= (others => '0' );
|
| 350 |
|
|
elsif i2s_cl 'event and i2s_cl='0' then if charge ='1' and valid_word= '1' then
|
| 351 |
|
|
|
| 352 |
|
|
donnee(31 downto 0) <= "0000000" & dat(27 downto 4) & '0';
|
| 353 |
|
|
if block_wsel ='0' then word_sel <= not word_sel; end if;
|
| 354 |
|
|
else donnee(31 downto 0) <= '0' & donnee(31 downto 1) ;
|
| 355 |
|
|
end if;
|
| 356 |
|
|
end if;
|
| 357 |
|
|
end process;
|
| 358 |
|
|
------------------------------------------+
|
| 359 |
|
|
-- the registerd dat contains only the values sampled so need to know
|
| 360 |
|
|
-- the values corresponding : a xor function can do this
|
| 361 |
|
|
--------------------------------------------------+
|
| 362 |
|
|
msb_first : process(nreset,charge)
|
| 363 |
|
|
--variable I : integer range 0 to 27;
|
| 364 |
|
|
begin
|
| 365 |
|
|
if nreset = '0' then dat <=( others => '0');
|
| 366 |
|
|
elsif charge 'event and charge = '1' then for I in 0 to 27 loop
|
| 367 |
|
|
dat(I) <= register_dat(2*I) xor register_dat (2*I +1);
|
| 368 |
|
|
end loop;
|
| 369 |
|
|
end if;
|
| 370 |
|
|
end process;
|
| 371 |
|
|
|
| 372 |
|
|
--------------------------------------------------+
|
| 373 |
|
|
v_ctrl <= '1' when status = preamb_b else '0';
|
| 374 |
|
|
sync_start <= echantillon0;
|
| 375 |
|
|
lr <= word_sel;
|
| 376 |
|
|
preambule_l<= preambule_m;
|
| 377 |
|
|
preambule_r <= valid_word;
|
| 378 |
|
|
--sclk <= CONV_STD_LOGIC_VECTOR(entier,7);
|
| 379 |
|
|
data_v <= donnee(0) when status = value else '0' when status = value else '0';
|
| 380 |
|
|
begin_block <= end_frame;
|
| 381 |
|
|
fin <= i2s_cl;
|
| 382 |
|
|
copie_d <= block_wsel;
|
| 383 |
|
|
serial_out <= donnee(0);
|
| 384 |
|
|
end architecture;
|
