URL https://opencores.org/ocsvn/image_component_labeling_and_feature_extraction/image_component_labeling_and_feature_extraction/trunk

Subversion Repositories image_component_labeling_and_feature_extraction

[/] [image_component_labeling_and_feature_extraction/] [trunk/] [equivalenceTable.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log


 
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:24:37 10/25/2008 
-- Design Name: 
-- Module Name:    equivalenceTable - Struct 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity equivalenceTable is
    Port ( a                                    : in  STD_LOGIC_VECTOR (9 downto 0);
           b                                    : in  STD_LOGIC_VECTOR (9 downto 0);
                          c                                     : in  STD_LOGIC_VECTOR (9 downto 0);
           d                                    : in  STD_LOGIC_VECTOR (9 downto 0);
                          we                                    : in  STD_LOGIC;
                          readAddr                      : in  STD_LOGIC_VECTOR (9 downto 0);
           dout                                 : out STD_LOGIC_VECTOR (9 downto 0);
                          equalcnt                      : out STD_LOGIC_VECTOR (9 downto 0);
           fsync                                : in  STD_LOGIC;
           tableReady           : out  STD_LOGIC;
                          tablePreset           : in  STD_LOGIC;
                          reset                         : in  STD_LOGIC;
           clk                          : in  STD_LOGIC;
                          space                         : out STD_LOGIC;
                          SetdoutrefA        : out std_logic_vector(9 downto 0);--asynchronous out put of memory
                          SetdoutrefB        : out std_logic_vector(9 downto 0)
                          );
end equivalenceTable;
 
architecture Struct of equivalenceTable is
 
signal SaddrRA,SdoutA,SaddrRB,SdoutB,SaddrW,Sdin : std_logic_vector(9 downto 0);
signal TaddrRA,TdoutA,TaddrRB,TdoutB,TaddrW,Tdin : std_logic_vector(9 downto 0);
signal Twe,Swe,eqready,spc,selectSpace : std_logic := '0';
                        signal  Saddrefa :  STD_LOGIC_VECTOR (9 downto 0);
                        signal  Saddrefb :  STD_LOGIC_VECTOR (9 downto 0);
                        signal  Sdoutrefa : STD_LOGIC_VECTOR (9 downto 0);
                        signal  Sdoutrefb:  STD_LOGIC_VECTOR (9 downto 0);
         signal  Taddrefa :  STD_LOGIC_VECTOR (9 downto 0);
                        signal  Taddrefb :  STD_LOGIC_VECTOR (9 downto 0);
                        signal  Tdoutrefa : STD_LOGIC_VECTOR (9 downto 0);
                        signal  Tdoutrefb : STD_LOGIC_VECTOR (9 downto 0);
signal SetAddrW,PostAddrW,PreAddrW : std_logic_vector(9 downto 0);
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                signal PostAddrR,PostAddrRDelayed : std_logic_vector(9 downto 0);
signal SetDoutA,SetDoutB,PostDout : std_logic_vector(9 downto 0);                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                signal SetDin, PostDin, PreDin : std_logic_vector(9 downto 0);
 
signal SetWe,PostWe,PreWe : std_logic;
 
signal a_delay1,b_delay1 : std_logic_vector(9 downto 0);
 
type ppstatetype is (idle,startup1,startup2,indexing,toFindEqual,findEqual);
signal ppstate : ppstatetype;
signal tblwrite : std_logic_vector(9 downto 0); -- Used for debugging purposes
 
type ByteT is (c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,
                                                c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30,c31,c32,c33,c34,
                                                c35,c36,c37,c38,c39,c40,c41,c42,c43,c44,c45,c46,c47,c48,c49,c50,
                                                c51,c52,c53,c54,c55,c56,c57,c58,c59,c60,c61,c62,c63,c64,c65,c66,
                                                c67,c68,c69,c70,c71,c72,c73,c74,c75,c76,c77,c78,c79,c80,c81,c82,
                                                c83,c84,c85,c86,c87,c88,c89,c90,c91,c92,c93,c94,c95,c96,c97,c98,
                                                c99,c100,c101,c102,c103,c104,c105,c106,c107,c108,c109,c110,c111,
                                                c112,c113,c114,c115,c116,c117,c118,c119,c120,c121,c122,c123,c124,
                                                c125,c126,c127,c128,c129,c130,c131,c132,c133,c134,c135,c136,c137,
                                                c138,c139,c140,c141,c142,c143,c144,c145,c146,c147,c148,c149,c150,
                                                c151,c152,c153,c154,c155,c156,c157,c158,c159,c160,c161,c162,c163,
                                                c164,c165,c166,c167,c168,c169,c170,c171,c172,c173,c174,c175,c176,
                                                c177,c178,c179,c180,c181,c182,c183,c184,c185,c186,c187,c188,c189,
                                                c190,c191,c192,c193,c194,c195,c196,c197,c198,c199,c200,c201,c202,
                                                c203,c204,c205,c206,c207,c208,c209,c210,c211,c212,c213,c214,c215,
                                                c216,c217,c218,c219,c220,c221,c222,c223,c224,c225,c226,c227,c228,
                                                c229,c230,c231,c232,c233,c234,c235,c236,c237,c238,c239,c240,c241,
                                c242,c243,c244,c245,c246,c247,c248,c249,c250,c251,c252,c253,c254,c255);
  subtype Byte is ByteT;
  type ByteFileType is file of Byte;
  file outfile  : ByteFileType open write_mode is "Labels.bin";
 
begin
 
ramS : entity work.ram1w2r port map (
          addrefa => Saddrefa,
                          addrefb=> Saddrefb,
                          doutrefa => Sdoutrefa,
                          doutrefb => Sdoutrefb,
                          addrW => SaddrW,
           din => Sdin,
           we => Swe,
           addrRA => SaddrRA,
           doutA => SdoutA,
           addrRB => SaddrRB,
           doutB => SdoutB,
           clk => clk);
 
ramT : entity work.ram1w2r port map (
           addrefa => Taddrefa,
                          addrefb=> Taddrefb,
                          doutrefa => Tdoutrefa,
                          doutrefb => Tdoutrefb,
                          addrW => TaddrW,
           din => Tdin,
           we => Twe,
           addrRA => TaddrRA,
           doutA => TdoutA,
           addrRB => TaddrRB,
           doutB => TdoutB,
           clk => clk);
 
--=============== Multiplexer statements for selecting memories for interlieving of table accesses =======
--=============== selectSpace is the signal that controls interlieveing per frames                 =======
 
----------  Memory inputs -----------------------------
        SaddrRA <= c when selectSpace ='0' else
                                 PostAddrR;
        SaddrRB <= d when selectSpace = '0' else
                                  readAddr;
        SaddrW  <= SetAddrW when selectSpace='0' else
                             PostAddrW when eqready='0' else
                                  PreAddrW;
        Sdin      <= SetDin when selectSpace = '0' else
                                  PostDin when eqready = '0' else
                                  PreDin;
        Swe       <= SetWe when selectSpace='0' else
                                  PostWe when eqready = '0' else
                                  PreWe;
        Saddrefa <= a when selectSpace = '0' ;
        Saddrefb <= b when selectSpace = '0' ;
 
        TaddrRA <= c when selectSpace ='1' else
                                 PostAddrR;
        TaddrRB <= d when selectSpace = '1' else
                                  readAddr;
        TaddrW  <= SetAddrW when selectSpace='1' else
                             PostAddrW when eqready='0' else
                                  PreAddrW;
        Tdin      <= SetDin when selectSpace = '1' else
                                  PostDin when eqready = '0' else
                                  PreDin;
        Twe       <= SetWe when selectSpace='1' else
                                  PostWe when eqready = '0' else
                                  PreWe;
   Taddrefa <= a when selectSpace = '1';
        Taddrefb <= b when selectSpace = '1' ;
-------------------------------------------------------
 
----------  Memory outputs ----------------------------
 
        SetDoutA  <= SdoutA when selectSpace = '0' else
                                   TdoutA;
        SetDoutB <= SdoutB when selectSpace = '0' else
                                   TdoutB;
        PostDout <= SdoutA when selectSpace = '1' else
                                        TdoutA;
        dout            <= SdoutB when selectSpace = '1' else
                                        TdoutB;
        SetdoutrefA  <= Sdoutrefa when selectSpace = '0' else
                   Tdoutrefa;
        SetdoutrefB  <= Sdoutrefb when selectSpace = '0' else
                        Tdoutrefb;
 
-------------------------------------------------------
 
--====================== Other signal mappings =========================================================
        tableReady <= eqready;
        space <= selectspace;
--======================================================================================================
 
EqualSet : process(clk,reset)
 
   variable contentA, contentB : std_logic_vector(9 downto 0);
        begin
                if reset = '1' then
                        Setwe <= '0';
                        a_delay1 <= (others=>'0');
                        b_delay1 <= (others=>'0');
                        tblwrite <= (others=>'0');
 
                elsif clk'event and clk = '1' then
 
                        if fsync = '1' then
--                              write(outfile, ByteT'val(0));
--                              write(outfile, ByteT'val(0));
--                              write(outfile, ByteT'val(0));
                        end  if;
 
                        if we = '1' or fsync = '1' then
                                if a_delay1 = SetaddrW and Setwe = '1' then
                                        contentA := Setdin;
                                else
                                        contentA := SetDoutA;
                                end if;
                                if b_delay1 = SetaddrW and Setwe = '1' then
                                        contentB := Setdin;
                                else
                                        contentB := SetDoutB;
                                end if;
 
                                if contentA > contentB and a_delay1/= 0 and b_delay1/= 0 then
                                        SetaddrW <= contentA; -- Position a_store is overwritten by the smaller label in b_out
                                        Setdin <= contentB;
                                        Setwe <= '1';
                                        tblwrite <= tblwrite + 1;
--                                      write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(contentA))));
--                                      write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(contentB))));
                                        --write(outfile, ByteT'val(0));
                                elsif contentB > contentA and a_delay1/=0        and b_delay1/= 0 then
                                        SetaddrW <= contentB; -- Position b_store is overwritten by the smaller label in a_out
                                        Setdin <= contentA;
                                        Setwe <= '1';
                                        tblwrite <= tblwrite + 1;
--                                      write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(contentB))));
--                                      write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(contentA))));
                                        --write(outfile, ByteT'val(0));
                                else
                                        Setwe <= '0';
                                end if;
                        else
                                Setwe <= '0';
                        end if;
                   if(fsync = '1' ) then
                                a_delay1 <= (others=>'0');
                                b_delay1 <= (others=>'0');
                                tblwrite <= (others=>'0');
                        elsif we = '1' then
                                a_delay1 <= c;
                                b_delay1 <= d;
                        end if;
 
                end if;
 
        end process EqualSet;
PostProc : process(clk,reset)
 
        variable eqindex,aindex,bindex,equcnt : std_logic_vector(9 downto 0);
        variable incIndex : std_logic := '0';
        variable scount : std_logic_vector(6 downto 0);
        begin
                if reset = '1' then
                        spc <= '0';
                        selectSpace <= '0';
                        eqready <= '1';
                        eqindex := (others=>'0');
                        PostAddrR <= eqindex;
                        PostWe <= '0';
                        incIndex := '0';
                        equcnt := (others=>'0');
                        scount := (others=>'0');
 
                elsif clk'event and clk = '1' then
 
                        selectSpace <= spc;
 
                        case ppstate is
                                when idle=>
                                        if fsync = '1' then
                                                ppstate <= startup1;
                                                PostAddrR <= eqindex;
                                                eqready <= '0';
                                                eqindex := (others=>'0');
                                                spc <= not spc;
                                                equcnt := (others=>'0');
                                                scount := (others=>'0');
                                        end if;
                                        PostWe <= '0';
                                when startup1 =>
                                        ppstate <= startup2;
                                        PostAddrR <= eqindex;
                                        PostWe <= '0';
                                when startup2 =>
                                        scount := (others=>'0');
                                        ppstate <= indexing;
                                        PostAddrR <= eqindex;
                                        PostWe <= '0';
                                when indexing =>
                                        if fsync = '1' then
                                                ppstate <= startup1;
                                                PostAddrR <= eqindex;
                                                eqready <= '0';
                                                eqindex := (others=>'0');
                                                spc <= not spc;
                                                PostWe <= '0';
                                        elsif eqindex = 1023 then
                                                ppstate <= idle;
                                                eqready <= '1';
                                                PostWe <= '0';
                                        elsif PostAddrRDelayed /= PostDout and PostDout /= 0 then
                                                aindex := PostAddrRDelayed;
                                                bindex := PostDout;
                                                PostAddrR <= bindex;
                                                equcnt := equcnt + 1;
                                                ppstate <= toFindEqual;
                                                if incIndex = '1' then
                                                        eqindex := eqindex + 1;
                                                else
                                                        incIndex := '1';
                                                end if;
                                        elsif eqindex < 1023 then
                                                eqindex := eqindex + 1;
                                                PostAddrR <= eqindex;
                                                incIndex := '0';
                                        else
                                                eqready <= '1';
                                                equalcnt <= equcnt;
                                                ppstate <= idle;
                                        end if;
                                        PostWe <= '0';
                                when toFindEqual =>
                                        ppstate <= FindEqual;
                                        PostWe <= '0';
                                when findEqual =>
                                        if fsync = '1' then
                                                ppstate <= startup1;
                                                PostAddrR <= eqindex;
                                                eqready <= '0';
                                                eqindex := (others=>'0');
                                                spc <= not spc;
                                                PostWe <= '0';
                                        elsif PostAddrRDelayed /= PostDout and PostDout /= 0  and scount < 127 then
                                                bindex := PostDout;
                                                PostAddrR <= bindex;
                                                scount := scount + 1;
                                                PostWe <= '0';
                                        else
                                                PostAddrW <= aindex;
                                                PostDin <= bindex;
                                                PostWe <= '1';
                                                PostAddrR <= eqindex;
                                                ppstate <= startup2;
                                        end if;
                                when others =>
                                        ppstate <= idle;
                        end case;
                        PostAddrRDelayed <= PostAddrR;
                end if;
        end process PostProc;
 
 
PreSet : process(clk,reset)
 
        variable ind : std_logic_vector(9 downto 0);
        constant maxind : std_logic_vector(9 downto 0):= (others=>'1');
        begin
                if reset='1' then
                        ind := maxind;
                        PreWe <= '0';
                elsif clk'event and clk='1' then
                        if tablePreset = '1' and ind = maxind then
                                ind := (others=>'0');
                                PreAddrW <= ind;
                                PreDin <= ind;
                                PreWe <= '1';
                        elsif ind < maxind then
                                ind := ind + 1;
                                PreAddrW <= ind;
                                PreDin <= ind;
                                PreWe <= '1';
                        else
                                PreWe <= '0';
                        end if;
                end if;
        end process PreSet;
 
end Struct;
 

Browse

Tools

Subversion Repositories image_component_labeling_and_feature_extraction

[/] [image_component_labeling_and_feature_extraction/] [trunk/] [equivalenceTable.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	malikpearl
2			`----------------------------------------------------------------------------------`
3			`-- Company:`
4			`-- Engineer:`
5			`--`
6			`-- Create Date: 22:24:37 10/25/2008`
7			`-- Design Name:`
8			`-- Module Name: equivalenceTable - Struct`
9			`-- Project Name:`
10			`-- Target Devices:`
11			`-- Tool versions:`
12			`-- Description:`
13			`--`
14			`-- Dependencies:`
15			`--`
16			`-- Revision:`
17			`-- Revision 0.01 - File Created`
18			`-- Additional Comments:`
19			`--`
20			`----------------------------------------------------------------------------------`
21			`library IEEE;`
22			`use IEEE.STD_LOGIC_1164.ALL;`
23			`use IEEE.STD_LOGIC_ARITH.ALL;`
24			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
25
26			`---- Uncomment the following library declaration if instantiating`
27			`---- any Xilinx primitives in this code.`
28			`--library UNISIM;`
29			`--use UNISIM.VComponents.all;`
30
31			`entity equivalenceTable is`
32			`Port ( a : in STD_LOGIC_VECTOR (9 downto 0);`
33			`b : in STD_LOGIC_VECTOR (9 downto 0);`
34			`c : in STD_LOGIC_VECTOR (9 downto 0);`
35			`d : in STD_LOGIC_VECTOR (9 downto 0);`
36			`we : in STD_LOGIC;`
37			`readAddr : in STD_LOGIC_VECTOR (9 downto 0);`
38			`dout : out STD_LOGIC_VECTOR (9 downto 0);`
39			`equalcnt : out STD_LOGIC_VECTOR (9 downto 0);`
40			`fsync : in STD_LOGIC;`
41			`tableReady : out STD_LOGIC;`
42			`tablePreset : in STD_LOGIC;`
43			`reset : in STD_LOGIC;`
44			`clk : in STD_LOGIC;`
45			`space : out STD_LOGIC;`
46			`SetdoutrefA : out std_logic_vector(9 downto 0);--asynchronous out put of memory`
47			`SetdoutrefB : out std_logic_vector(9 downto 0)`
48			`);`
49			`end equivalenceTable;`
50
51			`architecture Struct of equivalenceTable is`
52
53			`signal SaddrRA,SdoutA,SaddrRB,SdoutB,SaddrW,Sdin : std_logic_vector(9 downto 0);`
54			`signal TaddrRA,TdoutA,TaddrRB,TdoutB,TaddrW,Tdin : std_logic_vector(9 downto 0);`
55			`signal Twe,Swe,eqready,spc,selectSpace : std_logic := '0';`
56			`signal Saddrefa : STD_LOGIC_VECTOR (9 downto 0);`
57			`signal Saddrefb : STD_LOGIC_VECTOR (9 downto 0);`
58			`signal Sdoutrefa : STD_LOGIC_VECTOR (9 downto 0);`
59			`signal Sdoutrefb: STD_LOGIC_VECTOR (9 downto 0);`
60			`signal Taddrefa : STD_LOGIC_VECTOR (9 downto 0);`
61			`signal Taddrefb : STD_LOGIC_VECTOR (9 downto 0);`
62			`signal Tdoutrefa : STD_LOGIC_VECTOR (9 downto 0);`
63			`signal Tdoutrefb : STD_LOGIC_VECTOR (9 downto 0);`
64			`signal SetAddrW,PostAddrW,PreAddrW : std_logic_vector(9 downto 0);`
65			`signal PostAddrR,PostAddrRDelayed : std_logic_vector(9 downto 0);`
66			signal SetDoutA,SetDoutB,PostDout : std_logic_vector(9 downto 0); signal SetDin, PostDin, PreDin : std_logic_vector(9 downto 0);
67
68			`signal SetWe,PostWe,PreWe : std_logic;`
69
70			`signal a_delay1,b_delay1 : std_logic_vector(9 downto 0);`
71
72			`type ppstatetype is (idle,startup1,startup2,indexing,toFindEqual,findEqual);`
73			`signal ppstate : ppstatetype;`
74			`signal tblwrite : std_logic_vector(9 downto 0); -- Used for debugging purposes`
75
76			`type ByteT is (c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,`
77			`c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30,c31,c32,c33,c34,`
78			`c35,c36,c37,c38,c39,c40,c41,c42,c43,c44,c45,c46,c47,c48,c49,c50,`
79			`c51,c52,c53,c54,c55,c56,c57,c58,c59,c60,c61,c62,c63,c64,c65,c66,`
80			`c67,c68,c69,c70,c71,c72,c73,c74,c75,c76,c77,c78,c79,c80,c81,c82,`
81			`c83,c84,c85,c86,c87,c88,c89,c90,c91,c92,c93,c94,c95,c96,c97,c98,`
82			`c99,c100,c101,c102,c103,c104,c105,c106,c107,c108,c109,c110,c111,`
83			`c112,c113,c114,c115,c116,c117,c118,c119,c120,c121,c122,c123,c124,`
84			`c125,c126,c127,c128,c129,c130,c131,c132,c133,c134,c135,c136,c137,`
85			`c138,c139,c140,c141,c142,c143,c144,c145,c146,c147,c148,c149,c150,`
86			`c151,c152,c153,c154,c155,c156,c157,c158,c159,c160,c161,c162,c163,`
87			`c164,c165,c166,c167,c168,c169,c170,c171,c172,c173,c174,c175,c176,`
88			`c177,c178,c179,c180,c181,c182,c183,c184,c185,c186,c187,c188,c189,`
89			`c190,c191,c192,c193,c194,c195,c196,c197,c198,c199,c200,c201,c202,`
90			`c203,c204,c205,c206,c207,c208,c209,c210,c211,c212,c213,c214,c215,`
91			`c216,c217,c218,c219,c220,c221,c222,c223,c224,c225,c226,c227,c228,`
92			`c229,c230,c231,c232,c233,c234,c235,c236,c237,c238,c239,c240,c241,`
93			`c242,c243,c244,c245,c246,c247,c248,c249,c250,c251,c252,c253,c254,c255);`
94			`subtype Byte is ByteT;`
95			`type ByteFileType is file of Byte;`
96			`file outfile : ByteFileType open write_mode is "Labels.bin";`
97
98			`begin`
99
100			`ramS : entity work.ram1w2r port map (`
101			`addrefa => Saddrefa,`
102			`addrefb=> Saddrefb,`
103			`doutrefa => Sdoutrefa,`
104			`doutrefb => Sdoutrefb,`
105			`addrW => SaddrW,`
106			`din => Sdin,`
107			`we => Swe,`
108			`addrRA => SaddrRA,`
109			`doutA => SdoutA,`
110			`addrRB => SaddrRB,`
111			`doutB => SdoutB,`
112			`clk => clk);`
113
114			`ramT : entity work.ram1w2r port map (`
115			`addrefa => Taddrefa,`
116			`addrefb=> Taddrefb,`
117			`doutrefa => Tdoutrefa,`
118			`doutrefb => Tdoutrefb,`
119			`addrW => TaddrW,`
120			`din => Tdin,`
121			`we => Twe,`
122			`addrRA => TaddrRA,`
123			`doutA => TdoutA,`
124			`addrRB => TaddrRB,`
125			`doutB => TdoutB,`
126			`clk => clk);`
127
128			`--=============== Multiplexer statements for selecting memories for interlieving of table accesses =======`
129			`--=============== selectSpace is the signal that controls interlieveing per frames =======`
130
131			`---------- Memory inputs -----------------------------`
132			`SaddrRA <= c when selectSpace ='0' else`
133			`PostAddrR;`
134			`SaddrRB <= d when selectSpace = '0' else`
135			`readAddr;`
136			`SaddrW <= SetAddrW when selectSpace='0' else`
137			`PostAddrW when eqready='0' else`
138			`PreAddrW;`
139			`Sdin <= SetDin when selectSpace = '0' else`
140			`PostDin when eqready = '0' else`
141			`PreDin;`
142			`Swe <= SetWe when selectSpace='0' else`
143			`PostWe when eqready = '0' else`
144			`PreWe;`
145			`Saddrefa <= a when selectSpace = '0' ;`
146			`Saddrefb <= b when selectSpace = '0' ;`
147
148			`TaddrRA <= c when selectSpace ='1' else`
149			`PostAddrR;`
150			`TaddrRB <= d when selectSpace = '1' else`
151			`readAddr;`
152			`TaddrW <= SetAddrW when selectSpace='1' else`
153			`PostAddrW when eqready='0' else`
154			`PreAddrW;`
155			`Tdin <= SetDin when selectSpace = '1' else`
156			`PostDin when eqready = '0' else`
157			`PreDin;`
158			`Twe <= SetWe when selectSpace='1' else`
159			`PostWe when eqready = '0' else`
160			`PreWe;`
161			`Taddrefa <= a when selectSpace = '1';`
162			`Taddrefb <= b when selectSpace = '1' ;`
163			`-------------------------------------------------------`
164
165			`---------- Memory outputs ----------------------------`
166
167			`SetDoutA <= SdoutA when selectSpace = '0' else`
168			`TdoutA;`
169			`SetDoutB <= SdoutB when selectSpace = '0' else`
170			`TdoutB;`
171			`PostDout <= SdoutA when selectSpace = '1' else`
172			`TdoutA;`
173			`dout <= SdoutB when selectSpace = '1' else`
174			`TdoutB;`
175			`SetdoutrefA <= Sdoutrefa when selectSpace = '0' else`
176			`Tdoutrefa;`
177			`SetdoutrefB <= Sdoutrefb when selectSpace = '0' else`
178			`Tdoutrefb;`
179
180			`-------------------------------------------------------`
181
182			`--====================== Other signal mappings =========================================================`
183			`tableReady <= eqready;`
184			`space <= selectspace;`
185			`--======================================================================================================`
186
187			`EqualSet : process(clk,reset)`
188
189			`variable contentA, contentB : std_logic_vector(9 downto 0);`
190			`begin`
191			`if reset = '1' then`
192			`Setwe <= '0';`
193			`a_delay1 <= (others=>'0');`
194			`b_delay1 <= (others=>'0');`
195			`tblwrite <= (others=>'0');`
196
197			`elsif clk'event and clk = '1' then`
198
199			`if fsync = '1' then`
200			`-- write(outfile, ByteT'val(0));`
201			`-- write(outfile, ByteT'val(0));`
202			`-- write(outfile, ByteT'val(0));`
203			`end if;`
204
205			`if we = '1' or fsync = '1' then`
206			`if a_delay1 = SetaddrW and Setwe = '1' then`
207			`contentA := Setdin;`
208			`else`
209			`contentA := SetDoutA;`
210			`end if;`
211			`if b_delay1 = SetaddrW and Setwe = '1' then`
212			`contentB := Setdin;`
213			`else`
214			`contentB := SetDoutB;`
215			`end if;`
216
217			`if contentA > contentB and a_delay1/= 0 and b_delay1/= 0 then`
218			`SetaddrW <= contentA; -- Position a_store is overwritten by the smaller label in b_out`
219			`Setdin <= contentB;`
220			`Setwe <= '1';`
221			`tblwrite <= tblwrite + 1;`
222			`-- write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(contentA))));`
223			`-- write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(contentB))));`
224			`--write(outfile, ByteT'val(0));`
225			`elsif contentB > contentA and a_delay1/=0 and b_delay1/= 0 then`
226			`SetaddrW <= contentB; -- Position b_store is overwritten by the smaller label in a_out`
227			`Setdin <= contentA;`
228			`Setwe <= '1';`
229			`tblwrite <= tblwrite + 1;`
230			`-- write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(contentB))));`
231			`-- write(outfile, ByteT'val(ieee.numeric_std.To_Integer(ieee.numeric_std.unsigned(contentA))));`
232			`--write(outfile, ByteT'val(0));`
233			`else`
234			`Setwe <= '0';`
235			`end if;`
236			`else`
237			`Setwe <= '0';`
238			`end if;`
239			`if(fsync = '1' ) then`
240			`a_delay1 <= (others=>'0');`
241			`b_delay1 <= (others=>'0');`
242			`tblwrite <= (others=>'0');`
243			`elsif we = '1' then`
244			`a_delay1 <= c;`
245			`b_delay1 <= d;`
246			`end if;`
247
248			`end if;`
249
250			`end process EqualSet;`
251			`PostProc : process(clk,reset)`
252
253			`variable eqindex,aindex,bindex,equcnt : std_logic_vector(9 downto 0);`
254			`variable incIndex : std_logic := '0';`
255			`variable scount : std_logic_vector(6 downto 0);`
256			`begin`
257			`if reset = '1' then`
258			`spc <= '0';`
259			`selectSpace <= '0';`
260			`eqready <= '1';`
261			`eqindex := (others=>'0');`
262			`PostAddrR <= eqindex;`
263			`PostWe <= '0';`
264			`incIndex := '0';`
265			`equcnt := (others=>'0');`
266			`scount := (others=>'0');`
267
268			`elsif clk'event and clk = '1' then`
269
270			`selectSpace <= spc;`
271
272			`case ppstate is`
273			`when idle=>`
274			`if fsync = '1' then`
275			`ppstate <= startup1;`
276			`PostAddrR <= eqindex;`
277			`eqready <= '0';`
278			`eqindex := (others=>'0');`
279			`spc <= not spc;`
280			`equcnt := (others=>'0');`
281			`scount := (others=>'0');`
282			`end if;`
283			`PostWe <= '0';`
284			`when startup1 =>`
285			`ppstate <= startup2;`
286			`PostAddrR <= eqindex;`
287			`PostWe <= '0';`
288			`when startup2 =>`
289			`scount := (others=>'0');`
290			`ppstate <= indexing;`
291			`PostAddrR <= eqindex;`
292			`PostWe <= '0';`
293			`when indexing =>`
294			`if fsync = '1' then`
295			`ppstate <= startup1;`
296			`PostAddrR <= eqindex;`
297			`eqready <= '0';`
298			`eqindex := (others=>'0');`
299			`spc <= not spc;`
300			`PostWe <= '0';`
301			`elsif eqindex = 1023 then`
302			`ppstate <= idle;`
303			`eqready <= '1';`
304			`PostWe <= '0';`
305			`elsif PostAddrRDelayed /= PostDout and PostDout /= 0 then`
306			`aindex := PostAddrRDelayed;`
307			`bindex := PostDout;`
308			`PostAddrR <= bindex;`
309			`equcnt := equcnt + 1;`
310			`ppstate <= toFindEqual;`
311			`if incIndex = '1' then`
312			`eqindex := eqindex + 1;`
313			`else`
314			`incIndex := '1';`
315			`end if;`
316			`elsif eqindex < 1023 then`
317			`eqindex := eqindex + 1;`
318			`PostAddrR <= eqindex;`
319			`incIndex := '0';`
320			`else`
321			`eqready <= '1';`
322			`equalcnt <= equcnt;`
323			`ppstate <= idle;`
324			`end if;`
325			`PostWe <= '0';`
326			`when toFindEqual =>`
327			`ppstate <= FindEqual;`
328			`PostWe <= '0';`
329			`when findEqual =>`
330			`if fsync = '1' then`
331			`ppstate <= startup1;`
332			`PostAddrR <= eqindex;`
333			`eqready <= '0';`
334			`eqindex := (others=>'0');`
335			`spc <= not spc;`
336			`PostWe <= '0';`
337			`elsif PostAddrRDelayed /= PostDout and PostDout /= 0 and scount < 127 then`
338			`bindex := PostDout;`
339			`PostAddrR <= bindex;`
340			`scount := scount + 1;`
341			`PostWe <= '0';`
342			`else`
343			`PostAddrW <= aindex;`
344			`PostDin <= bindex;`
345			`PostWe <= '1';`
346			`PostAddrR <= eqindex;`
347			`ppstate <= startup2;`
348			`end if;`
349			`when others =>`
350			`ppstate <= idle;`
351			`end case;`
352			`PostAddrRDelayed <= PostAddrR;`
353			`end if;`
354			`end process PostProc;`
355
356
357			`PreSet : process(clk,reset)`
358
359			`variable ind : std_logic_vector(9 downto 0);`
360			`constant maxind : std_logic_vector(9 downto 0):= (others=>'1');`
361			`begin`
362			`if reset='1' then`
363			`ind := maxind;`
364			`PreWe <= '0';`
365			`elsif clk'event and clk='1' then`
366			`if tablePreset = '1' and ind = maxind then`
367			`ind := (others=>'0');`
368			`PreAddrW <= ind;`
369			`PreDin <= ind;`
370			`PreWe <= '1';`
371			`elsif ind < maxind then`
372			`ind := ind + 1;`
373			`PreAddrW <= ind;`
374			`PreDin <= ind;`
375			`PreWe <= '1';`
376			`else`
377			`PreWe <= '0';`
378			`end if;`
379			`end if;`
380			`end process PreSet;`
381
382			`end Struct;`
383