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malikpearl |
library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.std_logic_arith.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity label8AndFeatures is
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generic( CODE_BITS : integer := 10;
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row : natural := 480;
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col : natural := 640);
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port (
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ip9 : in std_logic_vector(CODE_BITS-1 downto 0);
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ip8 : in std_logic_vector(CODE_BITS-1 downto 0);
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ip7 : in std_logic_vector(CODE_BITS-1 downto 0);
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ip6 : in std_logic_vector(CODE_BITS-1 downto 0);
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ibin : in std_logic;
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pdata_in : in std_logic_vector(7 downto 0);
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fsync_in : in std_logic;
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fsync_out : out std_logic;
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pdata_o : out std_logic_vector(CODE_BITS-1 downto 0) := (others => '0');
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rsync_in : in std_logic;
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rsync_out : out std_logic;
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Reset : in std_logic;
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pclk : in std_logic;
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featureDataStrobe : out std_logic;
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acknowledge : in std_logic;
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cntObjects : out std_logic_vector(9 downto 0);
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x_cog : out std_logic_vector(16 downto 0);
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y_cog : out std_logic_vector (16 downto 0)
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);
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end label8AndFeatures;
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architecture struct of label8AndFeatures is
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signal a,b,dout,indexMax,equalcnt : std_logic_vector(9 downto 0):= (others => '0');
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signal readAddr: std_logic_vector(9 downto 0);
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signal tableReady,tablePreset,we,computeDone : std_logic;
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signal hit : std_logic_vector(CODE_BITS-1 downto 0);
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signal selectspace : std_logic := '0';
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signal pdata_osig : std_logic_vector(CODE_BITS-1 downto 0) := (others => '0');
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signal pdata_delayed : std_logic_vector(7 downto 0);
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signal eindex : std_logic_vector(CODE_BITS-1 downto 0);
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signal compuCode : std_logic_vector(9 downto 0);
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signal mergeEnable, compute : std_logic;
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signal refa,refb:std_logic_vector(9 downto 0);
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subtype col_range is natural range 0 to col ;
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subtype row_range is natural range 0 to row + 1;
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begin
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equtbl : entity work.equivalenceTable Port map
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( a => a,
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b => b,
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c => refa,--contents of memory locations are set for merging not just labels
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d => refb,
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we => we,
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readAddr => readAddr,
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dout => dout,
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equalcnt => equalcnt,
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fsync => fsync_in,
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tableReady => tableReady,
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tablePreset => tablePreset,
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space => selectspace,
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reset => Reset,
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clk => pclk,
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SetdoutrefA => refa,
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SetdoutrefB => refb
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);
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MAC : entity work.mac_module
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generic map( ROW=>row, COL=>col,CODE_BITS=>CODE_BITS)
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Port Map
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( code => pdata_osig,
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fsync_in => fsync_in,
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rsync_in => rsync_in,
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Reset => reset,
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pclk => pclk,
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pdata_in => pdata_delayed,
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tablePreset => tablePreset,
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divready_out => computeDone,
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selectspace => selectspace,
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y_cog => y_cog,
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compuCode => compuCode,
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mergeEnable => mergeEnable,
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compute => compute,
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x_cog => x_cog
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);
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Sequencer : entity work.compuSequencer Port map
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( clk => pclk,
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reset => fsync_in,
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tableReady => tableReady,
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computeDone => computeDone,
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featureDataStrobe => featureDataStrobe,
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acknowledge => acknowledge,
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indexMax => indexMax,
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eqData => dout,
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eqAddress => readAddr,
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compuCode => compuCode,
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cntObjects => cntObjects,
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mergeEnable => mergeEnable,
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compute => compute,
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tablePreset => tablePreset
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);
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a <= (others=>'0') when reset= '1' else --check all the conditions for labelling
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ip6 when (ibin = '1' and ip7 /= 0 and ip6 /= 0) else
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ip6 when (ibin = '1' and ip8 /= 0 and ip6 /= 0) else
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ip6 when (ibin = '1' and ip9 /= 0 and ip6 /= 0) else
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ip8 when (ibin = '1' and ip8 /= 0 and ip9 /= 0) else
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ip7 when (ibin = '1' and ip7 /= 0 and ip9 /= 0) else
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ip7 when (ibin = '1' and ip7 /= 0 and ip8 /= 0) else
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ip6 when (ibin = '1' and ip7 /= 0 and ip6 /= 0) else
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ip8 when (ibin = '1' and ip8 /= 0) else
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ip6 when (ibin = '1' and ip6 /= 0)else
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ip9 when (ibin= '1' and ip9 /= 0) else
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ip7 when (ibin= '1' and ip7 /= 0) else
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eindex when ibin='1' else
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(others=> '0');
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b <=(others=>'0') when reset= '1' else
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ip7 when (ibin = '1' and ip7 /= 0 and ip6 /= 0) else
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ip8 when (ibin = '1' and ip8 /= 0 and ip6 /= 0) else
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ip9 when (ibin = '1' and ip9 /= 0 and ip6 /= 0) else
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ip9 when (ibin = '1' and ip8 /= 0 and ip9 /= 0) else
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ip9 when (ibin = '1' and ip7 /= 0 and ip9 /= 0) else
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ip8 when (ibin = '1' and ip7 /= 0 and ip8 /= 0) else
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ip7 when (ibin = '1' and ip7 /= 0 and ip6 /= 0) else
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ip8 when (ibin = '1' and ip8 /= 0) else
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ip6 when (ibin = '1' and ip6 /= 0) else
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ip9 when (ibin= '1' and ip9 /= 0) else
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ip7 when (ibin= '1' and ip7 /= 0) else
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eindex when ibin='1' else
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(others =>'0');
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--eindex <= eindex+1 when (ibin = '1' and ip6 = 0 and ip7 = 0 and ip8=0 and ip9=0) ;
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-- pdata_o <= refa when (refa < refb) and ibin='1' else
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-- refb when ibin ='1' else
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-- (others=>'0');
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we <= '1' when (ip6 /= 0 or ip7 /= 0 or ip8/=0 or ip9/=0) else
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'0';
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label8: process(pclk,Reset)
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-- This process performs 8-connectivity labeling of the binary input video stream on input port ibin
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-- Only the first pass of the labeling process is done. This means that the information stored in the
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-- table of equvivalences must be read in order to identify all pixels belonging
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-- to one single image component. The equvivalences are stored in block-RAMs through the ports of
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-- equtbl : entity work.equivalenceTable. This entity actually contains two tables of equvivalences.
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-- One is written to during the labelling process and the other can be used for post processing when
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-- image component features are calculated.
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begin
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if Reset = '1' then
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eindex <= conv_std_logic_vector(1,CODE_BITS);
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--a <= (others=>'0');
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--b <= (others=>'0');
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hit <= (others=>'0');
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--we <= '0';
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elsif pclk'event and pclk = '1' then
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--we <= '0';
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if (ibin = '1' and ip6 = 0 and ip7 = 0 and ip8=0 and ip9=0) then
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eindex <= eindex+1 ;
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end if;
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if refa < refb and ibin='1' then
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pdata_osig <= refa;
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elsif ibin='1' then
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pdata_osig <= refb;
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else
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pdata_osig <= (others => '0');
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end if;
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if fsync_in = '1' then
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indexMax <= eindex;
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eindex <= conv_std_logic_vector(1,CODE_BITS);
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hit <= (others=>'0');
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end if;
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fsync_out <= fsync_in;
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rsync_out <= rsync_in;
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pdata_delayed <= pdata_in;
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end if;--pclk'event
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end process label8;
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pdata_o <= pdata_osig;
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end struct;
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