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malikpearl |
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity serial_div2 is
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generic ( M_PP : natural := 34; -- Size of dividend
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N_PP : natural := 19; -- Size of divisor
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R_PP : natural := 0; -- Size of remainder
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S_PP : natural := 0; -- Skip this many bits (known leading zeros)
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COUNT_WIDTH_PP : natural := 6; -- 2^COUNT_WIDTH_PP-1 >= (M_PP+R_PP-S_PP-1)
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HELD_OUTPUT_PP : natural := 1 -- Set to 1 if stable output should be held
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); -- from previous operation, during current operation.
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port ( clk_i : in std_logic;
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clk_en_i : in std_logic := '1';
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rst_i : in std_logic := '0';
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divide_i : in std_logic := '1';
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dividend_i : in std_logic_vector(M_PP-1 downto 0) := (others => '0');
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divisor_i : in std_logic_vector(N_PP-1 downto 0) := (others => '0');
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quotient_o : out std_logic_vector(M_PP+R_PP-N_PP+1 downto 0); --17
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done_o : out std_logic
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);
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end serial_div2;
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architecture Behavioral of serial_div2 is
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signal divide_count : std_logic_vector(COUNT_WIDTH_PP-1 downto 0) := (others => '0');
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signal divisor_node : std_logic_vector(M_PP+N_PP-1 downto 0);
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signal quotient_node : std_logic_vector(M_PP-N_PP+R_PP+1 downto 0);
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signal remainder_node : std_logic_vector(M_PP+N_PP-1 downto 0); -- Subtract node has extra "sign" bit
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--signal remainder_node2 : std_logic_vector(M_PP-1 downto 0); -- Subtract node has extra "sign" bit
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--signal msb_indicate : std_logic ;
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begin
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s_div : process(clk_i)
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begin -- s_div
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if(clk_i'event and clk_i='1') then
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if (rst_i = '1') then
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quotient_node <= (others => '0');
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divide_count <= (others => '0');
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divisor_node <= (others => '0');
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remainder_node <= (others => '0');
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-- quotient_o <= (others => '0');
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done_o <= '0';
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-- msb_indicate <= '0';
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else
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if (clk_en_i = '1') then
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if (divide_i = '1') then
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done_o <= '0';
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-- quotient_o <= (others => '0');
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quotient_node <= (others => '0');
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divide_count <= (others => '0');
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divisor_node(M_PP+N_PP-1 downto M_PP) <= divisor_i;
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divisor_node(M_PP-1 downto 0) <= (others => '0');
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remainder_node(M_PP+N_PP-1 downto N_PP) <= dividend_i;
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remainder_node(N_PP-1 downto 0) <= (others => '0');
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-- msb_indicate <= '0';
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elsif (conv_integer(divide_count) = (M_PP-11) ) then --- works with (-11), no explanation right now
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done_o <= '1';
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quotient_o <= quotient_node;
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else
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if (remainder_node > divisor_node) then
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remainder_node <= remainder_node - divisor_node;
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quotient_node <= quotient_node(M_PP+R_PP-N_PP downto 0) & '1';
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else
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quotient_node <= quotient_node(M_PP+R_PP-N_PP downto 0) & '0';
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end if;
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-- final shift... TODO
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divide_count <= divide_count + 1; -- Advance the counter
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divisor_node <= '0' & divisor_node(M_PP +N_PP-1 downto 1);
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end if; -- DIVIDE
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end if; -- clk_en
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end if; -- RST
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end if; -- CLK
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end process s_div;
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-- quotient_o <= quotient_node; -- final shift... TODO
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end Behavioral;
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