Subversion Repositories m65c02

;

; 6 5 0 2   F U N C T I O N A L   T E S T

;

; Copyright (C) 2012-2013  Klaus Dormann

;

; This program is free software: you can redistribute it and/or modify

; it under the terms of the GNU General Public License as published by

; the Free Software Foundation, either version 3 of the License, or

; (at your option) any later version.

;

; This program is distributed in the hope that it will be useful,

; but WITHOUT ANY WARRANTY; without even the implied warranty of

; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

; GNU General Public License for more details.

;

; You should have received a copy of the GNU General Public License

; along with this program.  If not, see .

;

;

; This program is designed to test all opcodes of a 6502 emulator using all

; addressing modes with focus on propper setting of the processor status

; register bits.

;

; version 23-jul-2013

; contact info at http://2m5.de or email K@2m5.de

;

; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/

; command line switches: -l -m -s2 -w -h0

;                         |  |  |   |  no page headers in listing

;                         |  |  |   wide listing (133 char/col)

;                         |  |  write intel hex file instead of binary

;                         |  expand macros in listing

;                         generate pass2 listing

;

; No IO - should be run from a monitor with access to registers.

; To run load intel hex image with a load command, than alter PC to 400 hex

; (code_segment) and enter a go command.

; Loop on program counter determines error or successful completion of test.

; Check listing for relevant traps (jump/branch *).

; Please note that in early tests some instructions will have to be used before

; they are actually tested!

;

; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled.

; Tests documented behavior of the original NMOS 6502 only! No unofficial

; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will

; not be tested. Decimal ops will only be tested with valid BCD operands and

; N V Z flags will be ignored.

;

; Debugging hints:

;     Most of the code is written sequentially. if you hit a trap, check the

;   immediately preceeding code for the instruction to be tested. Results are

;   tested first, flags are checked second by pushing them onto the stack and

;   pulling them to the accumulator after the result was checked. The "real"

;   flags are no longer valid for the tested instruction at this time!

;     If the tested instruction was indexed, the relevant index (X or Y) must

;   also be checked. Opposed to the flags, X and Y registers are still valid.

;

; versions:

;   28-jul-2012  1st version distributed for testing

;   29-jul-2012  fixed references to location 0, now #0

;                added license - GPLv3

;   30-jul-2012  added configuration options

;   01-aug-2012  added trap macro to allow user to change error handling

;   01-dec-2012  fixed trap in branch field must be a branch

;   02-mar-2013  fixed PLA flags not tested

;   19-jul-2013  allowed ROM vectors to be loaded when load_data_direct = 0

;                added test sequence check to detect if tests jump their fence

;   23-jul-2013  added RAM integrity check

;

;   30-Aug-2013  Modified by Michael A. Morris to allow selection of tests

;   04-Jan-2014  Modified trap vectors to use sbc2oslite BRK handler for error

;                trapping. Enabled success macro, which returns to the monitor.

;                Disabled BRK trap test in order to trap out to the monitor.

;   30-Jan-2014  Modified success macro to issue brk instruction instead of rts.

;   27-Nov-2014  Modified success macro to use stp instruction instead of brk

;   07-Dec-2014  Modified success macro to use brk instruction instead of stp

;

; C O N F I G U R A T I O N

;

;ROM_vectors writable (0=no, 1=yes)

;

;   if ROM vectors can not be used interrupts will not be trapped

;   as a consequence BRK can not be tested but will be emulated to test RTI

;

ROM_vectors = 0

;

;load_data_direct (0=move from code segment, 1=load directly)

;loading directly is preferred but may not be supported by your platform

;0 produces only consecutive object code, 1 is not suitable for a binary image

;

load_data_direct = 0

;

;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow

;change) 2 requires extra code and is not recommended. SEI & CLI can only be

;tested if you allow changing the interrupt status (I_flag = 3)

;

I_flag = 3

;

;configure memory - try to stay away from memory used by the system

;zero_page memory start address, $50 (80) consecutive Bytes required

;                                add 2 if I_flag = 2

;

zero_page = $B0

;

;data_segment memory start address, $5B (91) consecutive Bytes required

;

data_segment = $200

    if (data_segment & $ff) != 0

        ERROR ERROR ERROR low byte of data_segment MUST be $00 !!

    endif

;

;code_segment memory start address, 13kB of consecutive space required

;                                   add 2.5 kB if I_flag = 2

;parts of the code are self modifying and must reside in RAM

;

code_segment = $400

;

;RAM integrity test option. Checks for undesired RAM writes.

;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k)

;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM

;

ram_top = -1

;ram_top = $40

;

;   Define the top of stack location

;

stack_top = $1FF

;

;Skip to ADC/SBC tests

;

skip_part_1  = 0

;

;Skip Binary or Decimal mode ADC/SBC instruction tests

;

skip_bin_test = 0

skip_dec_test = 0

;

        noopt       ;do not take shortcuts

;

;macros for error & success traps to allow user modification

;example:

;

;trap    macro

;        jsr my_error_handler

;        endm

;

;trap_eq macro

;        bne skip\?

;        trap           ;failed equal (zero)

;skip\?

;        endm

;

; my_error_handler should pop the calling address from the stack and report it.

; putting larger portions of code (more than 3 bytes) inside the trap macro

; may lead to branch range problems for some tests.

trap    macro

;        db      $db         ; M65C02/M65C02A SToP instruction

        brk                 ; Use BRK to return to the monitor

        db      test_num

        endm

trap_eq macro

        bne skip\?

        trap           ;failed equal (zero)

skip\?

        endm

trap_ne macro

        beq skip\?

        trap           ;failed equal (zero)

skip\?

        endm

trap_cs macro

        bcc skip\?

        trap           ;failed equal (zero)

skip\?

        endm

trap_cc macro

        bcs skip\?

        trap           ;failed equal (zero)

skip\?

        endm

trap_mi macro

        bpl skip\?

        trap           ;failed equal (zero)

skip\?

        endm

trap_pl macro

        bmi skip\?

        trap           ;failed equal (zero)

skip\?

        endm

trap_vs macro

        bvc skip\?

        trap           ;failed equal (zero)

skip\?

        endm

trap_vc macro

        bvs skip\?

        trap           ;failed equal (zero)

skip\?

        endm

success macro

        brk

        db      test_num+1

        endm

carry   equ %00000001   ;flag bits in status

zero    equ %00000010

intdis  equ %00000100

decmode equ %00001000

break   equ %00010000

reserv  equ %00100000

overfl  equ %01000000

minus   equ %10000000

fc      equ carry

fz      equ zero

fzc     equ carry+zero

fv      equ overfl

fvz     equ overfl+zero

fn      equ minus

fnc     equ minus+carry

fnz     equ minus+zero

fnzc    equ minus+zero+carry

fnv     equ minus+overfl

fao     equ break+reserv    ;bits always on after PHP, BRK

fai     equ fao+intdis      ;+ forced interrupt disable

m8      equ $ff             ;8 bit mask

m8i     equ $ff&~intdis     ;8 bit mask - interrupt disable

;macros to allow masking of status bits.

;masking of interrupt enable/disable on load and compare

;masking of always on bits after PHP or BRK (unused & break) on compare

        if I_flag = 0

load_flag   macro

            lda #\1&m8i         ;force enable interrupts (mask I)

            endm

cmp_flag    macro

            cmp #(\1|fao)&m8i   ;I_flag is always enabled + always on bits

            endm

eor_flag    macro

            eor #(\1&m8i|fao)   ;mask I, invert expected flags + always on bits

            endm

        endif

        if I_flag = 1

load_flag   macro

            lda #\1|intdis      ;force disable interrupts

            endm

cmp_flag    macro

            cmp #(\1|fai)&m8    ;I_flag is always disabled + always on bits

            endm

eor_flag    macro

            eor #(\1|fai)       ;invert expected flags + always on bits + I

            endm

        endif

        if I_flag = 2

load_flag   macro

            lda #\1

            ora flag_I_on       ;restore I-flag

            and flag_I_off

            endm

cmp_flag    macro

            eor flag_I_on       ;I_flag is never changed

            cmp #(\1|fao)&m8i   ;expected flags + always on bits, mask I

            endm

eor_flag    macro

            eor flag_I_on       ;I_flag is never changed

            eor #(\1&m8i|fao)   ;mask I, invert expected flags + always on bits

            endm

        endif

        if I_flag = 3

load_flag   macro

            lda #\1             ;allow test to change I-flag (no mask)

            endm

cmp_flag    macro

            cmp #(\1|fao)&m8    ;expected flags + always on bits

            endm

eor_flag    macro

            eor #\1|fao         ;invert expected flags + always on bits

            endm

        endif

;macros to set (register|memory|zeropage) & status

set_stat    macro       ;setting flags in the processor status register

            load_flag \1

            pha         ;use stack to load status

            plp

            endm

set_a       macro       ;precharging accu & status

            load_flag \2

            pha         ;use stack to load status

            lda #\1     ;precharge accu

            plp

            endm

set_x       macro       ;precharging index & status

            load_flag \2

            pha         ;use stack to load status

            ldx #\1     ;precharge index x

            plp

            endm

set_y       macro       ;precharging index & status

            load_flag \2

            pha         ;use stack to load status

            ldy #\1     ;precharge index y

            plp

            endm

set_ax      macro       ;precharging indexed accu & immediate status

            load_flag \2

            pha         ;use stack to load status

            lda \1,x    ;precharge accu

            plp

            endm

set_ay      macro       ;precharging indexed accu & immediate status

            load_flag \2

            pha         ;use stack to load status

            lda \1,y    ;precharge accu

            plp

            endm

set_z       macro       ;precharging indexed zp & immediate status

            load_flag \2

            pha         ;use stack to load status

            lda \1,x    ;load to zeropage

            sta zpt

            plp

            endm

set_zx      macro       ;precharging zp,x & immediate status

            load_flag \2

            pha         ;use stack to load status

            lda \1,x    ;load to indexed zeropage

            sta zpt,x

            plp

            endm

set_abs     macro       ;precharging indexed memory & immediate status

            load_flag \2

            pha         ;use stack to load status

            lda \1,x    ;load to memory

            sta abst

            plp

            endm

set_absx    macro       ;precharging abs,x & immediate status

            load_flag \2

            pha         ;use stack to load status

            lda \1,x    ;load to indexed memory

            sta abst,x

            plp

            endm

;macros to test (register|memory|zeropage) & status & (mask)

tst_stat    macro       ;testing flags in the processor status register

            php         ;save status

            php         ;use stack to retrieve status

            pla

            cmp_flag \1

            trap_ne

            plp         ;restore status

            endm

tst_a       macro       ;testing result in accu & flags

            php         ;save flags

            php

            cmp #\1     ;test result

            trap_ne

            pla         ;load status

            cmp_flag \2

            trap_ne

            plp         ;restore status

            endm

tst_x       macro       ;testing result in x index & flags

            php         ;save flags

            php

            cpx #\1     ;test result

            trap_ne

            pla         ;load status

            cmp_flag \2

            trap_ne

            plp         ;restore status

            endm

tst_y       macro       ;testing result in y index & flags

            php         ;save flags

            php

            cpy #\1     ;test result

            trap_ne

            pla         ;load status

            cmp_flag \2

            trap_ne

            plp         ;restore status

            endm

tst_ax      macro       ;indexed testing result in accu & flags

            php         ;save flags

            cmp \1,x    ;test result

            trap_ne

            pla         ;load status

            eor_flag \3

            cmp \2,x    ;test flags

            trap_ne     ;

            endm

tst_ay      macro       ;indexed testing result in accu & flags

            php         ;save flags

            cmp \1,y    ;test result

            trap_ne     ;

            pla         ;load status

            eor_flag \3

            cmp \2,y    ;test flags

            trap_ne

            endm

tst_z       macro       ;indexed testing result in zp & flags

            php         ;save flags

            lda zpt

            cmp \1,x    ;test result

            trap_ne

            pla         ;load status

            eor_flag \3

            cmp \2,x    ;test flags

            trap_ne

            endm

tst_zx      macro       ;testing result in zp,x & flags

            php         ;save flags

            lda zpt,x

            cmp \1,x    ;test result

            trap_ne

            pla         ;load status

            eor_flag \3

            cmp \2,x    ;test flags

            trap_ne

            endm

tst_abs     macro       ;indexed testing result in memory & flags

            php         ;save flags

            lda abst

            cmp \1,x    ;test result

            trap_ne

            pla         ;load status

            eor_flag \3

            cmp \2,x    ;test flags

            trap_ne

            endm

tst_absx    macro       ;testing result in abs,x & flags

            php         ;save flags

            lda abst,x

            cmp \1,x    ;test result

            trap_ne

            pla         ;load status

            eor_flag \3

            cmp \2,x    ;test flags

            trap_ne

            endm

; RAM integrity test

;   verifies that none of the previous tests has altered RAM outside of the

;   designated write areas.

;   uses zpt word as indirect pointer, zpt+2 word as checksum

        if ram_top > -1

check_ram   macro

            cld

            lda #0

            sta zpt         ;set low byte of indirect pointer

            sta zpt+3       ;checksum high byte

            sta range_adr   ;reset self modifying code

            sta tandi1

            sta tandi2

            sta teori1

            sta teori2

            sta torai1

            sta torai2

            sta chkdadi

            sta chkdsbi

            sta chkadi

            sta chksbi

            clc

            ldx #zp_bss-zero_page ;zeropage - write test area

ccs3\?      adc zero_page,x

            bcc ccs2\?

            inc zpt+3       ;carry to high byte

            clc

ccs2\?      inx

            bne ccs3\?

            ldx #hi(data_segment) ;set high byte of indirect pointer

            stx zpt+1

            ldy #lo(data_bss) ;data after write test area

ccs5\?      adc (zpt),y

            bcc ccs4\?

            inc zpt+3       ;carry to high byte

            clc

ccs4\?      iny

            bne ccs5\?

            inx             ;advance RAM high address

            stx zpt+1

            cpx #ram_top

            bne ccs5\?

            sta zpt+2       ;checksum low is

            cmp ram_chksm   ;checksum low expected

            trap_ne         ;checksum mismatch

            lda zpt+3       ;checksum high is

            cmp ram_chksm+1 ;checksum high expected

            trap_ne         ;checksum mismatch

            endm

        else

check_ram   macro

            ;RAM check disabled - RAM size not set

            endm

        endif

next_test   macro           ;make sure, tests don't jump the fence

            lda test_case   ;previous test

            cmp #test_num

            trap_ne         ;test is out of sequence

test_num = test_num + 1

            lda #test_num   ;*** this tests' number

            sta test_case

            ;check_ram       ;uncomment to find altered RAM after each test

            endm

    if load_data_direct = 1

        data

    else

;        bss                 ;uninitialized segment, copy of data at end of code!

        code

        org 0

        ds  zero_page

    endif

;

        org zero_page

;

;        org 0

;        ds  zero_page

;

;break test interrupt save

;

irq_a   ds  1               ;a register

irq_x   ds  1               ;x register

    if I_flag = 2

;masking for I bit in status

flag_I_on   ds  1           ;or mask to load flags

flag_I_off  ds  1           ;and mask to load flags

    endif

zpt                         ;5 bytes store/modify test area

;add/subtract operand generation and result/flag prediction

adfc    ds  1               ;carry flag before op

ad1     ds  1               ;operand 1 - accumulator

ad2     ds  1               ;operand 2 - memory / immediate

adrl    ds  1               ;expected result bits 0-7

adrh    ds  1               ;expected result bit 8 (carry)

adrf    ds  1               ;expected flags NV0000ZC (-V in decimal mode)

sb2     ds  1               ;operand 2 complemented for subtract

zp_bss

zp1     db  $c3,$82,$41,0   ;test patterns for LDx BIT ROL ROR ASL LSR

zp7f    db  $7f             ;test pattern for compare

;logical zeropage operands

zpOR    db  0,$1f,$71,$80   ;test pattern for OR

zpAN    db  $0f,$ff,$7f,$80 ;test pattern for AND

zpEO    db  $ff,$0f,$8f,$8f ;test pattern for EOR

;indirect addressing pointers

ind1    dw  abs1            ;indirect pointer to pattern in absolute memory

        dw  abs1+1

        dw  abs1+2

        dw  abs1+3

        dw  abs7f

inw1    dw  abs1-$f8        ;indirect pointer for wrap-test pattern

indt    dw  abst            ;indirect pointer to store area in absolute memory

        dw  abst+1

        dw  abst+2

        dw  abst+3

inwt    dw  abst-$f8        ;indirect pointer for wrap-test store

indAN   dw  absAN           ;indirect pointer to AND pattern in absolute memory

        dw  absAN+1

        dw  absAN+2

        dw  absAN+3

indEO   dw  absEO           ;indirect pointer to EOR pattern in absolute memory

        dw  absEO+1

        dw  absEO+2

        dw  absEO+3

indOR   dw  absOR           ;indirect pointer to OR pattern in absolute memory

        dw  absOR+1

        dw  absOR+2

        dw  absOR+3

;add/subtract indirect pointers

adi2    dw  ada2            ;indirect pointer to operand 2 in absolute memory

sbi2    dw  sba2            ;indirect pointer to complemented operand 2 (SBC)

adiy2   dw  ada2-$ff        ;with offset for indirect indexed

sbiy2   dw  sba2-$ff

zp_bss_end

        org data_segment

test_case   ds  1           ;current test number

ram_chksm   ds  2           ;checksum for RAM integrity test

;add/subtract operand copy - abs tests write area

abst                        ;5 bytes store/modify test area

ada2    ds  1               ;operand 2

sba2    ds  1               ;operand 2 complemented for subtract

        ds  3               ;fill remaining bytes

data_bss

abs1    db  $c3,$82,$41,0   ;test patterns for LDx BIT ROL ROR ASL LSR

abs7f   db  $7f             ;test pattern for compare

;loads

fLDx    db  fn,fn,0,fz      ;expected flags for load

;shifts

rASL                        ;expected result ASL & ROL -carry

rROL    db  $86,$04,$82,0   ; "

rROLc   db  $87,$05,$83,1   ;expected result ROL +carry

rLSR                        ;expected result LSR & ROR -carry

rROR    db  $61,$41,$20,0   ; "

rRORc   db  $e1,$c1,$a0,$80 ;expected result ROR +carry

fASL                        ;expected flags for shifts

fROL    db  fnc,fc,fn,fz    ;no carry in

fROLc   db  fnc,fc,fn,0     ;carry in

fLSR

fROR    db  fc,0,fc,fz      ;no carry in

fRORc   db  fnc,fn,fnc,fn   ;carry in

;increments (decrements)

rINC    db  $7f,$80,$ff,0,1 ;expected result for INC/DEC

fINC    db  0,fn,fn,fz,0    ;expected flags for INC/DEC

;logical memory operand

absOR   db  0,$1f,$71,$80   ;test pattern for OR

absAN   db  $0f,$ff,$7f,$80 ;test pattern for AND

absEO   db  $ff,$0f,$8f,$8f ;test pattern for EOR

;logical accu operand

absORa  db  0,$f1,$1f,0     ;test pattern for OR

absANa  db  $f0,$ff,$ff,$ff ;test pattern for AND

absEOa  db  $ff,$f0,$f0,$0f ;test pattern for EOR

;logical results

absrlo  db  0,$ff,$7f,$80

absflo  db  fz,fn,0,fn

data_bss_end

        code

        org code_segment

start   cld

        lda #0          ;*** test 0 = initialize

        sta test_case

test_num = 0

;stop interrupts before initializing BSS

    if I_flag = 1

        sei

    endif

;initialize BSS segment

    if load_data_direct != 1

        ldx #zp_end-zp_init-1

ld_zp   lda zp_init,x

        sta zp_bss,x

        dex

        bpl ld_zp

        ldx #data_end-data_init-1

ld_data lda data_init,x

        sta data_bss,x

        dex

        bpl ld_data

      if ROM_vectors = 1

        ldx #5

ld_vect lda vec_init,x

        sta vec_bss,x

        dex

        bpl ld_vect

      endif

    endif

;retain status of interrupt flag

    if I_flag = 2

        php

        pla

        and #4          ;isolate flag

        sta flag_I_on   ;or mask

        eor #lo(~4)     ;reverse

        sta flag_I_off  ;and mask

    endif

;generate checksum for RAM integrity test

    if ram_top > -1

        lda #0

        sta zpt         ;set low byte of indirect pointer

        sta ram_chksm+1 ;checksum high byte

        sta range_adr   ;reset self modifying code

        sta tandi1

        sta tandi2

        sta teori1

        sta teori2

        sta torai1

        sta torai2

        sta chkdadi

        sta chkdsbi

        sta chkadi

        sta chksbi

        clc

        ldx #zp_bss-zero_page ;zeropage - write test area

gcs3    adc zero_page,x

        bcc gcs2

        inc ram_chksm+1 ;carry to high byte

        clc

gcs2    inx

        bne gcs3

        ldx #hi(data_segment) ;set high byte of indirect pointer

        stx zpt+1

        ldy #lo(data_bss) ;data after write test area

gcs5    adc (zpt),y

        bcc gcs4

        inc ram_chksm+1 ;carry to high byte

        clc

gcs4    iny

        bne gcs5

        inx             ;advance RAM high address

        stx zpt+1

        cpx #ram_top

        bne gcs5

        sta ram_chksm   ;checksum complete

    endif

    if skip_part_1 = 1

        jmp  bin_test

    endif

        next_test

;testing relative addressing with BEQ

        ldy #$fe        ;testing maximum range, not -1/-2 (invalid/self adr)

range_loop

        dey             ;next relative address

        tya

        tax             ;precharge count to end of loop

        bpl range_fw    ;calculate relative address

        clc             ;avoid branch self or to relative address of branch

        adc #2

range_fw

        eor #$7f        ;complement except sign

        sta range_adr   ;load into test target

        lda #0          ;should set zero flag in status register

        jmp range_op

        ;relative address target field with branch under test in the middle

        dex             ;-128 - max backward

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex             ;-120

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex             ;-110

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex             ;-100

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex             ;-90

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex             ;-80

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex

        dex             ;-70

        dex

        dex

        dex

        dex

        dex

        dex