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`timescale 1ns / 1ps
`default_nettype none
////////////////////////////////////////////////////////////////////////
// 
// 4004 Instruction Decoder
// 
// This file is part of the MCS-4 project hosted at OpenCores:
//      http://www.opencores.org/cores/mcs-4/
// 
// Copyright � 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
// 
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
// 
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
 
module instruction_decode(
        input  wire                     sysclk,                                 // 50 MHz FPGA clock
 
        // Inputs from the Timing and I/O board
        input  wire                     clk1,
        input  wire                     clk2,
        input  wire                     a22,
        input  wire                     m12,
        input  wire                     m22,
        input  wire                     x12,
        input  wire                     x22,
        input  wire                     x32,
        input  wire                     poc,                                    // Power-On Clear (reset)
        input  wire                     n0432,                                  // Conditioned TEST_PAD
 
        // Common 4-bit data bus
        inout  wire     [3:0]    data,
 
        // These drive the Instruction Pointer (IP) board
        output wire                     jcn_isz,                                // JCN+ISZ
        output wire                     jin_fin,                                // JIN+FIN
        output wire                     jun_jms,                                // JUN+JMS
        output wire                     cn_n,                                   // ~CN
        output wire                     bbl,                                    // BBL
        output wire                     jms,                                    // JMS
 
        // Outputs to both the IP and SP boards
        output wire                     sc,                                             // SC (Single Cycle)
        output wire                     dc,                                             // DC (Double Cycle, ~SC)
 
        // Outputs to the Scratch Pad (SP) board
        output wire                     n0636,                                  // JIN+FIN
        output wire                     sc_m22_clk2,                    // SC&M22&CLK2 
        output wire                     fin_fim_src_jin,                // FIN+FIM+SRC+JIN
        output wire                     inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
        output wire                     inc_isz_xch,                    // INC+ISZ+XCH
        output wire                     opa0_n,                                 // ~OPA.0
 
        // Inputs from the ALU board (condition bits)
        input  wire                     acc_0,                                  // ACC_0
        input  wire                     add_0,                                  // ADD_0
        input  wire                     cy_1,                                   // CY_1
 
        // Outputs to the Arithmetic Logic Unit (ALU) board
        output wire                     cma,
        output wire                     write_acc_1,
        output wire                     write_carry_2,
        output wire                     read_acc_3,
        output wire                     add_group_4,
        output wire                     inc_group_5,
        output wire                     sub_group_6,
        output wire                     ior,
        output wire                     iow,
        output wire                     ral,
        output wire                     rar,
        output wire                     ope_n,
        output wire                     daa,
        output wire                     dcl,
        output wire                     inc_isz,
        output wire                     kbp,
        output wire                     o_ib,
        output wire                     tcs,
        output wire                     xch,
        output wire                     n0342,
        output wire                     x21_clk2,
        output wire                     x31_clk2,
        output wire                     com_n
        );
 
        wire    sc_m12_clk2 = sc & m12 & clk2;
        assign  sc_m22_clk2 = sc & m22 & clk2;
 
        // Latch the first 4 bits of the opcode
        reg [3:0] opr = 4'b0000;
        always @(posedge sysclk) begin
                if (sc_m12_clk2)
                        opr <= data;
        end
 
        // Latch the second 4 bits of the opcode
        reg [3:0] opa = 4'b0000;
        always @(posedge sysclk) begin
                if (sc_m22_clk2)
                        opa <= data;
        end
        assign opa0_n = ~opa[0];
 
        // Full OPR Decoding
        wire    nop             = (opr == 4'b0000);
        wire    jcn             = (opr == 4'b0001);
        wire    fim_src = (opr == 4'b0010);
        assign  jin_fin = (opr == 4'b0011);
        wire    jun             = (opr == 4'b0100);
        assign  jms             = (opr == 4'b0101);
        wire    inc             = (opr == 4'b0110);
        wire    isz             = (opr == 4'b0111);
        wire    add             = (opr == 4'b1000);
        wire    sub             = (opr == 4'b1001);
        wire    ld              = (opr == 4'b1010);
        assign  xch             = (opr == 4'b1011);
        assign  bbl             = (opr == 4'b1100);
        wire    ldm             = (opr == 4'b1101);
        wire    io              = (opr == 4'b1110);
        wire    ope             = (opr == 4'b1111);
 
        assign  ope_n   = ~ope;
        assign  n0636   = jin_fin;
        assign  jcn_isz = jcn | isz;
        assign  jun_jms = jun | jms;
        wire    ldm_bbl = ldm | bbl;
        assign  inc_isz = (inc | isz) & sc;
        assign  inc_isz_xch = inc | isz | xch;
        assign  inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
        assign  fin_fim_src_jin = fim_src | jin_fin;
 
        // OPE: OPA Decoding
        assign  o_ib    = ope & (opa[3] == 1'b0);
        wire    clb             = ope & (opa == 4'b0000);
        wire    clc             = ope & (opa == 4'b0001);
        wire    iac             = ope & (opa == 4'b0010);
        wire    cmc             = ope & (opa == 4'b0011);
        assign  cma             = ope & (opa == 4'b0100);
        assign  ral             = ope & (opa == 4'b0101);
        assign  rar             = ope & (opa == 4'b0110);
        wire    tcc             = ope & (opa == 4'b0111);
 
        wire    dac             = ope & (opa == 4'b1000);
        assign  tcs             = ope & (opa == 4'b1001);
        wire    stc             = ope & (opa == 4'b1010);
        assign  daa             = ope & (opa == 4'b1011);
        assign  kbp             = ope & (opa == 4'b1100);
        assign  dcl             = ope & (opa == 4'b1101);
 
        // IO: OPA Decoding
        assign  iow             = io & (opa[3] == 1'b0);
        assign  ior             = io & (opa[3] == 1'b1);
        wire    adm             = io & (opa == 4'b1011);
        wire    sbm             = io & (opa == 4'b1000);
 
        wire    fin_fim = fin_fim_src_jin & ~opa[0];
        wire    src             = fim_src & opa[0];
 
        assign  write_acc_1             = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
                                                                clb | ior | ld  | sub | add | ldm_bbl);
        assign  write_carry_2   = ~(tcs | poc | tcc | stc | cmc | dac | iac |
                                                                clc | clb | sbm | adm | sub | add);
        assign  read_acc_3              = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
        assign  add_group_4             = ~(tcs | tcc | adm | add);
        assign  inc_group_5             = ~(inc_isz | stc | iac);
        assign  sub_group_6             = ~(cmc | sbm | sub | m12);
 
        // The Condition Flip-Flop
        reg  n0397;
        wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
        wire n0419 = ~((add_0 | ~isz) & (~jcn | ((n0486 | opa[3]) & (~n0486 | ~opa[3]))));
        wire n0413 = ~((sc & n0419 & x32) | (~x32 & n0397));
        reg  n0405;
        always @(posedge sysclk) begin
                if (clk2)
                        n0405 <= n0413;
        end
        always @(posedge sysclk) begin
                if (clk1)
                        n0397 <= ~n0405;
        end
        assign cn_n = ~n0397;
 
        // The Single-Cycle Flip-Flop
        reg  n0343 = 1'b0;
        wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
        reg  n0362 = 1'b1;
        always @(posedge sysclk) begin
                if (clk2)
                        n0362 <= n0368;
                if (clk1)
                        n0343 <= ~n0362;
        end
        assign sc = ~n0343;
        assign dc = ~sc;
 
        // Generate ~(X21&~CLK2)
        reg n0360;
        always @(posedge sysclk) begin
                if (clk2)
                        n0360 <= ~x12;
        end
        wire n0337 = ~(n0360 | clk2);
        assign x21_clk2 = ~n0337;
 
        // Generate ~(X31&~CLK2)
        reg n0380;
        always @(posedge sysclk) begin
                if (clk2)
                        n0380 <= ~x22;
        end
        wire n0375 = ~(n0380 | clk2);
        assign x31_clk2 = ~n0375;
 
        // Generate ~COM
        wire n0329 = io;
 
        reg n0414, n0797;
        always @(posedge sysclk) begin
                if (clk2)
                        n0414 <= a22;
                else
                        n0797 <= n0414;
        end
 
        reg n0433, n0801;
        always @(posedge sysclk) begin
                if (clk2)
                        n0433 <= m12;
                else
                        n0801 <= n0433;
        end
 
        reg n0425, n0805;
        always @(posedge sysclk) begin
                if (clk2)
                        n0425 <= x12;
                else
                        n0805 <= n0425;
        end
 
        wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
        assign com_n = n0782;
 
        // Generate N0342
        wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
        assign n0342 = n0332;
 
        // Output OPA onto the data bus
        wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
        assign data = opa_ib ? opa : 4'bzzzz;
 
endmodule

Line No.	Rev	Author	Line
1	2	rrpollack	`timescale 1ns / 1ps
2			`default_nettype none
3			`////////////////////////////////////////////////////////////////////////`
4			`//`
5			`// 4004 Instruction Decoder`
6			`//`
7			`// This file is part of the MCS-4 project hosted at OpenCores:`
8			`// http://www.opencores.org/cores/mcs-4/`
9			`//`
10	4	rrpollack	`// Copyright � 2012, 2020 by Reece Pollack <rrpollack@opencores.org>`
11	2	rrpollack	`//`
12			`// These materials are provided under the Creative Commons`
13			`// "Attribution-NonCommercial-ShareAlike" Public License. They`
14			`// are NOT "public domain" and are protected by copyright.`
15			`//`
16			`// This work based on materials provided by Intel Corporation and`
17			`// others under the same license. See the file doc/License for`
18			`// details of this license.`
19			`//`
20			`////////////////////////////////////////////////////////////////////////`
21
22			`module instruction_decode(`
23			`input wire sysclk, // 50 MHz FPGA clock`
24
25			`// Inputs from the Timing and I/O board`
26			`input wire clk1,`
27			`input wire clk2,`
28			`input wire a22,`
29			`input wire m12,`
30			`input wire m22,`
31			`input wire x12,`
32			`input wire x22,`
33			`input wire x32,`
34			`input wire poc, // Power-On Clear (reset)`
35			`input wire n0432, // Conditioned TEST_PAD`
36
37			`// Common 4-bit data bus`
38			`inout wire [3:0] data,`
39
40			`// These drive the Instruction Pointer (IP) board`
41			`output wire jcn_isz, // JCN+ISZ`
42			`output wire jin_fin, // JIN+FIN`
43			`output wire jun_jms, // JUN+JMS`
44			`output wire cn_n, // ~CN`
45			`output wire bbl, // BBL`
46			`output wire jms, // JMS`
47
48			`// Outputs to both the IP and SP boards`
49			`output wire sc, // SC (Single Cycle)`
50			`output wire dc, // DC (Double Cycle, ~SC)`
51
52			`// Outputs to the Scratch Pad (SP) board`
53	4	rrpollack	`output wire n0636, // JIN+FIN`
54	2	rrpollack	`output wire sc_m22_clk2, // SC&M22&CLK2`
55			`output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN`
56			`output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD`
57			`output wire inc_isz_xch, // INC+ISZ+XCH`
58			`output wire opa0_n, // ~OPA.0`
59
60			`// Inputs from the ALU board (condition bits)`
61			`input wire acc_0, // ACC_0`
62			`input wire add_0, // ADD_0`
63			`input wire cy_1, // CY_1`
64
65			`// Outputs to the Arithmetic Logic Unit (ALU) board`
66			`output wire cma,`
67			`output wire write_acc_1,`
68			`output wire write_carry_2,`
69			`output wire read_acc_3,`
70			`output wire add_group_4,`
71			`output wire inc_group_5,`
72			`output wire sub_group_6,`
73			`output wire ior,`
74			`output wire iow,`
75			`output wire ral,`
76			`output wire rar,`
77			`output wire ope_n,`
78			`output wire daa,`
79			`output wire dcl,`
80			`output wire inc_isz,`
81			`output wire kbp,`
82			`output wire o_ib,`
83			`output wire tcs,`
84			`output wire xch,`
85			`output wire n0342,`
86			`output wire x21_clk2,`
87			`output wire x31_clk2,`
88			`output wire com_n`
89			`);`
90
91			`wire sc_m12_clk2 = sc & m12 & clk2;`
92			`assign sc_m22_clk2 = sc & m22 & clk2;`
93
94			`// Latch the first 4 bits of the opcode`
95			`reg [3:0] opr = 4'b0000;`
96			`always @(posedge sysclk) begin`
97			`if (sc_m12_clk2)`
98			`opr <= data;`
99			`end`
100
101			`// Latch the second 4 bits of the opcode`
102			`reg [3:0] opa = 4'b0000;`
103			`always @(posedge sysclk) begin`
104			`if (sc_m22_clk2)`
105			`opa <= data;`
106			`end`
107			`assign opa0_n = ~opa[0];`
108
109			`// Full OPR Decoding`
110			`wire nop = (opr == 4'b0000);`
111			`wire jcn = (opr == 4'b0001);`
112			`wire fim_src = (opr == 4'b0010);`
113			`assign jin_fin = (opr == 4'b0011);`
114			`wire jun = (opr == 4'b0100);`
115			`assign jms = (opr == 4'b0101);`
116			`wire inc = (opr == 4'b0110);`
117			`wire isz = (opr == 4'b0111);`
118			`wire add = (opr == 4'b1000);`
119			`wire sub = (opr == 4'b1001);`
120			`wire ld = (opr == 4'b1010);`
121			`assign xch = (opr == 4'b1011);`
122			`assign bbl = (opr == 4'b1100);`
123			`wire ldm = (opr == 4'b1101);`
124			`wire io = (opr == 4'b1110);`
125			`wire ope = (opr == 4'b1111);`
126
127			`assign ope_n = ~ope;`
128	4	rrpollack	`assign n0636 = jin_fin;`
129	2	rrpollack	`assign jcn_isz = jcn \| isz;`
130			`assign jun_jms = jun \| jms;`
131			`wire ldm_bbl = ldm \| bbl;`
132			`assign inc_isz = (inc \| isz) & sc;`
133			`assign inc_isz_xch = inc \| isz \| xch;`
134			`assign inc_isz_add_sub_xch_ld = inc \| isz \| add \| sub \| xch \| ld;`
135			`assign fin_fim_src_jin = fim_src \| jin_fin;`
136
137			`// OPE: OPA Decoding`
138			`assign o_ib = ope & (opa[3] == 1'b0);`
139			`wire clb = ope & (opa == 4'b0000);`
140			`wire clc = ope & (opa == 4'b0001);`
141			`wire iac = ope & (opa == 4'b0010);`
142			`wire cmc = ope & (opa == 4'b0011);`
143			`assign cma = ope & (opa == 4'b0100);`
144			`assign ral = ope & (opa == 4'b0101);`
145			`assign rar = ope & (opa == 4'b0110);`
146			`wire tcc = ope & (opa == 4'b0111);`
147
148			`wire dac = ope & (opa == 4'b1000);`
149			`assign tcs = ope & (opa == 4'b1001);`
150			`wire stc = ope & (opa == 4'b1010);`
151			`assign daa = ope & (opa == 4'b1011);`
152			`assign kbp = ope & (opa == 4'b1100);`
153			`assign dcl = ope & (opa == 4'b1101);`
154
155			`// IO: OPA Decoding`
156			`assign iow = io & (opa[3] == 1'b0);`
157			`assign ior = io & (opa[3] == 1'b1);`
158			`wire adm = io & (opa == 4'b1011);`
159			`wire sbm = io & (opa == 4'b1000);`
160
161			`wire fin_fim = fin_fim_src_jin & ~opa[0];`
162			`wire src = fim_src & opa[0];`
163
164			`assign write_acc_1 = ~(kbp \| tcs \| daa \| xch \| poc \| cma \| tcc \| dac \| iac \|`
165			`clb \| ior \| ld \| sub \| add \| ldm_bbl);`
166			`assign write_carry_2 = ~(tcs \| poc \| tcc \| stc \| cmc \| dac \| iac \|`
167			`clc \| clb \| sbm \| adm \| sub \| add);`
168			`assign read_acc_3 = ~(daa \| rar \| ral \| dac \| iac \| sbm \| adm \| sub \| add);`
169			`assign add_group_4 = ~(tcs \| tcc \| adm \| add);`
170			`assign inc_group_5 = ~(inc_isz \| stc \| iac);`
171			`assign sub_group_6 = ~(cmc \| sbm \| sub \| m12);`
172
173			`// The Condition Flip-Flop`
174			`reg n0397;`
175			`wire n0486 = ~((opa[2] & acc_0) \| (opa[1] & cy_1) \| (opa[0] & n0432));`
176	4	rrpollack	`wire n0419 = ~((add_0 \| ~isz) & (~jcn \| ((n0486 \| opa[3]) & (~n0486 \| ~opa[3]))));`
177			`wire n0413 = ~((sc & n0419 & x32) \| (~x32 & n0397));`
178	2	rrpollack	`reg n0405;`
179			`always @(posedge sysclk) begin`
180			`if (clk2)`
181			`n0405 <= n0413;`
182	4	rrpollack	`end`
183			`always @(posedge sysclk) begin`
184	2	rrpollack	`if (clk1)`
185			`n0397 <= ~n0405;`
186			`end`
187			`assign cn_n = ~n0397;`
188
189			`// The Single-Cycle Flip-Flop`
190	4	rrpollack	`reg n0343 = 1'b0;`
191	2	rrpollack	`wire n0368 = ~((sc & (fin_fim \| jcn_isz \| jun_jms) & x32) \| (n0343 & ~x32));`
192	4	rrpollack	`reg n0362 = 1'b1;`
193	2	rrpollack	`always @(posedge sysclk) begin`
194			`if (clk2)`
195			`n0362 <= n0368;`
196			`if (clk1)`
197			`n0343 <= ~n0362;`
198			`end`
199			`assign sc = ~n0343;`
200			`assign dc = ~sc;`
201
202			`// Generate ~(X21&~CLK2)`
203			`reg n0360;`
204			`always @(posedge sysclk) begin`
205			`if (clk2)`
206			`n0360 <= ~x12;`
207			`end`
208			`wire n0337 = ~(n0360 \| clk2);`
209			`assign x21_clk2 = ~n0337;`
210
211			`// Generate ~(X31&~CLK2)`
212			`reg n0380;`
213			`always @(posedge sysclk) begin`
214			`if (clk2)`
215			`n0380 <= ~x22;`
216			`end`
217			`wire n0375 = ~(n0380 \| clk2);`
218			`assign x31_clk2 = ~n0375;`
219
220			`// Generate ~COM`
221			`wire n0329 = io;`
222
223			`reg n0414, n0797;`
224			`always @(posedge sysclk) begin`
225			`if (clk2)`
226			`n0414 <= a22;`
227			`else`
228			`n0797 <= n0414;`
229			`end`
230
231			`reg n0433, n0801;`
232			`always @(posedge sysclk) begin`
233			`if (clk2)`
234			`n0433 <= m12;`
235			`else`
236			`n0801 <= n0433;`
237			`end`
238
239			`reg n0425, n0805;`
240			`always @(posedge sysclk) begin`
241			`if (clk2)`
242			`n0425 <= x12;`
243			`else`
244			`n0805 <= n0425;`
245			`end`
246
247			`wire n0782 = ~((n0801 & n0329) \| (src & n0805) \| n0797);`
248			`assign com_n = n0782;`
249
250			`// Generate N0342`
251			`wire n0332 = ~(((n0329 \| poc) & x22 & clk2) \| (~(n0329 \| poc) & n0337 & clk1));`
252			`assign n0342 = n0332;`
253
254			`// Output OPA onto the data bus`
255			`wire opa_ib = (ldm_bbl \| jun_jms) & ~x21_clk2;`
256			`assign data = opa_ib ? opa : 4'bzzzz;`
257
258			`endmodule`

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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4004/] [instruction_decode.v] - Blame information for rev 5