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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4004/] [instruction_pointer.v] - Blame information for rev 6

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`timescale 1ns / 1ps
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Instruction Pointer Array
//
// This file is part of the MCS-4 project hosted at OpenCores:
//      http://www.opencores.org/cores/mcs-4/
//
// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
// They are NOT "public domain", and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
 
module instruction_pointer (
    input  wire         sysclk,                 // 50 MHz FPGA clock
 
    // Inputs from the Timing and I/O board
    input  wire         clk1,
    input  wire         clk2,
    input  wire         a12,
    input  wire         a22,
    input  wire         a32,
    input  wire         m12,
    input  wire         m22,
    input  wire         x12,
    input  wire         x22,
    input  wire         x32,
    input  wire         poc,                    // Power-On Clear (reset)
    input  wire         m12_m22_clk1_m11_m12,   // M12+M22+CLK1~(M11+M12)
 
    // Common 4-bit data bus
    inout  wire [3:0]   data,
 
    // Inputs from the Instruction Decode board
    input  wire         jcn_isz,                // JCN+ISZ
    input  wire         jin_fin,                // JIN+FIN
    input  wire         jun_jms,                // JUN+JMS
    input  wire         cn_n,                   // ~CN
    input  wire         bbl,                    // BBL
    input  wire         jms,                    // JMS
    input  wire         sc,                     // SC (Single Cycle)
    input  wire         dc                      // DC (Double Cycle, ~SC)
    );
 
    reg  [11:0] dram_array [0:3];
    reg  [11:0] dram_temp;
    wire  [3:0] din_n;
 
    wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
 
    // Row Counter stuff
    wire [1:0]  addr_ptr;               // Effective Address counter
    wire        addr_ptr_step;          // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
    wire        n0459;
    wire        n0466;
 
    assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
                                       (m22 & dc & jms)));
    counter addr_ptr_0 (
        .sysclk(sysclk),
        .step_a_in(clk1),
        .step_b_in(addr_ptr_step),
        .step_a_out(n0459),
        .step_b_out(n0466),
        .q(),
        .qn(addr_ptr[0])
    );
    counter addr_ptr_1 (
        .sysclk(sysclk),
        .step_a_in(n0459),
        .step_b_in(n0466),
        .step_a_out(),
        .step_b_out(),
        .q(),
        .qn(addr_ptr[1])
    );
 
    // Refresh counter stuff
    wire [1:0]  addr_rfsh;              // Row Refresh counter
    wire        addr_rfsh_step;         // (~INH)&X32&CLK2
    wire        n0455;
    wire        n0463;
 
    assign addr_rfsh_step = ~inh & x32 & clk2;
 
    counter addr_rfsh_0 (
        .sysclk(sysclk),
        .step_a_in(clk1),
        .step_b_in(addr_rfsh_step),
        .step_a_out(n0455),
        .step_b_out(n0463),
        .q(),
        .qn(addr_rfsh[0])
    );
    counter addr_rfsh_1 (
        .sysclk(sysclk),
        .step_a_in(n0455),
        .step_b_in(n0463),
        .step_a_out(),
        .step_b_out(),
        .q(),
        .qn(addr_rfsh[1])
    );
 
    // Row selection mux
    reg  [1:0]  row;                    // {N0409, N0420}
    always @(posedge sysclk) begin
        if (x12)
            row <= addr_rfsh;
        if (x32)
            row <= addr_ptr;
    end
 
 
    // Row Precharge/Read/Write stuff
    wire        precharge;              // (~INH)(X11+X31)CLK1
    wire        row_read;               // (~POC)CLK2(X12+X32)~INH
    wire        row_write;              // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)
 
    reg n0517;
    always @(posedge sysclk) begin
        if (clk2)
            n0517 <= ~(m22 | x22);
    end
    assign precharge = ~(n0517 | inh | ~clk1);
 
    assign row_read = ~poc & clk2 & (x12 | x32) & ~inh;
 
    reg n0438;
    always @(posedge sysclk) begin
        if (clk2)
            n0438 <= ~((x12 & ~inh) | a32);
    end
    assign row_write = ~(n0438 | (jin_fin & ~sc) | ~clk1);
 
 
    // Column Read selection stuff
    reg n0416;
    always @(posedge sysclk) begin
        if (clk2)
            n0416 <= ~x32;
    end
    wire radb0 = ~(n0416 | clk2);
 
    reg n0384;
    always @(posedge sysclk) begin
        if (clk2)
            n0384 <= ~a12;
    end
    wire radb1 = ~(n0384 | clk2);
 
    reg n0374;
    always @(posedge sysclk) begin
        if (clk2)
            n0374 <= ~a22;
    end
    wire radb2 = ~(n0374 | clk2);
 
 
    // Column Write selection stuff
    wire n0322 = ~(sc | cn_n);
    wire wadb0 = ~(~clk2 | ~(a12 | (sc & jin_fin & x32) |
                        (((jcn_isz & n0322) | (jun_jms & ~sc)) & m22)));
    wire wadb1 = ~(~clk2 | ~(a22 | (sc & jin_fin & x22) |
                        (((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
    wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
 
 
    // Manage the row data buffer
    wire [11:0] row_data = dram_array[row];
    always @(posedge sysclk) begin
        if (precharge)
            dram_temp <= 12'b0;
 
        if (row_read)
            dram_temp <= row_data;
 
        if (wadb0)
            dram_temp[ 3:0] <= ~din_n;
        if (wadb1)
            dram_temp[ 7:4] <= ~din_n;
        if (wadb2)
            dram_temp[11:8] <= ~din_n;
    end
 
    // Handle row writes
    always @(posedge sysclk) begin
        if (row_write)
            dram_array[row] <= dram_temp;
    end
 
    // Manage the data output mux
    reg   [3:0] dout;
    always @(*) begin
        (* PARALLEL_CASE *)
        case (1'b1)
            radb0:      dout = dram_temp[ 3:0];
            radb1:      dout = dram_temp[ 7:4];
            radb2:      dout = dram_temp[11:8];
            default:    dout = 4'bzzzz;
        endcase
    end
    assign data = dout;
 
    // Data In mux and incrementer
    reg [3:0] incr_in;
    always @(posedge sysclk) begin
        if (m12_m22_clk1_m11_m12)
            incr_in <= data;
    end
 
    reg carry_out, carry_in;
    wire [4:0] incr_out = (a12 | ((a22 | a32) & carry_in)) ?
            (incr_in + 4'b0001) : {1'b0, incr_in};
    always @(posedge sysclk) begin
        if (clk2)
            carry_out <= incr_out[4];
        if (clk1)
            carry_in <= carry_out;
    end
    assign din_n = ~incr_out[3:0];
 
endmodule

Line No.	Rev	Author	Line
1	2	rrpollack	`timescale 1ns / 1ps
2			`default_nettype none
3			`////////////////////////////////////////////////////////////////////////`
4	6	rrpollack	`//`
5	2	rrpollack	`// 4004 Instruction Pointer Array`
6	6	rrpollack	`//`
7	2	rrpollack	`// This file is part of the MCS-4 project hosted at OpenCores:`
8			`// http://www.opencores.org/cores/mcs-4/`
9	6	rrpollack	`//`
10			`// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>`
11			`//`
12	2	rrpollack	`// These materials are provided under the Creative Commons`
13	6	rrpollack	`// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.`
14			`// They are NOT "public domain", and are protected by copyright.`
15			`//`
16	2	rrpollack	`// This work based on materials provided by Intel Corporation and`
17			`// others under the same license. See the file doc/License for`
18			`// details of this license.`
19			`//`
20			`////////////////////////////////////////////////////////////////////////`
21
22			`module instruction_pointer (`
23	6	rrpollack	`input wire sysclk, // 50 MHz FPGA clock`
24	2	rrpollack
25	6	rrpollack	`// Inputs from the Timing and I/O board`
26			`input wire clk1,`
27			`input wire clk2,`
28			`input wire a12,`
29			`input wire a22,`
30			`input wire a32,`
31			`input wire m12,`
32			`input wire m22,`
33			`input wire x12,`
34			`input wire x22,`
35			`input wire x32,`
36			`input wire poc, // Power-On Clear (reset)`
37			`input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)`
38	2	rrpollack
39	6	rrpollack	`// Common 4-bit data bus`
40			`inout wire [3:0] data,`
41	2	rrpollack
42	6	rrpollack	`// Inputs from the Instruction Decode board`
43			`input wire jcn_isz, // JCN+ISZ`
44			`input wire jin_fin, // JIN+FIN`
45			`input wire jun_jms, // JUN+JMS`
46			`input wire cn_n, // ~CN`
47			`input wire bbl, // BBL`
48			`input wire jms, // JMS`
49			`input wire sc, // SC (Single Cycle)`
50			`input wire dc // DC (Double Cycle, ~SC)`
51			`);`
52	2	rrpollack
53	6	rrpollack	`reg [11:0] dram_array [0:3];`
54			`reg [11:0] dram_temp;`
55			`wire [3:0] din_n;`
56	2	rrpollack
57	6	rrpollack	`wire inh = (jin_fin & sc) \| ((jun_jms \| (jcn_isz & ~cn_n)) & dc);`
58	2	rrpollack
59	6	rrpollack	`// Row Counter stuff`
60			`wire [1:0] addr_ptr; // Effective Address counter`
61			`wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))`
62			`wire n0459;`
63			`wire n0466;`
64	2	rrpollack
65	6	rrpollack	`assign addr_ptr_step = ~(~clk2 \| ~(((m22 \| x12 \| x22) & bbl) \|`
66			`(m22 & dc & jms)));`
67			`counter addr_ptr_0 (`
68			`.sysclk(sysclk),`
69			`.step_a_in(clk1),`
70			`.step_b_in(addr_ptr_step),`
71			`.step_a_out(n0459),`
72			`.step_b_out(n0466),`
73			`.q(),`
74			`.qn(addr_ptr[0])`
75			`);`
76			`counter addr_ptr_1 (`
77			`.sysclk(sysclk),`
78			`.step_a_in(n0459),`
79			`.step_b_in(n0466),`
80			`.step_a_out(),`
81			`.step_b_out(),`
82			`.q(),`
83			`.qn(addr_ptr[1])`
84			`);`
85	2	rrpollack
86	6	rrpollack	`// Refresh counter stuff`
87			`wire [1:0] addr_rfsh; // Row Refresh counter`
88			`wire addr_rfsh_step; // (~INH)&X32&CLK2`
89			`wire n0455;`
90			`wire n0463;`
91	2	rrpollack
92	6	rrpollack	`assign addr_rfsh_step = ~inh & x32 & clk2;`
93	2	rrpollack
94	6	rrpollack	`counter addr_rfsh_0 (`
95			`.sysclk(sysclk),`
96			`.step_a_in(clk1),`
97			`.step_b_in(addr_rfsh_step),`
98			`.step_a_out(n0455),`
99			`.step_b_out(n0463),`
100			`.q(),`
101			`.qn(addr_rfsh[0])`
102			`);`
103			`counter addr_rfsh_1 (`
104			`.sysclk(sysclk),`
105			`.step_a_in(n0455),`
106			`.step_b_in(n0463),`
107			`.step_a_out(),`
108			`.step_b_out(),`
109			`.q(),`
110			`.qn(addr_rfsh[1])`
111			`);`
112	2	rrpollack
113	6	rrpollack	`// Row selection mux`
114			`reg [1:0] row; // {N0409, N0420}`
115			`always @(posedge sysclk) begin`
116			`if (x12)`
117			`row <= addr_rfsh;`
118			`if (x32)`
119			`row <= addr_ptr;`
120			`end`
121	2	rrpollack
122
123	6	rrpollack	`// Row Precharge/Read/Write stuff`
124			`wire precharge; // (~INH)(X11+X31)CLK1`
125			`wire row_read; // (~POC)CLK2(X12+X32)~INH`
126			`wire row_write; // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)`
127	2	rrpollack
128	6	rrpollack	`reg n0517;`
129			`always @(posedge sysclk) begin`
130			`if (clk2)`
131			`n0517 <= ~(m22 \| x22);`
132			`end`
133			`assign precharge = ~(n0517 \| inh \| ~clk1);`
134	2	rrpollack
135	6	rrpollack	`assign row_read = ~poc & clk2 & (x12 \| x32) & ~inh;`
136	2	rrpollack
137	6	rrpollack	`reg n0438;`
138			`always @(posedge sysclk) begin`
139			`if (clk2)`
140			`n0438 <= ~((x12 & ~inh) \| a32);`
141			`end`
142			`assign row_write = ~(n0438 \| (jin_fin & ~sc) \| ~clk1);`
143	2	rrpollack
144
145	6	rrpollack	`// Column Read selection stuff`
146			`reg n0416;`
147			`always @(posedge sysclk) begin`
148			`if (clk2)`
149			`n0416 <= ~x32;`
150			`end`
151			`wire radb0 = ~(n0416 \| clk2);`
152	2	rrpollack
153	6	rrpollack	`reg n0384;`
154			`always @(posedge sysclk) begin`
155			`if (clk2)`
156			`n0384 <= ~a12;`
157			`end`
158			`wire radb1 = ~(n0384 \| clk2);`
159	2	rrpollack
160	6	rrpollack	`reg n0374;`
161			`always @(posedge sysclk) begin`
162			`if (clk2)`
163			`n0374 <= ~a22;`
164			`end`
165			`wire radb2 = ~(n0374 \| clk2);`
166	2	rrpollack
167
168	6	rrpollack	`// Column Write selection stuff`
169			`wire n0322 = ~(sc \| cn_n);`
170			`wire wadb0 = ~(~clk2 \| ~(a12 \| (sc & jin_fin & x32) \|`
171			`(((jcn_isz & n0322) \| (jun_jms & ~sc)) & m22)));`
172			`wire wadb1 = ~(~clk2 \| ~(a22 \| (sc & jin_fin & x22) \|`
173			`(((jcn_isz & n0322) \| (jun_jms & ~sc)) & m12)));`
174			`wire wadb2 = ~(~clk2 \| ~(a32 \| (jun_jms & ~sc & x22)));`
175	2	rrpollack
176
177	6	rrpollack	`// Manage the row data buffer`
178			`wire [11:0] row_data = dram_array[row];`
179			`always @(posedge sysclk) begin`
180			`if (precharge)`
181			`dram_temp <= 12'b0;`
182
183			`if (row_read)`
184			`dram_temp <= row_data;`
185
186			`if (wadb0)`
187			`dram_temp[ 3:0] <= ~din_n;`
188			`if (wadb1)`
189			`dram_temp[ 7:4] <= ~din_n;`
190			`if (wadb2)`
191			`dram_temp[11:8] <= ~din_n;`
192			`end`
193
194			`// Handle row writes`
195			`always @(posedge sysclk) begin`
196			`if (row_write)`
197			`dram_array[row] <= dram_temp;`
198			`end`
199
200			`// Manage the data output mux`
201			`reg [3:0] dout;`
202			`always @(*) begin`
203			`(* PARALLEL_CASE *)`
204			`case (1'b1)`
205			`radb0: dout = dram_temp[ 3:0];`
206			`radb1: dout = dram_temp[ 7:4];`
207			`radb2: dout = dram_temp[11:8];`
208			`default: dout = 4'bzzzz;`
209			`endcase`
210			`end`
211			`assign data = dout;`
212
213			`// Data In mux and incrementer`
214			`reg [3:0] incr_in;`
215			`always @(posedge sysclk) begin`
216			`if (m12_m22_clk1_m11_m12)`
217			`incr_in <= data;`
218			`end`
219
220			`reg carry_out, carry_in;`
221			`wire [4:0] incr_out = (a12 \| ((a22 \| a32) & carry_in)) ?`
222			`(incr_in + 4'b0001) : {1'b0, incr_in};`
223			`always @(posedge sysclk) begin`
224			`if (clk2)`
225			`carry_out <= incr_out[4];`
226			`if (clk1)`
227			`carry_in <= carry_out;`
228			`end`
229			`assign din_n = ~incr_out[3:0];`
230
231	2	rrpollack	`endmodule`

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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4004/] [instruction_pointer.v] - Blame information for rev 6