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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [altera-ep3sl150/] [default.sdc] - Blame information for rev 2

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1 2 dimamali
# Synplicity, Inc. constraint file
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# /home/jiri/ibm/vhdl/grlib/boards/gr-pci-xc2v/default.sdc
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# Written on Fri Jul 30 18:56:40 2004
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# by Synplify Pro, 7.6        Scope Editor
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#
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# Clocks
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#
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define_clock -name   {clk}  -freq 80.000 -clockgroup default_clkgroup
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define_clock -name   {clk125}  -freq 40.000 -clockgroup ddr_clkgroup
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#
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# Clock to Clock
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#
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#
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# Inputs/Outputs
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#
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define_output_delay -disable     -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
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define_input_delay -disable      -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
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#
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# Registers
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#
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#
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# Multicycle Path
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#
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#
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# False Path
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#
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#
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# Delay Path
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#
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# Attributes
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#
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define_global_attribute          syn_useioff {1}
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#
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# Compile Points
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#
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#
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# Other Constraints
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#

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