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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [avnet-xc2v1500/] [default.sdc] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
#
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# Clocks
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#
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define_clock   -name {clk}  -freq 50.000 -clockgroup default_clkgroup
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define_clock   -name {pci_clk}  -freq 45.000 -clockgroup pci_clkgroup
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#
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# Clock to Clock
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#
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# Inputs/Outputs
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define_output_delay -disable     -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
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define_input_delay -disable      -default  14.00 -improve 0.00 -route 0.00 -ref {clk:r}
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define_output_delay      -default  12.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
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define_input_delay       -default  15.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
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define_input_delay      {pci_rst}  0.00 -improve 0.00 -route 0.00 -ref {pci_clk:r}
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#
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# Registers
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#
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# Multicycle Path
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#
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# False Path
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# Delay Path
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# Attributes
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define_global_attribute          syn_useioff {1}
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#define_attribute          {erx_clk} syn_noclockbuf {1}
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#define_attribute          {etx_clk} syn_noclockbuf {1}
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#
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# Compile Points
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# Other Constraints
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#

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