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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [digilent-xup-xc2vp/] [default.ucf] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
############################################################################
2 
## This system.ucf file is generated by Base System Builder based on the
3 
## settings in the selected Xilinx Board Definition file. Please add other
4 
## user constraints to this file based on customer design specifications.
5 
## Author: Zhangxi Tan, UC Berkeley
6 
############################################################################
7 
 
8 
Net clk LOC=AJ15;
9 
Net clk IOSTANDARD = LVCMOS25;
10 
Net resetn LOC=AH5;
11 
Net resetn IOSTANDARD = LVTTL;
12 
## System level constraints
13 
Net clk TNM_NET = clk;
14 
TIMESPEC TS_clk = PERIOD clk 10000 ps;
15 
Net resetn TIG;
16 
 
17 
NET "ddrclk270" TNM_NET = "ddrclk270";
18 
TIMESPEC "TS_ddrclk270" = PERIOD "ddrclk270" 10.000 ns HIGH 50.00%;
19 
NET "ddrclk0" TNM_NET = "ddrclk0";
20 
TIMESPEC "TS_ddrclk0" = PERIOD "ddrclk0" "TS_ddrclk270" * 1.000000 PHASE-7.500ns HIGH 50.00%;
21 
NET "ddrclk180" TNM_NET = "ddrclk180";
22 
TIMESPEC "TS_ddrclk180" = PERIOD "ddrclk180" "TS_ddrclk270" * 1.000000 PHASE-2.500ns HIGH 50.00%;
23 
NET "ddrclk90" TNM_NET = "ddrclk90";
24 
TIMESPEC "TS_ddrclk90" = PERIOD "ddrclk90" "TS_ddrclk270" * 1.000000 PHASE-5.000ns HIGH 50.00%;
25 
 
26 
 
27 
Net "clkgen0/ddrclk_0" TNM_NET = clkgen0_ddrclk_0;
28 
TIMESPEC TS_clkgen0_ddrclk_0 = PERIOD clkgen0_ddrclk_0 10526 ps;
29 
Net "clkgen0/ddrclk_90" TNM_NET = clkgen0_ddrclk_90;
30 
TIMESPEC TS_clkgen0_ddrclk_90 = PERIOD clkgen0_ddrclk_90 TS_clkgen0_ddrclk_0 PHASE 2.632 ns HIGH 50%;
31 
Net "clkgen0/ddrclk_180" TNM_NET = clkgen0_ddrclk_180;
32 
TIMESPEC TS_clkgen0_ddrclk_180 = PERIOD clkgen0_ddrclk_180 TS_clkgen0_ddrclk_0 PHASE 5.263 ns HIGH 50%  ;
33 
Net "clkgen0/ddrclk_270" TNM_NET = clkgen0_ddrclk_270;
34 
TIMESPEC TS_clkgen0_ddrclk_270 = PERIOD clkgen0_ddrclk_270 TS_clkgen0_ddrclk_0 PHASE 7.895 ns HIGH 50%  ;
35 
 
36 
#Begin clock to clock delay constraints
37 
TIMEGRP "ddrclk270_rise" = RISING "ddrclk270";
38 
TIMEGRP "clkm_rise" = RISING "clkm";
39 
TIMESPEC "TS_ddrclk270_rise_clkm_rise" = FROM "ddrclk270_rise" TO "clkm_rise" TIG;
40 
TIMEGRP "ddrclk180_rise" = RISING "ddrclk180";
41 
TIMESPEC "TS_ddrclk180_rise_clkm_rise" = FROM "ddrclk180_rise" TO "clkm_rise" TIG;
42 
TIMEGRP "ddrclk90_rise" = RISING "ddrclk90";
43 
TIMESPEC "TS_ddrclk90_rise_clkm_rise" = FROM "ddrclk90_rise" TO "clkm_rise" TIG;
44 
TIMEGRP "ddrclk0_rise" = RISING "ddrclk0";
45 
TIMESPEC "TS_ddrclk0_rise_clkm_rise" = FROM "ddrclk0_rise" TO "clkm_rise" TIG;
46 
TIMESPEC "TS_clkm_rise_ddrclk270_rise" = FROM "clkm_rise" TO "ddrclk270_rise" TIG;
47 
TIMESPEC "TS_clkm_rise_ddrclk180_rise" = FROM "clkm_rise" TO "ddrclk180_rise" TIG;
48 
TIMESPEC "TS_clkm_rise_ddrclk90_rise" = FROM "clkm_rise" TO "ddrclk90_rise" TIG;
49 
TIMESPEC "TS_clkm_rise_ddrclk0_rise" = FROM "clkm_rise" TO "ddrclk0_rise" TIG;
50 
#End clock to clock delay constraints
51 
 
52 
 
53 
## IO Devices constraints
54 
 
55 
#### Module RS232_Uart_1 constraints
56 
 
57 
Net dsurx LOC=AJ8;
58 
Net dsurx IOSTANDARD = LVCMOS25;
59 
Net dsutx LOC=AE7;
60 
Net dsutx IOSTANDARD = LVCMOS25;
61 
Net dsutx SLEW = SLOW;
62 
Net dsutx DRIVE = 12;
63 
 
64 
#### Module DDR controller constraints
65 
Net ddr_ad<12> LOC=M25;
66 
Net ddr_ad<12> IOSTANDARD = SSTL2_II;
67 
Net ddr_ad<11> LOC=N25;
68 
Net ddr_ad<11> IOSTANDARD = SSTL2_II;
69 
Net ddr_ad<10> LOC=L26;
70 
Net ddr_ad<10> IOSTANDARD = SSTL2_II;
71 
Net ddr_ad<9> LOC=M29;
72 
Net ddr_ad<9> IOSTANDARD = SSTL2_II;
73 
Net ddr_ad<8> LOC=K30;
74 
Net ddr_ad<8> IOSTANDARD = SSTL2_II;
75 
Net ddr_ad<7> LOC=G25;
76 
Net ddr_ad<7> IOSTANDARD = SSTL2_II;
77 
Net ddr_ad<6> LOC=G26;
78 
Net ddr_ad<6> IOSTANDARD = SSTL2_II;
79 
Net ddr_ad<5> LOC=D26;
80 
Net ddr_ad<5> IOSTANDARD = SSTL2_II;
81 
Net ddr_ad<4> LOC=J24;
82 
Net ddr_ad<4> IOSTANDARD = SSTL2_II;
83 
Net ddr_ad<3> LOC=K24;
84 
Net ddr_ad<3> IOSTANDARD = SSTL2_II;
85 
Net ddr_ad<2> LOC=F28;
86 
Net ddr_ad<2> IOSTANDARD = SSTL2_II;
87 
Net ddr_ad<1> LOC=F30;
88 
Net ddr_ad<1> IOSTANDARD = SSTL2_II;
89 
Net ddr_ad<0> LOC=M24;
90 
Net ddr_ad<0> IOSTANDARD = SSTL2_II;
91 
Net ddr_ba<1> LOC=M26;
92 
Net ddr_ba<1> IOSTANDARD = SSTL2_II;
93 
Net ddr_ba<0> LOC=K26;
94 
Net ddr_ba<0> IOSTANDARD = SSTL2_II;
95 
Net ddr_cas LOC=L27;
96 
Net ddr_cas IOSTANDARD = SSTL2_II;
97 
Net ddr_cke LOC=R26;
98 
Net ddr_cke IOSTANDARD = SSTL2_II;
99 
Net ddr_cs LOC=R24;
100 
Net ddr_cs IOSTANDARD = SSTL2_II;
101 
Net ddr_ras LOC=N29;
102 
Net ddr_ras IOSTANDARD = SSTL2_II;
103 
Net ddr_we LOC=N26;
104 
Net ddr_we IOSTANDARD = SSTL2_II;
105 
Net ddr_dm<7> LOC=U26;
106 
Net ddr_dm<7> IOSTANDARD = SSTL2_II;
107 
Net ddr_dm<6> LOC=V29;
108 
Net ddr_dm<6> IOSTANDARD = SSTL2_II;
109 
Net ddr_dm<5> LOC=W29;
110 
Net ddr_dm<5> IOSTANDARD = SSTL2_II;
111 
Net ddr_dm<4> LOC=T22;
112 
Net ddr_dm<4> IOSTANDARD = SSTL2_II;
113 
Net ddr_dm<3> LOC=W28;
114 
Net ddr_dm<3> IOSTANDARD = SSTL2_II;
115 
Net ddr_dm<2> LOC=W27;
116 
Net ddr_dm<2> IOSTANDARD = SSTL2_II;
117 
Net ddr_dm<1> LOC=W26;
118 
Net ddr_dm<1> IOSTANDARD = SSTL2_II;
119 
Net ddr_dm<0> LOC=W25;
120 
Net ddr_dm<0> IOSTANDARD = SSTL2_II;
121 
Net ddr_dqs<7> LOC=E30;
122 
Net ddr_dqs<7> IOSTANDARD = SSTL2_II;
123 
Net ddr_dqs<6> LOC=J29;
124 
Net ddr_dqs<6> IOSTANDARD = SSTL2_II;
125 
Net ddr_dqs<5> LOC=M30;
126 
Net ddr_dqs<5> IOSTANDARD = SSTL2_II;
127 
Net ddr_dqs<4> LOC=P29;
128 
Net ddr_dqs<4> IOSTANDARD = SSTL2_II;
129 
Net ddr_dqs<3> LOC=V23;
130 
Net ddr_dqs<3> IOSTANDARD = SSTL2_II;
131 
Net ddr_dqs<2> LOC=AA25;
132 
Net ddr_dqs<2> IOSTANDARD = SSTL2_II;
133 
Net ddr_dqs<1> LOC=AC25;
134 
Net ddr_dqs<1> IOSTANDARD = SSTL2_II;
135 
Net ddr_dqs<0> LOC=AH26;
136 
Net ddr_dqs<0> IOSTANDARD = SSTL2_II;
137 
Net ddr_dq<63> LOC=C27;
138 
Net ddr_dq<63> IOSTANDARD = SSTL2_II;
139 
Net ddr_dq<62> LOC=D28;
140 
Net ddr_dq<62> IOSTANDARD = SSTL2_II;
141 
Net ddr_dq<61> LOC=D29;
142 
Net ddr_dq<61> IOSTANDARD = SSTL2_II;
143 
Net ddr_dq<60> LOC=D30;
144 
Net ddr_dq<60> IOSTANDARD = SSTL2_II;
145 
Net ddr_dq<59> LOC=H25;
146 
Net ddr_dq<59> IOSTANDARD = SSTL2_II;
147 
Net ddr_dq<58> LOC=H26;
148 
Net ddr_dq<58> IOSTANDARD = SSTL2_II;
149 
Net ddr_dq<57> LOC=E27;
150 
Net ddr_dq<57> IOSTANDARD = SSTL2_II;
151 
Net ddr_dq<56> LOC=E28;
152 
Net ddr_dq<56> IOSTANDARD = SSTL2_II;
153 
Net ddr_dq<55> LOC=J26;
154 
Net ddr_dq<55> IOSTANDARD = SSTL2_II;
155 
Net ddr_dq<54> LOC=G27;
156 
Net ddr_dq<54> IOSTANDARD = SSTL2_II;
157 
Net ddr_dq<53> LOC=G28;
158 
Net ddr_dq<53> IOSTANDARD = SSTL2_II;
159 
Net ddr_dq<52> LOC=G30;
160 
Net ddr_dq<52> IOSTANDARD = SSTL2_II;
161 
Net ddr_dq<51> LOC=L23;
162 
Net ddr_dq<51> IOSTANDARD = SSTL2_II;
163 
Net ddr_dq<50> LOC=L24;
164 
Net ddr_dq<50> IOSTANDARD = SSTL2_II;
165 
Net ddr_dq<49> LOC=H27;
166 
Net ddr_dq<49> IOSTANDARD = SSTL2_II;
167 
Net ddr_dq<48> LOC=H28;
168 
Net ddr_dq<48> IOSTANDARD = SSTL2_II;
169 
Net ddr_dq<47> LOC=J27;
170 
Net ddr_dq<47> IOSTANDARD = SSTL2_II;
171 
Net ddr_dq<46> LOC=J28;
172 
Net ddr_dq<46> IOSTANDARD = SSTL2_II;
173 
Net ddr_dq<45> LOC=K29;
174 
Net ddr_dq<45> IOSTANDARD = SSTL2_II;
175 
Net ddr_dq<44> LOC=L29;
176 
Net ddr_dq<44> IOSTANDARD = SSTL2_II;
177 
Net ddr_dq<43> LOC=N23;
178 
Net ddr_dq<43> IOSTANDARD = SSTL2_II;
179 
Net ddr_dq<42> LOC=N24;
180 
Net ddr_dq<42> IOSTANDARD = SSTL2_II;
181 
Net ddr_dq<41> LOC=K27;
182 
Net ddr_dq<41> IOSTANDARD = SSTL2_II;
183 
Net ddr_dq<40> LOC=K28;
184 
Net ddr_dq<40> IOSTANDARD = SSTL2_II;
185 
Net ddr_dq<39> LOC=R22;
186 
Net ddr_dq<39> IOSTANDARD = SSTL2_II;
187 
Net ddr_dq<38> LOC=M27;
188 
Net ddr_dq<38> IOSTANDARD = SSTL2_II;
189 
Net ddr_dq<37> LOC=M28;
190 
Net ddr_dq<37> IOSTANDARD = SSTL2_II;
191 
Net ddr_dq<36> LOC=P30;
192 
Net ddr_dq<36> IOSTANDARD = SSTL2_II;
193 
Net ddr_dq<35> LOC=P23;
194 
Net ddr_dq<35> IOSTANDARD = SSTL2_II;
195 
Net ddr_dq<34> LOC=P24;
196 
Net ddr_dq<34> IOSTANDARD = SSTL2_II;
197 
Net ddr_dq<33> LOC=N27;
198 
Net ddr_dq<33> IOSTANDARD = SSTL2_II;
199 
Net ddr_dq<32> LOC=N28;
200 
Net ddr_dq<32> IOSTANDARD = SSTL2_II;
201 
Net ddr_dq<31> LOC=V27;
202 
Net ddr_dq<31> IOSTANDARD = SSTL2_II;
203 
Net ddr_dq<30> LOC=Y30;
204 
Net ddr_dq<30> IOSTANDARD = SSTL2_II;
205 
Net ddr_dq<29> LOC=U24;
206 
Net ddr_dq<29> IOSTANDARD = SSTL2_II;
207 
Net ddr_dq<28> LOC=U23;
208 
Net ddr_dq<28> IOSTANDARD = SSTL2_II;
209 
Net ddr_dq<27> LOC=V26;
210 
Net ddr_dq<27> IOSTANDARD = SSTL2_II;
211 
Net ddr_dq<26> LOC=V25;
212 
Net ddr_dq<26> IOSTANDARD = SSTL2_II;
213 
Net ddr_dq<25> LOC=Y29;
214 
Net ddr_dq<25> IOSTANDARD = SSTL2_II;
215 
Net ddr_dq<24> LOC=AA29;
216 
Net ddr_dq<24> IOSTANDARD = SSTL2_II;
217 
Net ddr_dq<23> LOC=Y26;
218 
Net ddr_dq<23> IOSTANDARD = SSTL2_II;
219 
Net ddr_dq<22> LOC=AA28;
220 
Net ddr_dq<22> IOSTANDARD = SSTL2_II;
221 
Net ddr_dq<21> LOC=AA27;
222 
Net ddr_dq<21> IOSTANDARD = SSTL2_II;
223 
Net ddr_dq<20> LOC=W24;
224 
Net ddr_dq<20> IOSTANDARD = SSTL2_II;
225 
Net ddr_dq<19> LOC=W23;
226 
Net ddr_dq<19> IOSTANDARD = SSTL2_II;
227 
Net ddr_dq<18> LOC=AB28;
228 
Net ddr_dq<18> IOSTANDARD = SSTL2_II;
229 
Net ddr_dq<17> LOC=AB27;
230 
Net ddr_dq<17> IOSTANDARD = SSTL2_II;
231 
Net ddr_dq<16> LOC=AC29;
232 
Net ddr_dq<16> IOSTANDARD = SSTL2_II;
233 
Net ddr_dq<15> LOC=AB25;
234 
Net ddr_dq<15> IOSTANDARD = SSTL2_II;
235 
Net ddr_dq<14> LOC=AE29;
236 
Net ddr_dq<14> IOSTANDARD = SSTL2_II;
237 
Net ddr_dq<13> LOC=AA24;
238 
Net ddr_dq<13> IOSTANDARD = SSTL2_II;
239 
Net ddr_dq<12> LOC=AA23;
240 
Net ddr_dq<12> IOSTANDARD = SSTL2_II;
241 
Net ddr_dq<11> LOC=AD28;
242 
Net ddr_dq<11> IOSTANDARD = SSTL2_II;
243 
Net ddr_dq<10> LOC=AD27;
244 
Net ddr_dq<10> IOSTANDARD = SSTL2_II;
245 
Net ddr_dq<9> LOC=AF30;
246 
Net ddr_dq<9> IOSTANDARD = SSTL2_II;
247 
Net ddr_dq<8> LOC=AF29;
248 
Net ddr_dq<8> IOSTANDARD = SSTL2_II;
249 
Net ddr_dq<7> LOC=AF25;
250 
Net ddr_dq<7> IOSTANDARD = SSTL2_II;
251 
Net ddr_dq<6> LOC=AG30;
252 
Net ddr_dq<6> IOSTANDARD = SSTL2_II;
253 
Net ddr_dq<5> LOC=AG29;
254 
Net ddr_dq<5> IOSTANDARD = SSTL2_II;
255 
Net ddr_dq<4> LOC=AD26;
256 
Net ddr_dq<4> IOSTANDARD = SSTL2_II;
257 
Net ddr_dq<3> LOC=AD25;
258 
Net ddr_dq<3> IOSTANDARD = SSTL2_II;
259 
Net ddr_dq<2> LOC=AG28;
260 
Net ddr_dq<2> IOSTANDARD = SSTL2_II;
261 
Net ddr_dq<1> LOC=AH27;
262 
Net ddr_dq<1> IOSTANDARD = SSTL2_II;
263 
Net ddr_dq<0> LOC=AH29;
264 
Net ddr_dq<0> IOSTANDARD = SSTL2_II;
265 
Net ddr_clk<2> LOC=AC27;
266 
Net ddr_clk<2> IOSTANDARD = SSTL2_II;
267 
Net ddr_clk<1> LOC=AD29;
268 
Net ddr_clk<1> IOSTANDARD = SSTL2_II;
269 
Net ddr_clk<0> LOC=AB23;
270 
Net ddr_clk<0> IOSTANDARD = SSTL2_II;
271 
Net ddr_clkn<2> LOC=AC28;
272 
Net ddr_clkn<2> IOSTANDARD = SSTL2_II;
273 
Net ddr_clkn<1> LOC=AD30;
274 
Net ddr_clkn<1> IOSTANDARD = SSTL2_II;
275 
Net ddr_clkn<0> LOC=AB24;
276 
Net ddr_clkn<0> IOSTANDARD = SSTL2_II;
277 
 
278 
Net ddr_clk_fb LOC=C16;
279 
Net ddr_clk_fb IOSTANDARD = SSTL2_II;
280 
Net ddr_clk_fb_out LOC=G23;
281 
Net ddr_clk_fb_out IOSTANDARD = SSTL2_II;
282 
 
283 
## NET ddr_clk_fb FEEDBACK = 1 ns NET ddr_clk_fb_out;
284 
 
285 
#### Ethernet MAC constraints####
286 
## NET "erx_clk" TNM_NET = "RXCLK_GRP_Ethernet_MAC";
287 
## NET "etx_clk" TNM_NET = "TXCLK_GRP_Ethernet_MAC";
288 
## TIMESPEC "TSTXOUT_Ethernet_MAC" = FROM "TXCLK_GRP_Ethernet_MAC" TO "PADS" 10 ns;
289 
## TIMESPEC "TSRXIN_Ethernet_MAC" = FROM "PADS" TO "RXCLK_GRP_Ethernet_MAC" 6 ns;
290 
## NET "etx_clk" MAXSKEW= 2.0 ns;
291 
## NET "erx_clk" MAXSKEW= 2.0 ns;
292 
NET "etx_clk" PERIOD = 40 ns HIGH 14 ns;
293 
NET "erx_clk" PERIOD = 40 ns HIGH 14 ns;
294 
## NET "erxd<3>" NODELAY;
295 
## NET "erxd<2>" NODELAY;
296 
## NET "erxd<1>" NODELAY;
297 
## NET "erxd<0>" NODELAY;
298 
## NET "erx_dv" NODELAY;
299 
## NET "erx_er" NODELAY;
300 
## NET "erx_crs" NODELAY;
301 
## NET "erx_col" NODELAY;
302 
 
303 
 
304 
Net em_slew1 LOC=B3;
305 
Net em_slew1 IOSTANDARD = LVTTL;
306 
Net em_slew1 SLEW = SLOW;
307 
Net em_slew1 DRIVE = 8;
308 
Net em_slew2 LOC=A3;
309 
Net em_slew2 IOSTANDARD = LVTTL;
310 
Net em_slew2 SLEW = SLOW;
311 
Net em_slew2 DRIVE = 8;
312 
Net em_resetn LOC=G6;
313 
Net em_resetn IOSTANDARD = LVTTL;
314 
Net em_resetn SLEW = SLOW;
315 
Net em_resetn DRIVE = 8;
316 
Net erx_crs LOC=C5;
317 
Net erx_crs IOSTANDARD = LVTTL;
318 
Net erx_col LOC=D5;
319 
Net erx_col IOSTANDARD = LVTTL;
320 
Net etxd<3> LOC=C2;
321 
Net etxd<3> IOSTANDARD = LVTTL;
322 
Net etxd<3> SLEW = SLOW;
323 
Net etxd<3> DRIVE = 8;
324 
Net etxd<2> LOC=C1;
325 
Net etxd<2> IOSTANDARD = LVTTL;
326 
Net etxd<2> SLEW = SLOW;
327 
Net etxd<2> DRIVE = 8;
328 
Net etxd<1> LOC=J8;
329 
Net etxd<1> IOSTANDARD = LVTTL;
330 
Net etxd<1> SLEW = SLOW;
331 
Net etxd<1> DRIVE = 8;
332 
Net etxd<0> LOC=J7;
333 
Net etxd<0> IOSTANDARD = LVTTL;
334 
Net etxd<0> SLEW = SLOW;
335 
Net etxd<0> DRIVE = 8;
336 
Net etx_en LOC=C4;
337 
Net etx_en IOSTANDARD = LVTTL;
338 
Net etx_en SLEW = SLOW;
339 
Net etx_en DRIVE = 8;
340 
Net etx_clk LOC=D3;
341 
Net etx_clk IOSTANDARD = LVTTL;
342 
Net etx_er LOC=H2;
343 
Net etx_er IOSTANDARD = LVTTL;
344 
Net erx_er LOC=J2;
345 
Net erx_er IOSTANDARD = LVTTL;
346 
Net erx_clk LOC=M8;
347 
Net erx_clk IOSTANDARD = LVTTL;
348 
Net erx_dv LOC=M7;
349 
Net erx_dv IOSTANDARD = LVTTL;
350 
Net erxd<0> LOC=K6;
351 
Net erxd<0> IOSTANDARD = LVTTL;
352 
Net erxd<1> LOC=K5;
353 
Net erxd<1> IOSTANDARD = LVTTL;
354 
Net erxd<2> LOC=J1;
355 
Net erxd<2> IOSTANDARD = LVTTL;
356 
Net erxd<3> LOC=K1;
357 
Net erxd<3> IOSTANDARD = LVTTL;
358 
Net emdc LOC=M6;
359 
Net emdc IOSTANDARD = LVTTL;
360 
Net emdc SLEW = SLOW;
361 
Net emdc DRIVE = 8;
362 
Net emdio LOC=M5;
363 
Net emdio IOSTANDARD = LVTTL;
364 
Net emdio SLEW = SLOW;
365 
Net emdio DRIVE = 8;
366 
 
367 
NET dsuact LOC = "AC4";
368 
NET dsuact IOSTANDARD = LVTTL;
369 
NET dsuact DRIVE = 12;
370 
NET dsuact SLEW = SLOW;
371 
 
372 
NET errorn LOC = "AC3";
373 
NET errorn IOSTANDARD = LVTTL;
374 
NET errorn DRIVE = 12;
375 
NET errorn SLEW = SLOW;

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