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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [xilinx-ml40x-xc4v/] [leon3mp.ucf] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
#
2 
#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
3 
#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
4 
#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
5 
#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
6 
#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
7 
#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
8 
#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
9 
#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
10 
#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
11 
#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
12 
#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
13 
#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14 
#     FOR A PARTICULAR PURPOSE.
15 
#
16 
#     (c) Copyright 2005 Xilinx, Inc.
17 
#     All rights reserved.
18 
#
19 
 
20 
# Bus clock nets
21 
#NET "clkm"  TNM_NET = "clkm";
22 
#NET "tft_clk"  TNM_NET = "tft_clk";
23 
#NET sys_clk TNM_NET = "sys_clk";
24 
#TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
25 
 
26 
NET sys_clk period = 10.000 ;
27 
NET sys_clk LOC = AE14;
28 
NET sys_clk IOSTANDARD = LVCMOS33;
29 
NET sys_rst_in LOC = D6 | IOSTANDARD = LVCMOS25;
30 
NET sys_rst_in PULLUP;
31 
NET sys_rst_in TIG;
32 
 
33 
#OFFSET = OUT : 5.600 : AFTER sys_clk ;
34 
OFFSET = OUT : 22.000 : AFTER sys_clk ;
35 
OFFSET = IN : 5.000 : BEFORE sys_clk ;
36 
 
37 
# SSRAM output delay
38 
#NET sram_flash_data(*) TNM = ssrdatapads;
39 
#TIMEGRP ssrdatapads OFFSET = OUT 5.600 AFTER sys_clk;
40 
 
41 
NET rxd1 LOC = W2;
42 
NET rxd1 IOSTANDARD = LVCMOS33;
43 
NET rxd1 TIG;
44 
NET txd1 LOC = W1;
45 
NET txd1 IOSTANDARD = LVCMOS33;
46 
NET txd1 TIG;
47 
 
48 
#NET ext_irq TIG;
49 
 
50 
# Reset timing ignore - treat as async paths
51 
#NET sys_rst TIG;
52 
#NET opb_v20_0_OPB_Rst TIG;
53 
#NET lmb_v10_1_OPB_Rst TIG;
54 
#NET lmb_v10_0_OPB_Rst TIG;
55 
#NET opb_v20_0_Debug_SYS_Rst TIG;
56 
#NET Debug_Rst TIG;
57 
#NET plb_v34_0_PLB_Rst TIG;
58 
#NET dcm_locked TIG;
59 
 
60 
# Locate DCM/BUFG - Tools can probably figure them out automatically
61 
#                   but just LOC them down to be safe
62 
#INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
63 
#INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
64 
#INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
65 
 
66 
#INST dcm_0/dcm_0/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y0;
67 
#INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
68 
#INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
69 
 
70 
#INST dcm_1/dcm_1/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y31;
71 
#INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
72 
 
73 
////////////////////////////////////////////////////////////////////////////
74 
// Buttons, LEDs, and DIP Switches
75 
////////////////////////////////////////////////////////////////////////////
76 
 
77 
# GPLED 0-3
78 
NET gpio(0)  LOC = G5 | IOSTANDARD = LVCMOS25;  #GPLED0
79 
NET gpio(1)  LOC = G6 | IOSTANDARD = LVCMOS25;  #GPLED1
80 
NET gpio(2)  LOC = A11 | IOSTANDARD = LVCMOS25; #GPLED2
81 
NET gpio(3)  LOC = A12 | IOSTANDARD = LVCMOS25; #GPLED3
82 
# North-East-South-West-Center LEDs
83 
NET gpio(4)  LOC = C6 | IOSTANDARD = LVCMOS25;  # C LED
84 
NET gpio(5)  LOC = F9 | IOSTANDARD = LVCMOS25;  # W LED
85 
NET gpio(6)  LOC = A5 | IOSTANDARD = LVCMOS25;  # S LED
86 
NET gpio(7)  LOC = E10 | IOSTANDARD = LVCMOS25; # E LED
87 
NET gpio(8)  LOC = E2 | IOSTANDARD = LVCMOS25;  # N LED
88 
# North-East-South-West-Center Buttons
89 
NET gpio(9)  LOC = B6 | IOSTANDARD = LVCMOS25;  # C Button
90 
NET gpio(10) LOC = E9 | IOSTANDARD = LVCMOS25;  # W Button
91 
NET gpio(11) LOC = A6 | IOSTANDARD = LVCMOS25;  # S Button
92 
NET gpio(12) LOC = F10 | IOSTANDARD = LVCMOS25; # E Button
93 
NET gpio(13) LOC = E7 | IOSTANDARD = LVCMOS25;  # N Button
94 
# Dip Switches 1-8
95 
NET gpio(14) LOC = U24; # DIP SW 8
96 
NET gpio(15) LOC = U25; # DIP SW 7
97 
NET gpio(16) LOC = V23; # DIP SW 6
98 
NET gpio(17) LOC = U23; # DIP SW 5
99 
NET gpio(18) LOC = U26; # DIP SW 4
100 
NET gpio(19) LOC = T26; # DIP SW 3
101 
NET gpio(20) LOC = R19; # DIP SW 2
102 
NET gpio(21) LOC = R20; # DIP SW 1
103 
NET gpio(14) IOSTANDARD = LVCMOS33;
104 
NET gpio(15) IOSTANDARD = LVCMOS33;
105 
NET gpio(16) IOSTANDARD = LVCMOS33;
106 
NET gpio(17) IOSTANDARD = LVCMOS33;
107 
NET gpio(18) IOSTANDARD = LVCMOS33;
108 
NET gpio(19) IOSTANDARD = LVCMOS33;
109 
NET gpio(20) IOSTANDARD = LVCMOS33;
110 
NET gpio(21) IOSTANDARD = LVCMOS33;
111 
#SMA Connectors
112 
NET gpio(22) LOC = C12; # SMA_IN_N
113 
NET gpio(23) LOC = C13; # SMA_IN_P
114 
NET gpio(24) LOC = D7 | IOSTANDARD = LVCMOS25;  # SMA_OUT_N
115 
NET gpio(25) LOC = D8 | IOSTANDARD = LVCMOS25;  # SMA_OUT_P
116 
NET gpio(26) LOC = AD12;# USERCLK
117 
NET gpio(26) IOSTANDARD = LVCMOS33;
118 
 
119 
NET "gpio(*)" PULLDOWN;
120 
NET "gpio(*)" TIG;
121 
NET "gpio(*)" SLEW = SLOW;
122 
NET "gpio(*)" DRIVE = 2;
123 
 
124 
NET "gpio(22)" SLEW = FAST;
125 
NET "gpio(22)" DRIVE = 12;
126 
NET "gpio(23)" SLEW = FAST;
127 
NET "gpio(23)" DRIVE = 12;
128 
NET "gpio(24)" SLEW = FAST;
129 
NET "gpio(24)" DRIVE = 12;
130 
NET "gpio(25)" SLEW = FAST;
131 
NET "gpio(25)" DRIVE = 12;
132 
 
133 
NET gpio(22) IOSTANDARD = LVCMOS25;
134 
NET gpio(23) IOSTANDARD = LVCMOS25;
135 
 
136 
#NET  "gpio2_d_out(*)" TIG;
137 
#NET  "gpio2_t_out(*)" TIG;
138 
#NET  "gpio2_in(*)" TIG;
139 
 
140 
#------------------------------------------------------------------------------
141 
# IO Pad Location Constraints / Properties for PS/2 Ports
142 
#------------------------------------------------------------------------------
143 
 
144 
#Keyboard
145 
NET ps2_keyb_clk  LOC = D2;
146 
NET ps2_keyb_clk  SLEW = SLOW;
147 
NET ps2_keyb_clk  DRIVE = 2;
148 
NET ps2_keyb_clk  TIG;
149 
NET ps2_keyb_data LOC = G9;
150 
NET ps2_keyb_data SLEW = SLOW;
151 
NET ps2_keyb_data DRIVE = 2;
152 
NET ps2_keyb_data TIG;
153 
NET ps2_keyb_clk IOSTANDARD = LVCMOS25;
154 
NET ps2_keyb_data IOSTANDARD = LVCMOS25;
155 
 
156 
#Mouse
157 
NET ps2_mouse_clk  LOC = B14;
158 
NET ps2_mouse_clk  SLEW = SLOW;
159 
NET ps2_mouse_clk  DRIVE = 2;
160 
NET ps2_mouse_clk  TIG;
161 
NET ps2_mouse_clk IOSTANDARD = LVCMOS25;
162 
NET ps2_mouse_data LOC = C14;
163 
NET ps2_mouse_data SLEW = SLOW;
164 
NET ps2_mouse_data DRIVE = 2;
165 
NET ps2_mouse_data TIG;
166 
NET ps2_mouse_data IOSTANDARD = LVCMOS25;
167 
 
168 
#------------------------------------------------------------------------------
169 
# IO Pad Location Constraints / Properties for IIC Controller
170 
#------------------------------------------------------------------------------
171 
 
172 
NET iic_scl    LOC = A17;
173 
NET iic_sda    LOC = B17;
174 
NET iic_scl    SLEW = SLOW;
175 
NET iic_scl    DRIVE = 6;
176 
#NET iic_scl    TIG;
177 
#NET iic_sda    SLEW = SLOW;
178 
NET iic_sda    DRIVE = 6;
179 
#NET iic_sda    TIG;
180 
 
181 
#------------------------------------------------------------------------------
182 
# IO Pad Location Constraints / Properties for AC97 Sound Controller
183 
#------------------------------------------------------------------------------
184 
 
185 
NET ac97_bit_clk   LOC = AE10;
186 
NET ac97_bit_clk   IOSTANDARD = LVCMOS33;
187 
#NET ac97_bit_clk   PERIOD = 80;
188 
NET ac97_sdata_in  LOC = AD16;
189 
NET ac97_sdata_in  IOSTANDARD = LVCMOS33;
190 
NET ac97_reset_n   LOC = AD10;
191 
NET ac97_reset_n   IOSTANDARD = LVCMOS33;
192 
#NET ac97_reset_n   TIG;
193 
NET ac97_sdata_out LOC = C8;
194 
NET ac97_sync      LOC = D9;
195 
NET ac97_sdata_out   IOSTANDARD = LVCMOS25;
196 
NET ac97_sync   IOSTANDARD = LVCMOS25;
197 
 
198 
#------------------------------------------------------------------------------
199 
# IO Pad Location Constraints / Properties for System ACE MPU / USB
200 
#------------------------------------------------------------------------------
201 
 
202 
NET sysace_clk_in   LOC        = AF11;
203 
NET sysace_clk_in   IOSTANDARD = LVCMOS33;
204 
#NET sysace_clk_in   TNM_NET    = "sysace_clk_in";
205 
# Leave 1 ns margin
206 
#TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
207 
 
208 
NET sace_usb_a(0)   LOC        = U22;
209 
NET sace_usb_a(1)   LOC        = Y10;
210 
NET sace_usb_a(2)   LOC        = AA10;
211 
NET sace_usb_a(3)   LOC        = AC7;
212 
NET sace_usb_a(4)   LOC        = Y7;
213 
NET sace_usb_a(5)   LOC        = AA9;
214 
NET sace_usb_a(6)   LOC        = Y9;
215 
NET sace_usb_a(*)   IOSTANDARD = LVCMOS33;
216 
NET sace_usb_a(*)   SLEW       = FAST;
217 
NET sace_usb_a(*)   DRIVE      = 8;
218 
NET sace_mpce       LOC        = AD5;
219 
NET sace_mpce       IOSTANDARD = LVCMOS33;
220 
NET sace_mpce       SLEW       = FAST;
221 
NET sace_mpce       DRIVE      = 8;
222 
NET sace_usb_d(0)   LOC        = AB7;
223 
NET sace_usb_d(1)   LOC        = AC9;
224 
NET sace_usb_d(2)   LOC        = AB9;
225 
NET sace_usb_d(3)   LOC        = AE6;
226 
NET sace_usb_d(4)   LOC        = AD6;
227 
NET sace_usb_d(5)   LOC        = AF9;
228 
NET sace_usb_d(6)   LOC        = AE9;
229 
NET sace_usb_d(7)   LOC        = AD8;
230 
NET sace_usb_d(8)   LOC        = AC8;
231 
NET sace_usb_d(9)   LOC        = AF4;
232 
NET sace_usb_d(10)  LOC        = AE4;
233 
NET sace_usb_d(11)  LOC        = AD3;
234 
NET sace_usb_d(12)  LOC        = AC3;
235 
NET sace_usb_d(13)  LOC        = AF6;
236 
NET sace_usb_d(14)  LOC        = AF5;
237 
NET sace_usb_d(15)  LOC        = AA7;
238 
NET sace_usb_d(*)   IOSTANDARD = LVCMOS33;
239 
NET sace_usb_d(*)   SLEW       = FAST;
240 
NET sace_usb_d(*)   DRIVE      = 8;
241 
#NET sace_usb_d(*)   PULLDOWN;
242 
NET sace_usb_oen    LOC        = AA8;
243 
NET sace_usb_oen    IOSTANDARD = LVCMOS33;
244 
NET sace_usb_oen    SLEW       = FAST;
245 
NET sace_usb_oen    DRIVE      = 8;
246 
NET sace_usb_wen    LOC        = Y8;
247 
NET sace_usb_wen    IOSTANDARD = LVCMOS33;
248 
NET sace_usb_wen    SLEW       = FAST;
249 
NET sace_usb_wen    DRIVE      = 8;
250 
NET sysace_mpirq    LOC        = AD4;
251 
NET sysace_mpirq    IOSTANDARD = LVCMOS33;
252 
#NET sysace_mpirq    TIG;
253 
#NET sysace_mpirq    PULLDOWN;
254 
 
255 
NET usb_csn         LOC        = AF10;
256 
NET usb_csn         IOSTANDARD = LVCMOS33;
257 
NET usb_csn         SLEW       = FAST;
258 
NET usb_csn         DRIVE      = 8;
259 
NET usb_hpi_reset_n LOC        = A7;
260 
NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
261 
#NET usb_hpi_reset_n TIG;
262 
NET usb_hpi_int     LOC        = V5;
263 
NET usb_hpi_int     IOSTANDARD = LVCMOS33;
264 
#NET usb_hpi_int     TIG;
265 
#NET usb_hpi_int     PULLDOWN;
266 
 
267 
#------------------------------------------------------------------------------
268 
# IO Pad Location Constraints / Properties for DDR Controllers
269 
#------------------------------------------------------------------------------
270 
 
271 
NET ddr_ad(0)  LOC = C26; # DDR_A0
272 
NET ddr_ad(1)  LOC = E17; # DDR_A1
273 
NET ddr_ad(2)  LOC = D18; # DDR_A2
274 
NET ddr_ad(3)  LOC = C19; # DDR_A3
275 
NET ddr_ad(4)  LOC = F17; # DDR_A4
276 
NET ddr_ad(5)  LOC = B18; # DDR_A5
277 
NET ddr_ad(6)  LOC = B20; # DDR_A6
278 
NET ddr_ad(7)  LOC = C20; # DDR_A7
279 
NET ddr_ad(8)  LOC = D20; # DDR_A8
280 
NET ddr_ad(9)  LOC = C21; # DDR_A9
281 
NET ddr_ad(10) LOC = A18; # DDR_A10
282 
NET ddr_ad(11) LOC = B21; # DDR_A11
283 
NET ddr_ad(12) LOC = A24; # DDR_A12
284 
NET ddr_ba(0)  LOC = B12; # DDR_BA0
285 
NET ddr_ba(1)  LOC = A16; # DDR_BA1
286 
NET ddr_casb   LOC = F23; # DDR_CAS_N
287 
NET ddr_cke    LOC = G22; # DDR_CKE
288 
NET ddr_csb    LOC = G21; # DDR_CS_N
289 
NET ddr_rasb   LOC = F24; # DDR_RAS_N
290 
NET ddr_web    LOC = A23; # DDR_WE_N
291 
 
292 
NET ddr_clk    LOC = A10; # DDR_CK1_P
293 
NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
294 
NET ddr_clkb   LOC = B10; # DDR_CK1_N
295 
 
296 
NET ddr_dm(0)  LOC = G19; # DDR_DM0
297 
NET ddr_dm(1)  LOC = G24; # DDR_DM1
298 
NET ddr_dm(2)  LOC = G20; # DDR_DM2
299 
NET ddr_dm(3)  LOC = C22; # DDR_DM3
300 
 
301 
NET ddr_dqs(0) LOC = D25; # DDR_DQS0
302 
NET ddr_dqs(1) LOC = G18; # DDR_DQS1
303 
NET ddr_dqs(2) LOC = G17; # DDR_DQS2
304 
NET ddr_dqs(3) LOC = D26; # DDR_DQS3
305 
 
306 
NET ddr_dq(0) LOC = H20; # DDR_D0
307 
NET ddr_dq(1) LOC = E23; # DDR_D1
308 
NET ddr_dq(2) LOC = H26; # DDR_D2
309 
NET ddr_dq(3) LOC = H22; # DDR_D3
310 
NET ddr_dq(4) LOC = E25; # DDR_D4
311 
NET ddr_dq(5) LOC = E26; # DDR_D5
312 
NET ddr_dq(6) LOC = F26; # DDR_D6
313 
NET ddr_dq(7) LOC = E24; # DDR_D7
314 
NET ddr_dq(8) LOC = E20; # DDR_D8
315 
NET ddr_dq(9) LOC = A22; # DDR_D9
316 
NET ddr_dq(10) LOC = C23; # DDR_D10
317 
NET ddr_dq(11) LOC = C24; # DDR_D11
318 
NET ddr_dq(12) LOC = A20; # DDR_D12
319 
NET ddr_dq(13) LOC = A21; # DDR_D13
320 
NET ddr_dq(14) LOC = D24; # DDR_D14
321 
NET ddr_dq(15) LOC = E18; # DDR_D15
322 
NET ddr_dq(16) LOC = F18; # DDR_D16
323 
NET ddr_dq(17) LOC = A19; # DDR_D17
324 
NET ddr_dq(18) LOC = F19; # DDR_D18
325 
NET ddr_dq(19) LOC = B23; # DDR_D19
326 
NET ddr_dq(20) LOC = E21; # DDR_D20
327 
NET ddr_dq(21) LOC = D22; # DDR_D21
328 
NET ddr_dq(22) LOC = D23; # DDR_D22
329 
NET ddr_dq(23) LOC = B24; # DDR_D23
330 
NET ddr_dq(24) LOC = E22; # DDR_D24
331 
NET ddr_dq(25) LOC = F20; # DDR_D25
332 
NET ddr_dq(26) LOC = H23; # DDR_D26
333 
NET ddr_dq(27) LOC = G25; # DDR_D27
334 
NET ddr_dq(28) LOC = G26; # DDR_D28
335 
NET ddr_dq(29) LOC = H25; # DDR_D29
336 
NET ddr_dq(30) LOC = H24; # DDR_D30
337 
NET ddr_dq(31) LOC = H21; # DDR_D31
338 
 
339 
NET ddr_ad(*)  IOSTANDARD = SSTL2_I;
340 
NET ddr_ba(*)  IOSTANDARD = SSTL2_I;
341 
NET ddr_casb   IOSTANDARD = SSTL2_I;
342 
NET ddr_cke    IOSTANDARD = SSTL2_I;
343 
NET ddr_clk    IOSTANDARD = SSTL2_I;
344 
NET ddr_clk_fb IOSTANDARD = LVCMOS25;
345 
NET ddr_clkb   IOSTANDARD = SSTL2_I;
346 
NET ddr_casb   IOSTANDARD = SSTL2_I;
347 
NET ddr_csb    IOSTANDARD = SSTL2_I;
348 
NET ddr_rasb   IOSTANDARD = SSTL2_I;
349 
NET ddr_web    IOSTANDARD = SSTL2_I;
350 
 
351 
NET ddr_dqs(*) IOSTANDARD = SSTL2_II;
352 
NET ddr_dm(*)  IOSTANDARD = SSTL2_II;
353 
NET ddr_dq(*)  IOSTANDARD = SSTL2_II;
354 
 
355 
// Timing Constraint for DDR Feedback Clock
356 
#NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
357 
#TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
358 
 
359 
#------------------------------------------------------------------------------
360 
# IO Pad Location Constraints / Properties for ADV7125 VGA Controller
361 
#------------------------------------------------------------------------------
362 
 
363 
NET vid_b(0) LOC = M21 | IOSTANDARD = LVCMOS33; # VGA_B0
364 
NET vid_b(1) LOC = M26 | IOSTANDARD = LVCMOS33; # VGA_B1
365 
NET vid_b(2) LOC = L26 | IOSTANDARD = LVCMOS33; # VGA_B2
366 
NET vid_b(3) LOC = C5 | IOSTANDARD = LVCMOS25;  # VGA_B3
367 
NET vid_b(4) LOC = C7 | IOSTANDARD = LVCMOS25;  # VGA_B4
368 
NET vid_b(5) LOC = B7 | IOSTANDARD = LVCMOS25;  # VGA_B5
369 
NET vid_b(6) LOC = G8 | IOSTANDARD = LVCMOS25;  # VGA_B6
370 
NET vid_b(7) LOC = F8 | IOSTANDARD = LVCMOS25;  # VGA_B7
371 
NET vid_b(*) SLEW = FAST;
372 
NET vid_b(*) DRIVE = 8;
373 
 
374 
NET tft_lcd_clk  LOC = AF8;
375 
NET tft_lcd_clk  IOSTANDARD = LVDCI_33;
376 
NET tft_lcd_clk  SLEW = FAST;
377 
NET tft_lcd_clk  DRIVE = 8;
378 
 
379 
NET vid_g(0) LOC = M22 | IOSTANDARD = LVCMOS33; # VGA_G0
380 
NET vid_g(1) LOC = M23 | IOSTANDARD = LVCMOS33; # VGA_G1
381 
NET vid_g(2) LOC = M20 | IOSTANDARD = LVCMOS33; # VGA_G2
382 
NET vid_g(3) LOC = E4 | IOSTANDARD = LVCMOS25;  # VGA_G3
383 
NET vid_g(4) LOC = D3 | IOSTANDARD = LVCMOS25;  # VGA_G4
384 
NET vid_g(5) LOC = H7 | IOSTANDARD = LVCMOS25;  # VGA_G5
385 
NET vid_g(6) LOC = H8 | IOSTANDARD = LVCMOS25;  # VGA_G6
386 
NET vid_g(7) LOC = C1 | IOSTANDARD = LVCMOS25;  # VGA_G7
387 
NET vid_g(*) SLEW = FAST;
388 
NET vid_g(*) DRIVE = 8;
389 
 
390 
NET vid_hsync LOC = C10 | IOSTANDARD = LVCMOS25;
391 
NET vid_hsync SLEW = FAST;
392 
NET vid_hsync DRIVE = 8;
393 
 
394 
NET vid_r(2) LOC = N23 | IOSTANDARD = LVCMOS33; #VGA_R0
395 
NET vid_r(2) LOC = N24 | IOSTANDARD = LVCMOS33; #VGA_R1
396 
NET vid_r(2) LOC = N25 | IOSTANDARD = LVCMOS33; #VGA_R2
397 
NET vid_r(3) LOC = C2 | IOSTANDARD = LVCMOS25; #VGA_R3
398 
NET vid_r(4) LOC = G7 | IOSTANDARD = LVCMOS25; #VGA_R4
399 
NET vid_r(5) LOC = F7 | IOSTANDARD = LVCMOS25; #VGA_R5
400 
NET vid_r(6) LOC = E5 | IOSTANDARD = LVCMOS25; #VGA_R6
401 
NET vid_r(7) LOC = E6 | IOSTANDARD = LVCMOS25; #VGA_R7
402 
NET vid_r(*) SLEW = FAST;
403 
NET vid_r(*) DRIVE = 8;
404 
 
405 
NET vid_vsync LOC = A8 | IOSTANDARD = LVCMOS25;
406 
NET vid_vsync SLEW = FAST;
407 
NET vid_vsync DRIVE = 8;
408 
 
409 
#TIMESPEC "TSPLB_TFT" = FROM "clkm" TO "tft_clk" TIG;
410 
#TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "clkm" TIG;
411 
 
412 
////////////////////////////////////////////////////////////////////////////
413 
// Misc Board Signals
414 
////////////////////////////////////////////////////////////////////////////
415 
 
416 
NET plb_error LOC = L24;
417 
NET plb_error IOSTANDARD = LVCMOS33;
418 
NET plb_error TIG;
419 
NET opb_error LOC = V6;
420 
NET opb_error IOSTANDARD = LVCMOS33;
421 
NET opb_error TIG;
422 
 
423 
#------------------------------------------------------------------------------
424 
# IO Pad Location Constraints / Properties for Ethernet
425 
#------------------------------------------------------------------------------
426 
 
427 
NET phy_col        LOC = E3 | IOSTANDARD = LVCMOS25;
428 
NET phy_crs        LOC = D5 | IOSTANDARD = LVCMOS25;
429 
NET phy_dv         LOC = A9 | IOSTANDARD = LVCMOS25;
430 
NET phy_rx_clk     LOC = B15 | IOSTANDARD = LVCMOS25;
431 
NET phy_rx_data(3) LOC = C4 | IOSTANDARD = LVCMOS25;
432 
NET phy_rx_data(2) LOC = D4 | IOSTANDARD = LVCMOS25;
433 
NET phy_rx_data(1) LOC = E1 | IOSTANDARD = LVCMOS25;
434 
NET phy_rx_data(0) LOC = F1 | IOSTANDARD = LVCMOS25;
435 
 
436 
NET phy_rx_er      LOC = B9 | IOSTANDARD = LVCMOS25;
437 
NET phy_tx_clk     LOC = C15 | IOSTANDARD = LVCMOS25;
438 
NET phy_mii_clk    LOC = D1 | IOSTANDARD = LVCMOS25;
439 
NET phy_rst_n      LOC = D10 | IOSTANDARD = LVCMOS25;
440 
NET phy_tx_data(3) LOC = G1 | IOSTANDARD = LVCMOS25;
441 
NET phy_tx_data(2) LOC = H3 | IOSTANDARD = LVCMOS25;
442 
NET phy_tx_data(1) LOC = H2 | IOSTANDARD = LVCMOS25;
443 
NET phy_tx_data(0) LOC = H1 | IOSTANDARD = LVCMOS25;
444 
NET phy_tx_en      LOC = F4 | IOSTANDARD = LVCMOS25;
445 
NET phy_tx_er      LOC = F3 | IOSTANDARD = LVCMOS25;
446 
NET phy_mii_data   LOC = G4 | IOSTANDARD = LVCMOS25;
447 
 
448 
#NET phy_mii_int_n  LOC = H4;
449 
#NET phy_mii_int_n  PULLUP;
450 
#NET phy_mii_int_n  TIG;
451 
 
452 
NET phy_rst_n      TIG;
453 
NET phy_mii_data   TIG;
454 
NET phy_mii_clk    TIG;
455 
 
456 
# Timing Constraints (these are recommended in documentation and
457 
# are unaltered except for the TIG)
458 
NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
459 
NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
460 
TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
461 
TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
462 
 
463 
NET "phy_tx_clk" MAXSKEW= 1.0 ns;
464 
NET "phy_rx_clk" MAXSKEW= 1.0 ns;
465 
NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
466 
NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
467 
 
468 
NET "phy_rx_data(3)" IOBDELAY=NONE;
469 
NET "phy_rx_data(2)" IOBDELAY=NONE;
470 
NET "phy_rx_data(1)" IOBDELAY=NONE;
471 
NET "phy_rx_data(0)" IOBDELAY=NONE;
472 
NET "phy_dv" IOBDELAY=NONE;
473 
NET "phy_rx_er" IOBDELAY=NONE;
474 
NET "phy_crs" IOBDELAY=NONE;
475 
NET "phy_col" IOBDELAY=NONE;
476 
 
477 
# Timing ignores (to specify unconstrained paths)
478 
#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "clkm" TIG;
479 
#TIMESPEC "TS_OPB_PHYTX" = FROM "clkm" TO "TXCLK_GRP" TIG;
480 
#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "clkm" TIG;
481 
#TIMESPEC "TS_OPB_PHYRX" = FROM "clkm" TO "RXCLK_GRP" TIG;
482 
 
483 
#------------------------------------------------------------------------------
484 
# IO Pad Location Constraints / Properties for SRAM/FLASH
485 
#------------------------------------------------------------------------------
486 
 
487 
NET sram_clk            LOC = AF7;
488 
NET sram_clk_fb         LOC = AD17;
489 
NET flash_a23           LOC = T21;
490 
NET sram_flash_addr(22) LOC = U20;
491 
NET sram_flash_addr(21) LOC = T19;
492 
NET sram_flash_addr(20) LOC = AC5;
493 
NET sram_flash_addr(19) LOC = AB5;
494 
NET sram_flash_addr(18) LOC = AC4;
495 
NET sram_flash_addr(17) LOC = AB4;
496 
 
497 
NET sram_flash_addr(16) LOC = AB3;
498 
NET sram_flash_addr(15) LOC = AA4;
499 
NET sram_flash_addr(14) LOC = AA3;
500 
NET sram_flash_addr(13) LOC = W5;
501 
NET sram_flash_addr(12) LOC = W6;
502 
NET sram_flash_addr(11) LOC = W3;
503 
NET sram_flash_addr(10) LOC = AF3;
504 
NET sram_flash_addr(9)  LOC = AE3;
505 
NET sram_flash_addr(8)  LOC = AD2;
506 
NET sram_flash_addr(7)  LOC = AD1;
507 
NET sram_flash_addr(6)  LOC = AC2;
508 
NET sram_flash_addr(5)  LOC = AC1;
509 
NET sram_flash_addr(4)  LOC = AB2;
510 
NET sram_flash_addr(3)  LOC = AB1;
511 
NET sram_flash_addr(2)  LOC = AA1;
512 
NET sram_flash_addr(1)  LOC = Y2;
513 
NET sram_flash_addr(0)  LOC = Y1;
514 
NET sram_flash_data(31) LOC = F14;
515 
NET sram_flash_data(30) LOC = F13;
516 
NET sram_flash_data(29) LOC = F12;
517 
NET sram_flash_data(28) LOC = F11;
518 
NET sram_flash_data(27) LOC = F16;
519 
NET sram_flash_data(26) LOC = F15;
520 
NET sram_flash_data(25) LOC = D14;
521 
NET sram_flash_data(24) LOC = D13;
522 
NET sram_flash_data(23) LOC = D15;
523 
NET sram_flash_data(22) LOC = E14;
524 
NET sram_flash_data(21) LOC = C11;
525 
NET sram_flash_data(20) LOC = D11;
526 
NET sram_flash_data(19) LOC = D16;
527 
NET sram_flash_data(18) LOC = C16;
528 
NET sram_flash_data(17) LOC = E13;
529 
NET sram_flash_data(16) LOC = D12;
530 
NET sram_flash_data(15) LOC = AA14;
531 
NET sram_flash_data(14) LOC = AB14;
532 
NET sram_flash_data(13) LOC = AC12;
533 
NET sram_flash_data(12) LOC = AC11;
534 
NET sram_flash_data(11) LOC = AA16;
535 
NET sram_flash_data(10) LOC = AA15;
536 
NET sram_flash_data(9)  LOC = AB13;
537 
NET sram_flash_data(8)  LOC = AA13;
538 
NET sram_flash_data(7)  LOC = AC14;
539 
NET sram_flash_data(6)  LOC = AD14;
540 
NET sram_flash_data(5)  LOC = AA12;
541 
NET sram_flash_data(4)  LOC = AA11;
542 
NET sram_flash_data(3)  LOC = AC16;
543 
NET sram_flash_data(2)  LOC = AC15;
544 
NET sram_flash_data(1)  LOC = AC13;
545 
NET sram_flash_data(0)  LOC = AD13;
546 
NET sram_cen            LOC = V7;
547 
NET sram_flash_oe_n     LOC = AC6;
548 
NET sram_flash_we_n     LOC = AB6;
549 
NET sram_bw(3)          LOC = Y3; #Y4;
550 
NET sram_bw(2)          LOC = Y4; #Y3;
551 
NET sram_bw(1)          LOC = Y5; #Y6;
552 
NET sram_bw(0)          LOC = Y6; #Y5;
553 
NET flash_ce            LOC = W7;
554 
NET sram_adv_ld_n       LOC = W4;
555 
NET sram_mode           LOC = V26;
556 
 
557 
NET sram_clk           IOSTANDARD = LVCMOS33;
558 
NET sram_clk           DRIVE = 16;
559 
NET sram_clk           SLEW = FAST;
560 
NET sram_clk_fb        IOSTANDARD = LVCMOS33;
561 
 
562 
NET flash_a23          IOSTANDARD = LVDCI_33;
563 
NET flash_a23  SLEW = FAST;
564 
NET flash_a23  DRIVE = 8;
565 
 
566 
NET sram_mode          IOSTANDARD = LVDCI_33;
567 
NET sram_mode SLEW = FAST;
568 
NET sram_mode DRIVE = 8;
569 
 
570 
NET sram_flash_addr(*) IOSTANDARD = LVDCI_33;
571 
NET sram_flash_addr(*)  SLEW = FAST;
572 
NET sram_flash_addr(*)  DRIVE = 8;
573 
 
574 
NET sram_flash_data(*) IOSTANDARD = LVCMOS33;
575 
NET sram_flash_data(*) DRIVE = 12;
576 
NET sram_flash_data(*) SLEW = FAST;
577 
NET sram_flash_data(*) PULLDOWN;
578 
 
579 
NET sram_flash_oe_n    IOSTANDARD = LVDCI_33;
580 
NET sram_flash_oe_n SLEW = FAST;
581 
NET sram_flash_oe_n DRIVE = 8;
582 
 
583 
NET sram_flash_we_n    IOSTANDARD = LVDCI_33;
584 
NET sram_flash_we_n SLEW = FAST;
585 
NET sram_flash_we_n DRIVE = 8;
586 
 
587 
NET sram_bw(*)         IOSTANDARD = LVDCI_33;
588 
NET sram_bw(*) SLEW = FAST;
589 
NET sram_bw(*) DRIVE = 8;
590 
 
591 
NET flash_ce           IOSTANDARD = LVDCI_33;
592 
NET flash_ce SLEW = FAST;
593 
NET flash_ce DRIVE = 8;
594 
 
595 
NET sram_cen           IOSTANDARD = LVDCI_33;
596 
NET sram_cen SLEW = FAST;
597 
NET sram_cen DRIVE = 8;
598 
 
599 
NET sram_adv_ld_n      IOSTANDARD = LVDCI_33;
600 
NET sram_adv_ld_n SLEW = FAST;
601 
NET sram_adv_ld_n DRIVE = 8;
602 
 
603 
#------------------------------------------------------------------------------
604 
# IO Pad Location Constraints / Properties for Expansion Header GPIO
605 
#------------------------------------------------------------------------------
606 
 
607 
NET gpio_exp_hdr1(31) LOC = AF24; # HDR1_64
608 
NET gpio_exp_hdr1(30) LOC = AE24; # HDR1_62
609 
NET gpio_exp_hdr1(29) LOC = AD22; # HDR1_8
610 
NET gpio_exp_hdr1(28) LOC = AB21; # HDR1_58
611 
NET gpio_exp_hdr1(27) LOC = W20;  # HDR1_44
612 
NET gpio_exp_hdr1(26) LOC = W21;  # HDR1_48
613 
NET gpio_exp_hdr1(25) LOC = AB22; # HDR1_14
614 
NET gpio_exp_hdr1(24) LOC = AD25; # HDR1_20
615 
NET gpio_exp_hdr1(23) LOC = W22;  # HDR1_46
616 
NET gpio_exp_hdr1(22) LOC = V21;  # HDR1_56
617 
NET gpio_exp_hdr1(21) LOC = V22;  # HDR1_54
618 
NET gpio_exp_hdr1(20) LOC = AC22; # HDR1_16
619 
NET gpio_exp_hdr1(19) LOC = AD26; # HDR1_18
620 
NET gpio_exp_hdr1(18) LOC = AC26; # HDR1_34
621 
NET gpio_exp_hdr1(17) LOC = AD23; # HDR1_6
622 
NET gpio_exp_hdr1(16) LOC = AB25; # HDR1_30
623 
NET gpio_exp_hdr1(15) LOC = AC23; # HDR1_4
624 
NET gpio_exp_hdr1(14) LOC = AB26; # HDR1_24
625 
NET gpio_exp_hdr1(13) LOC = AC21; # HDR1_60
626 
NET gpio_exp_hdr1(12) LOC = AA23; # HDR1_10
627 
NET gpio_exp_hdr1(11) LOC = AA26; # HDR1_22
628 
NET gpio_exp_hdr1(10) LOC = Y25;  # HDR1_40
629 
NET gpio_exp_hdr1(9)  LOC = Y26;  # HDR1_38
630 
NET gpio_exp_hdr1(8)  LOC = W26;  # HDR1_50
631 
NET gpio_exp_hdr1(7)  LOC = AB23; # HDR1_12
632 
NET gpio_exp_hdr1(6)  LOC = Y24;  # HDR1_26
633 
NET gpio_exp_hdr1(5)  LOC = AB24; # HDR1_32
634 
NET gpio_exp_hdr1(4)  LOC = W25;  # HDR1_52
635 
NET gpio_exp_hdr1(3)  LOC = AC24; # HDR1_2
636 
NET gpio_exp_hdr1(2)  LOC = AC25; # HDR1_36
637 
NET gpio_exp_hdr1(1)  LOC = V20;  # HDR1_42
638 
NET gpio_exp_hdr1(0)  LOC = AA24; # HDR1_28
639 
#NET gpio_exp_hdr1(*) TIG;
640 
#NET gpio_exp_hdr1(*) PULLDOWN;
641 
 
642 
NET gpio_exp_hdr2(31) LOC = AF18; # HDR2_40
643 
NET gpio_exp_hdr2(30) LOC = AE18; # HDR2_38
644 
NET gpio_exp_hdr2(29) LOC = AF19; # HDR2_32
645 
NET gpio_exp_hdr2(28) LOC = AF20; # HDR2_30
646 
NET gpio_exp_hdr2(27) LOC = AF21; # HDR2_44
647 
NET gpio_exp_hdr2(26) LOC = AF22; # HDR2_42
648 
NET gpio_exp_hdr2(25) LOC = AF23; # HDR2_24
649 
NET gpio_exp_hdr2(24) LOC = AE23; # HDR2_22
650 
NET gpio_exp_hdr2(23) LOC = AC18; # HDR2_48
651 
NET gpio_exp_hdr2(22) LOC = AB18; # HDR2_46
652 
NET gpio_exp_hdr2(21) LOC = AD19; # HDR2_64
653 
NET gpio_exp_hdr2(20) LOC = AC19; # HDR2_62
654 
NET gpio_exp_hdr2(19) LOC = AE20; # HDR2_16
655 
NET gpio_exp_hdr2(18) LOC = AD20; # HDR2_14
656 
NET gpio_exp_hdr2(17) LOC = AE21; # HDR2_36
657 
NET gpio_exp_hdr2(16) LOC = AD21; # HDR2_34
658 
NET gpio_exp_hdr2(15) LOC = AB20; # HDR2_52
659 
NET gpio_exp_hdr2(14) LOC = AC20; # HDR2_50
660 
NET gpio_exp_hdr2(13) LOC = Y17;  # HDR2_56
661 
NET gpio_exp_hdr2(12) LOC = AA17; # HDR2_54
662 
NET gpio_exp_hdr2(11) LOC = AA19; # HDR2_60
663 
NET gpio_exp_hdr2(10) LOC = AA20; # HDR2_58
664 
NET gpio_exp_hdr2(9)  LOC = Y22;  # HDR2_8
665 
NET gpio_exp_hdr2(8)  LOC = Y23;  # HDR2_6
666 
NET gpio_exp_hdr2(7)  LOC = W23;  # HDR2_12
667 
NET gpio_exp_hdr2(6)  LOC = W24;  # HDR2_10
668 
NET gpio_exp_hdr2(5)  LOC = Y20;  # HDR2_20
669 
NET gpio_exp_hdr2(4)  LOC = Y21;  # HDR2_18
670 
NET gpio_exp_hdr2(3)  LOC = Y19;  # HDR2_28
671 
NET gpio_exp_hdr2(2)  LOC = W19;  # HDR2_26
672 
NET gpio_exp_hdr2(1)  LOC = AA18; # HDR2_4
673 
NET gpio_exp_hdr2(0)  LOC = Y18;  # HDR2_2
674 
#NET gpio_exp_hdr2(*) TIG;
675 
#NET gpio_exp_hdr2(*) PULLDOWN;
676 
 
677 
#------------------------------------------------------------------------------
678 
# IO Pad Location Constraints / Properties for Character LCD GPIO
679 
#------------------------------------------------------------------------------
680 
 
681 
NET gpio_char_lcd(6) LOC = AE13; # LCD_E
682 
NET gpio_char_lcd(5) LOC = AC17; # LCD_RS
683 
NET gpio_char_lcd(4) LOC = AB17; # LCD_RW
684 
NET gpio_char_lcd(3) LOC = AF12; # LCD_DB7
685 
NET gpio_char_lcd(2) LOC = AE12; # LCD_DB6
686 
NET gpio_char_lcd(1) LOC = AC10; # LCD_DB5
687 
NET gpio_char_lcd(0) LOC = AB10; # LCD_DB4
688 
NET gpio_char_lcd(*) IOSTANDARD = LVCMOS33;
689 
#NET gpio_char_lcd(*) TIG;
690 
#NET gpio_char_lcd(*) PULLDOWN;

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