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dimamali |
------------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2008 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.net.all;
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use gaisler.ata.all;
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use gaisler.jtag.all;
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library esa;
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use esa.memoryctrl.all;
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use work.config.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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ncpu : integer := CFG_NCPU;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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freq : integer := 50000 -- frequency of main clock (used for PLLs)
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);
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port (
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resetn : in std_ulogic;
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clk : in std_ulogic;
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errorn : out std_ulogic;
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-- flash/ssram bus
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address : out std_logic_vector(25 downto 1);
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data : inout std_logic_vector(31 downto 0);
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romsn : out std_ulogic;
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oen : out std_logic;
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writen : out std_logic;
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rstoutn : out std_ulogic;
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ssram_cen : out std_logic;
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ssram_wen : out std_logic;
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ssram_bw : out std_logic_vector (0 to 3);
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ssram_oen : out std_ulogic;
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ssram_clk : out std_ulogic;
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ssram_adscn : out std_ulogic;
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-- ssram_adsp_n : out std_ulogic;
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-- ssram_adv_n : out std_ulogic;
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-- pragma translate_off
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iosn : out std_ulogic;
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-- pragma translate_on
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-- DDR
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ddr_clk : out std_logic;
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ddr_clkn : out std_logic;
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ddr_cke : out std_logic;
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ddr_csb : out std_logic;
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
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-- debug support unit
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dsubren : in std_ulogic;
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dsuact : out std_ulogic;
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-- I/O port
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gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
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-- Connections over HSMC connector
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-- LCD touch panel display
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hc_vd : out std_logic;
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hc_hd : out std_logic;
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hc_den : out std_logic;
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hc_nclk : out std_logic;
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hc_lcd_data : out std_logic_vector(7 downto 0);
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hc_grest : out std_logic;
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hc_scen : out std_logic;
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hc_sda : inout std_logic;
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hc_adc_penirq_n : in std_logic;
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hc_adc_dout : in std_logic;
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hc_adc_busy : in std_logic;
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hc_adc_din : out std_logic;
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hc_adc_dclk : out std_logic;
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hc_adc_cs_n : out std_logic; -- Shared with video decoder
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-- Shared by video decoder and audio codec
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hc_i2c_sclk : out std_logic;
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hc_i2c_sdat : inout std_logic;
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-- Video decoder
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hc_td_d : inout std_logic_vector(7 downto 0);
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hc_td_hs : in std_logic;
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hc_td_vs : in std_logic;
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hc_td_27mhz : in std_logic;
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hc_td_reset : out std_logic;
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-- Audio codec
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hc_aud_adclrck : out std_logic;
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hc_aud_adcdat : in std_logic;
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hc_aud_daclrck : out std_logic;
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hc_aud_dacdat : out std_logic;
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hc_aud_bclk : out std_logic;
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hc_aud_xck : out std_logic;
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-- SD card
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hc_sd_dat : inout std_logic;
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hc_sd_dat3 : inout std_logic;
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hc_sd_cmd : inout std_logic;
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hc_sd_clk : inout std_logic;
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-- Ethernet PHY
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hc_tx_d : out std_logic_vector(3 downto 0);
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hc_rx_d : in std_logic_vector(3 downto 0);
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hc_tx_clk : in std_logic;
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hc_rx_clk : in std_logic;
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hc_tx_en : out std_logic;
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hc_rx_dv : in std_logic;
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hc_rx_crs : in std_logic;
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hc_rx_err : in std_logic;
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hc_rx_col : in std_logic;
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hc_mdio : inout std_logic;
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hc_mdc : out std_logic;
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hc_eth_reset_n : out std_logic;
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-- RX232 (console/debug UART)
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hc_uart_rxd : in std_logic;
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hc_uart_txd : out std_logic;
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-- PS/2
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hc_ps2_dat : inout std_logic;
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hc_ps2_clk : inout std_logic;
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-- VGA/DAC
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hc_vga_data : out std_logic_vector(9 downto 0);
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hc_vga_clock : out std_ulogic;
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hc_vga_hs : out std_ulogic;
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hc_vga_vs : out std_ulogic;
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hc_vga_blank : out std_ulogic;
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hc_vga_sync : out std_ulogic;
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-- I2C EEPROM
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hc_id_i2cscl : out std_logic;
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hc_id_i2cdat : inout std_logic
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);
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end;
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architecture rtl of leon3mp is
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component serializer
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generic (
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length : integer := 8 -- vector length
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);
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port (
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clk : in std_ulogic;
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sync : in std_ulogic;
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ivec0 : in std_logic_vector((length-1) downto 0);
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ivec1 : in std_logic_vector((length-1) downto 0);
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ivec2 : in std_logic_vector((length-1) downto 0);
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ovec : out std_logic_vector((length-1) downto 0)
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);
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end component;
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component altera_eek_clkgen
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generic (
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clk0_mul : integer := 1;
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clk0_div : integer := 1;
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clk1_mul : integer := 1;
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clk1_div : integer := 1;
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clk_freq : integer := 25000);
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port (
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inclk0 : in std_ulogic;
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clk0 : out std_ulogic;
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clk0x3 : out std_ulogic;
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clksel : in std_logic_vector(1 downto 0);
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locked : out std_ulogic);
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end component;
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+
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CFG_SVGA_ENABLE+CFG_GRETH;
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signal vcc, gnd : std_logic_vector(7 downto 0);
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signal memi, smemi : memory_in_type;
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signal memo, smemo : memory_out_type;
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signal wpo : wprot_out_type;
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signal ddsi : ddrmem_in_type;
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signal ddso : ddrmem_out_type;
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signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
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signal ddr_clkv : std_logic_vector(2 downto 0);
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signal ddr_clkbv : std_logic_vector(2 downto 0);
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signal ddr_ckev : std_logic_vector(1 downto 0);
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signal ddr_csbv : std_logic_vector(1 downto 0);
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signal ddr_adl : std_logic_vector (13 downto 0);
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signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
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signal tck, tckn, tms, tdi, tdo : std_ulogic;
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signal ddrclk, ddrrst : std_ulogic;
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal clkm, rstn, rawrstn, ssram_clkl : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal u1i, dui : uart_in_type;
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signal u1o, duo : uart_out_type;
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signal irqi : irq_in_vector(0 to NCPU-1);
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signal irqo : irq_out_vector(0 to NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal gpti : gptimer_in_type;
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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signal ps2i : ps2_in_type;
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signal ps2o : ps2_out_type;
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signal i2ci : i2c_in_type;
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signal i2co : i2c_out_type;
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signal spii : spi_in_type;
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signal spio : spi_out_type;
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signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
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signal spmi : spimctrl_in_type;
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signal spmo : spimctrl_out_type;
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signal ethi : eth_in_type;
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signal etho : eth_out_type;
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signal lcdo : apbvga_out_type;
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signal lcd_data : std_logic_vector(7 downto 0);
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signal lcd_den : std_ulogic;
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signal lcd_grest : std_ulogic;
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signal lcdspii : spi_in_type;
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signal lcdspio : spi_out_type;
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signal lcdslvsel : std_logic_vector(1 downto 0);
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signal lcdclksel : std_logic_vector(1 downto 0);
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signal lcdclk : std_ulogic;
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signal lcdclk3x : std_ulogic;
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signal lcdclklck : std_ulogic;
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signal vgao : apbvga_out_type;
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signal vga_data : std_logic_vector(9 downto 0);
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signal vgaclksel : std_logic_vector(1 downto 0);
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signal vgaclk : std_ulogic;
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signal vgaclk3x : std_ulogic;
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signal vgaclklck : std_ulogic;
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constant IOAEN : integer := 1;
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constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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signal lclk, lclkout : std_ulogic;
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signal dsubre : std_ulogic;
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attribute syn_keep : boolean;
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attribute syn_keep of clkm : signal is true;
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attribute syn_keep of clkml : signal is true;
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attribute syn_keep of lcdclk : signal is true;
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attribute syn_keep of lcdclk3x : signal is true;
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attribute syn_keep of vgaclk : signal is true;
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attribute syn_keep of vgaclk3x : signal is true;
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begin
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
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clklock <= cgo.clklock and lock and lcdclklck and vgaclklck;
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clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
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clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
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generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
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clk_div => CFG_CLKDIV, sdramen => 1,
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freq => freq)
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port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
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clk2x => open, sdclk => ssram_clkl, pciclk => open,
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cgi => cgi, cgo => cgo);
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|
|
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
|
327 |
|
|
port map (ssram_clk, ssram_clkl);
|
328 |
|
|
|
329 |
|
|
rst0 : rstgen -- reset generator
|
330 |
|
|
port map (resetn, clkm, clklock, rstn, rawrstn);
|
331 |
|
|
|
332 |
|
|
rstoutn <= resetn;
|
333 |
|
|
|
334 |
|
|
----------------------------------------------------------------------
|
335 |
|
|
--- AVOID BUS CONTENTION --------------------------------------------
|
336 |
|
|
----------------------------------------------------------------------
|
337 |
|
|
-- This design uses the ethernet PHY and we must therefore disable the
|
338 |
|
|
-- video decoder and stay away from the touch panel.
|
339 |
|
|
-- Video coder
|
340 |
|
|
hc_td_reset <= '0'; -- Video Decoder Reset
|
341 |
|
|
|
342 |
|
|
----------------------------------------------------------------------
|
343 |
|
|
--- AHB CONTROLLER --------------------------------------------------
|
344 |
|
|
----------------------------------------------------------------------
|
345 |
|
|
|
346 |
|
|
ahb0 : ahbctrl -- AHB arbiter/multiplexer
|
347 |
|
|
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
|
348 |
|
|
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
|
349 |
|
|
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
|
350 |
|
|
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
|
351 |
|
|
|
352 |
|
|
----------------------------------------------------------------------
|
353 |
|
|
--- LEON3 processor and DSU -----------------------------------------
|
354 |
|
|
----------------------------------------------------------------------
|
355 |
|
|
|
356 |
|
|
l3 : if CFG_LEON3 = 1 generate
|
357 |
|
|
cpu : for i in 0 to NCPU-1 generate
|
358 |
|
|
u0 : leon3s -- LEON3 processor
|
359 |
|
|
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
|
360 |
|
|
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
|
361 |
|
|
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
|
362 |
|
|
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
|
363 |
|
|
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
|
364 |
|
|
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
|
365 |
|
|
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
|
366 |
|
|
irqi(i), irqo(i), dbgi(i), dbgo(i));
|
367 |
|
|
end generate;
|
368 |
|
|
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
|
369 |
|
|
|
370 |
|
|
dsugen : if CFG_DSU = 1 generate
|
371 |
|
|
dsu0 : dsu3 -- LEON3 Debug Support Unit
|
372 |
|
|
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
|
373 |
|
|
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
|
374 |
|
|
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
|
375 |
|
|
|
376 |
|
|
dsui.enable <= '1';
|
377 |
|
|
|
378 |
|
|
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
|
379 |
|
|
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
|
380 |
|
|
end generate;
|
381 |
|
|
end generate;
|
382 |
|
|
nodcom : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; end generate;
|
383 |
|
|
|
384 |
|
|
dcomgen : if CFG_AHB_UART = 1 generate
|
385 |
|
|
dcom0 : ahbuart -- Debug UART
|
386 |
|
|
generic map (hindex => NCPU, pindex => 7, paddr => 7)
|
387 |
|
|
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
|
388 |
|
|
dsurx_pad : inpad generic map (tech => padtech) port map (hc_uart_rxd, dui.rxd);
|
389 |
|
|
dsutx_pad : outpad generic map (tech => padtech) port map (hc_uart_txd, duo.txd);
|
390 |
|
|
end generate;
|
391 |
|
|
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
|
392 |
|
|
|
393 |
|
|
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
|
394 |
|
|
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
|
395 |
|
|
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
|
396 |
|
|
open, open, open, open, open, open, open, gnd(0));
|
397 |
|
|
end generate;
|
398 |
|
|
|
399 |
|
|
----------------------------------------------------------------------
|
400 |
|
|
--- Memory controllers ----------------------------------------------
|
401 |
|
|
----------------------------------------------------------------------
|
402 |
|
|
|
403 |
|
|
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
|
404 |
|
|
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
|
405 |
|
|
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
|
406 |
|
|
sden => 0, ram16 => 1)
|
407 |
|
|
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
|
408 |
|
|
end generate;
|
409 |
|
|
|
410 |
|
|
memi.brdyn <= '1'; memi.bexcn <= '1';
|
411 |
|
|
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
|
412 |
|
|
|
413 |
|
|
ssr0 : if CFG_SSCTRL = 1 generate
|
414 |
|
|
ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
|
415 |
|
|
iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
|
416 |
|
|
bus16 => CFG_SSCTRLP16)
|
417 |
|
|
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
|
418 |
|
|
end generate;
|
419 |
|
|
|
420 |
|
|
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
|
421 |
|
|
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
|
422 |
|
|
roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
|
423 |
|
|
end generate;
|
424 |
|
|
|
425 |
|
|
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
|
426 |
|
|
addr_pad : outpadv generic map (width => 25, tech => padtech)
|
427 |
|
|
port map (address, memo.address(25 downto 1));
|
428 |
|
|
roms_pad : outpad generic map (tech => padtech)
|
429 |
|
|
port map (romsn, memo.romsn(0));
|
430 |
|
|
oen_pad : outpad generic map (tech => padtech)
|
431 |
|
|
port map (oen, memo.oen);
|
432 |
|
|
wri_pad : outpad generic map (tech => padtech)
|
433 |
|
|
port map (writen, memo.writen);
|
434 |
|
|
-- pragma translate_off
|
435 |
|
|
iosn_pad : outpad generic map (tech => padtech)
|
436 |
|
|
port map (iosn, memo.iosn);
|
437 |
|
|
-- pragma translate_on
|
438 |
|
|
|
439 |
|
|
-- ssram_adv_n_pad : outpad generic map (tech => padtech)
|
440 |
|
|
-- port map (ssram_adv_n, vcc(0));
|
441 |
|
|
-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
|
442 |
|
|
-- port map (ssram_adsp_n, gnd(0));
|
443 |
|
|
ssram_adscn_pad : outpad generic map (tech => padtech)
|
444 |
|
|
port map (ssram_adscn, gnd(0));
|
445 |
|
|
ssrams_pad : outpad generic map ( tech => padtech)
|
446 |
|
|
port map (ssram_cen, memo.ramsn(0));
|
447 |
|
|
ssram_oen_pad : outpad generic map (tech => padtech)
|
448 |
|
|
port map (ssram_oen, memo.oen);
|
449 |
|
|
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
|
450 |
|
|
port map (ssram_bw, memo.wrn);
|
451 |
|
|
ssram_wri_pad : outpad generic map (tech => padtech)
|
452 |
|
|
port map (ssram_wen, memo.writen);
|
453 |
|
|
data_pad : iopadvv generic map (tech => padtech, width => 32)
|
454 |
|
|
port map (data(31 downto 0), memo.data(31 downto 0),
|
455 |
|
|
memo.vbdrive, memi.data(31 downto 0));
|
456 |
|
|
end generate;
|
457 |
|
|
|
458 |
|
|
ddrsp0 : if (CFG_DDRSP /= 0) generate
|
459 |
|
|
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
|
460 |
|
|
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
|
461 |
|
|
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
|
462 |
|
|
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
|
463 |
|
|
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
|
464 |
|
|
port map (
|
465 |
|
|
resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
|
466 |
|
|
ddr_clkv, ddr_clkbv, open, gnd(0),
|
467 |
|
|
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
|
468 |
|
|
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
|
469 |
|
|
ddr_ad <= ddr_adl(12 downto 0);
|
470 |
|
|
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
|
471 |
|
|
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
|
472 |
|
|
end generate;
|
473 |
|
|
|
474 |
|
|
ddrsp1 : if (CFG_DDRSP = 0) generate
|
475 |
|
|
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
|
476 |
|
|
end generate;
|
477 |
|
|
|
478 |
|
|
spimc: if CFG_SPIMCTRL = 1 generate -- SPI Memory Controller
|
479 |
|
|
spimctrl0 : spimctrl
|
480 |
|
|
generic map (hindex => 4,
|
481 |
|
|
hirq => 9,
|
482 |
|
|
faddr => 16#b00#,
|
483 |
|
|
fmask => 16#f00#,
|
484 |
|
|
ioaddr => 16#002#,
|
485 |
|
|
iomask => 16#fff#,
|
486 |
|
|
spliten => CFG_SPLIT,
|
487 |
|
|
oepol => 0,
|
488 |
|
|
sdcard => CFG_SPIMCTRL_SDCARD,
|
489 |
|
|
readcmd => CFG_SPIMCTRL_READCMD,
|
490 |
|
|
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
|
491 |
|
|
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
|
492 |
|
|
scaler => CFG_SPIMCTRL_SCALER,
|
493 |
|
|
altscaler => CFG_SPIMCTRL_ASCALER,
|
494 |
|
|
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
|
495 |
|
|
port map (rstn, clkm, ahbsi, ahbso(4), spmi, spmo);
|
496 |
|
|
|
497 |
|
|
miso_pad : inpad generic map (tech => padtech)
|
498 |
|
|
port map (hc_sd_dat, spmi.miso);
|
499 |
|
|
mosi_pad : outpad generic map (tech => padtech)
|
500 |
|
|
port map (hc_sd_cmd, spmo.mosi);
|
501 |
|
|
sck_pad : outpad generic map (tech => padtech)
|
502 |
|
|
port map (hc_sd_clk, spmo.sck);
|
503 |
|
|
slvsel0_pad : iopad generic map (tech => padtech)
|
504 |
|
|
port map (hc_sd_dat3, spmo.csn, spmo.cdcsnoen, spmi.cd);
|
505 |
|
|
end generate;
|
506 |
|
|
|
507 |
|
|
----------------------------------------------------------------------
|
508 |
|
|
--- APB Bridge and various periherals -------------------------------
|
509 |
|
|
----------------------------------------------------------------------
|
510 |
|
|
|
511 |
|
|
apb0 : apbctrl -- AHB/APB bridge
|
512 |
|
|
generic map (hindex => 1, haddr => CFG_APBADDR)
|
513 |
|
|
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
|
514 |
|
|
|
515 |
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
516 |
|
|
uart1 : apbuart -- UART 1
|
517 |
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
518 |
|
|
fifosize => CFG_UART1_FIFO)
|
519 |
|
|
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
|
520 |
|
|
u1i.ctsn <= '0'; u1i.extclk <= '0';
|
521 |
|
|
upads : if CFG_AHB_UART = 0 generate
|
522 |
|
|
u1i.rxd <= hc_uart_rxd; hc_uart_txd <= u1o.txd;
|
523 |
|
|
end generate;
|
524 |
|
|
end generate;
|
525 |
|
|
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
|
526 |
|
|
|
527 |
|
|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
|
528 |
|
|
irqctrl0 : irqmp -- interrupt controller
|
529 |
|
|
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
|
530 |
|
|
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
|
531 |
|
|
end generate;
|
532 |
|
|
irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
533 |
|
|
x : for i in 0 to NCPU-1 generate
|
534 |
|
|
irqi(i).irl <= "0000";
|
535 |
|
|
end generate;
|
536 |
|
|
apbo(2) <= apb_none;
|
537 |
|
|
end generate;
|
538 |
|
|
|
539 |
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
540 |
|
|
timer0 : gptimer -- Timer unit
|
541 |
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
542 |
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
543 |
|
|
nbits => CFG_GPT_TW)
|
544 |
|
|
port map (rstn, clkm, apbi, apbo(3), gpti, open);
|
545 |
|
|
gpti.dhalt <= dsuo.active; gpti.extclk <= '0';
|
546 |
|
|
end generate;
|
547 |
|
|
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
548 |
|
|
|
549 |
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
|
550 |
|
|
grgpio0: grgpio
|
551 |
|
|
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
|
552 |
|
|
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
|
553 |
|
|
gpioi => gpioi, gpioo => gpioo);
|
554 |
|
|
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-3 generate
|
555 |
|
|
gpioi.din(i) <= gpio(i);
|
556 |
|
|
end generate;
|
557 |
|
|
gpioi.din(3) <= hc_adc_penirq_n;
|
558 |
|
|
gpioi.din(4) <= hc_adc_busy;
|
559 |
|
|
end generate;
|
560 |
|
|
|
561 |
|
|
ps2 : if CFG_PS2_ENABLE /= 0 generate -- PS/2 unit
|
562 |
|
|
ps20 : apbps2 generic map(pindex => 6, paddr => 6, pirq => 6)
|
563 |
|
|
port map(rstn, clkm, apbi, apbo(6), ps2i, ps2o);
|
564 |
|
|
end generate;
|
565 |
|
|
nops2 : if CFG_PS2_ENABLE = 0 generate
|
566 |
|
|
apbo(4) <= apb_none; ps2o <= ps2o_none;
|
567 |
|
|
end generate;
|
568 |
|
|
ps2clk_pad : iopad generic map (tech => padtech)
|
569 |
|
|
port map (hc_ps2_clk, ps2o.ps2_clk_o, ps2o.ps2_clk_oe, ps2i.ps2_clk_i);
|
570 |
|
|
ps2data_pad : iopad generic map (tech => padtech)
|
571 |
|
|
port map (hc_ps2_dat, ps2o.ps2_data_o, ps2o.ps2_data_oe, ps2i.ps2_data_i);
|
572 |
|
|
|
573 |
|
|
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
|
574 |
|
|
i2c0 : i2cmst
|
575 |
|
|
generic map (pindex => 8, paddr => 8, pmask => 16#FFF#, pirq => 11)
|
576 |
|
|
port map (rstn, clkm, apbi, apbo(8), i2ci, i2co);
|
577 |
|
|
-- The EEK does not use a bi-directional line for the I2C clock
|
578 |
|
|
i2ci.scl <= i2co.scloen; -- No clock stretch possible
|
579 |
|
|
-- When SCL output enable is activated the line should go low
|
580 |
|
|
i2c_scl_pad : outpad generic map (tech => padtech)
|
581 |
|
|
port map (hc_id_i2cscl, i2co.scloen);
|
582 |
|
|
i2c_sda_pad : iopad generic map (tech => padtech)
|
583 |
|
|
port map (hc_id_i2cdat, i2co.sda, i2co.sdaoen, i2ci.sda);
|
584 |
|
|
end generate i2cm;
|
585 |
|
|
|
586 |
|
|
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
|
587 |
|
|
spi1 : spictrl
|
588 |
|
|
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 9,
|
589 |
|
|
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
|
590 |
|
|
slvselsz => CFG_SPICTRL_SLVS)
|
591 |
|
|
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
|
592 |
|
|
miso_pad : iopad generic map (tech => padtech)
|
593 |
|
|
port map (hc_sd_dat, spio.miso, spio.misooen, spii.miso);
|
594 |
|
|
mosi_pad : iopad generic map (tech => padtech)
|
595 |
|
|
port map (hc_sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
|
596 |
|
|
sck_pad : iopad generic map (tech => padtech)
|
597 |
|
|
port map (hc_sd_clk, spio.sck, spio.sckoen, spii.sck);
|
598 |
|
|
slvsel_pad : outpad generic map (tech => padtech)
|
599 |
|
|
port map (hc_sd_dat3, slvsel(0));
|
600 |
|
|
spii.spisel <= '1'; -- Master only
|
601 |
|
|
end generate spic;
|
602 |
|
|
|
603 |
|
|
-----------------------------------------------------------------------
|
604 |
|
|
-- LCD touch panel ---------------------------------------------------
|
605 |
|
|
-----------------------------------------------------------------------
|
606 |
|
|
|
607 |
|
|
lcd: if CFG_LCD_ENABLE /= 0 generate -- LCD
|
608 |
|
|
lcd0 : svgactrl generic map(memtech => memtech, pindex => 11, paddr => 11,
|
609 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
|
610 |
|
|
clk0 => 30120, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 4)
|
611 |
|
|
port map(rstn, clkm, lcdclk, apbi, apbo(11), lcdo, ahbmi,
|
612 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
|
613 |
|
|
|
614 |
|
|
lcdser0: serializer generic map (length => 8)
|
615 |
|
|
port map (lcdclk3x, lcdo.hsync, lcdo.video_out_b, lcdo.video_out_g,
|
616 |
|
|
lcdo.video_out_r, lcd_data);
|
617 |
|
|
|
618 |
|
|
lcdclksel <= "00";
|
619 |
|
|
|
620 |
|
|
lcdclkgen : altera_eek_clkgen
|
621 |
|
|
generic map (clk0_mul => 166, clk0_div => 250, clk1_mul => 9,
|
622 |
|
|
clk1_div => 50, clk_freq => BOARD_FREQ)
|
623 |
|
|
port map (lclk, lcdclk, lcdclk3x, lcdclksel, lcdclklck);
|
624 |
|
|
|
625 |
|
|
lcd_vert_sync_pad : outpad generic map (tech => padtech)
|
626 |
|
|
port map (hc_vd, lcdo.vsync);
|
627 |
|
|
lcd_horiz_sync_pad : outpad generic map (tech => padtech)
|
628 |
|
|
port map (hc_hd, lcdo.hsync);
|
629 |
|
|
lcd_video_out_pad : outpadv generic map (width => 8, tech => padtech)
|
630 |
|
|
port map (hc_lcd_data, lcd_data);
|
631 |
|
|
lcd_video_clock_pad : outpad generic map (tech => padtech)
|
632 |
|
|
port map (hc_nclk, lcdclk3x);
|
633 |
|
|
lcd_den <= lcdo.blank;
|
634 |
|
|
end generate;
|
635 |
|
|
|
636 |
|
|
nolcd : if CFG_LCD_ENABLE = 0 generate
|
637 |
|
|
apbo(11) <= apb_none; lcdo <= vgao_none;
|
638 |
|
|
lcd_den <= '0'; -- LCD RGB Data Enable
|
639 |
|
|
lcdclk <= '0'; lcdclk3x <= '0'; lcdclklck <= '1';
|
640 |
|
|
end generate;
|
641 |
|
|
|
642 |
|
|
lcd_den_pad : outpad generic map (tech => padtech)
|
643 |
|
|
port map (hc_den, lcd_den);
|
644 |
|
|
|
645 |
|
|
lcdsysreset: if CFG_LCD_ENABLE /= 0 or CFG_LCD3T_ENABLE /= 0 generate
|
646 |
|
|
lcd_grest <= rstn;
|
647 |
|
|
end generate;
|
648 |
|
|
|
649 |
|
|
lcdalwaysreset: if CFG_LCD_ENABLE = 0 and CFG_LCD3T_ENABLE = 0 generate
|
650 |
|
|
lcd_grest <= '0';
|
651 |
|
|
end generate lcdalwaysreset;
|
652 |
|
|
|
653 |
|
|
lcd_reset_pad : outpad generic map (tech => padtech) -- LCD Global Reset, active low
|
654 |
|
|
port map (hc_grest, lcd_grest);
|
655 |
|
|
|
656 |
|
|
touch3wire: if CFG_LCD3T_ENABLE /= 0 generate -- LCD 3-wire and touch panel interface
|
657 |
|
|
-- TODO:
|
658 |
|
|
-- Interrupt and busy signals not connected
|
659 |
|
|
touch3spi1 : spictrl
|
660 |
|
|
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
|
661 |
|
|
fdepth => 2, slvselen => 1, slvselsz => 2)
|
662 |
|
|
port map (rstn, clkm, apbi, apbo(12), lcdspii, lcdspio, lcdslvsel);
|
663 |
|
|
adc_miso_pad : inpad generic map (tech => padtech)
|
664 |
|
|
port map (hc_adc_dout, lcdspii.miso);
|
665 |
|
|
adc_mosi_pad : outpad generic map (tech => padtech)
|
666 |
|
|
port map (hc_adc_din, lcdspio.mosi);
|
667 |
|
|
lcd_adc_dclk_pad : outpad generic map (tech => padtech)
|
668 |
|
|
port map (hc_adc_dclk, lcdspio.sck);
|
669 |
|
|
hcd_sda_pad : iopad generic map (tech => padtech)
|
670 |
|
|
port map (hc_sda, lcdspio.mosi, lcdspio.mosioen, lcdspii.mosi);
|
671 |
|
|
|
672 |
|
|
lcdspii.spisel <= '1'; -- Master only
|
673 |
|
|
end generate;
|
674 |
|
|
|
675 |
|
|
notouch3wire: if CFG_LCD3T_ENABLE = 0 generate
|
676 |
|
|
lcdslvsel <= (others => '1');
|
677 |
|
|
apbo(12) <= apb_none;
|
678 |
|
|
end generate;
|
679 |
|
|
|
680 |
|
|
hc_adc_cs_n_pad : outpad generic map (tech => padtech)
|
681 |
|
|
port map (hc_adc_cs_n, lcdslvsel(0));
|
682 |
|
|
hc_scen_pad : outpad generic map (tech => padtech)
|
683 |
|
|
port map (hc_scen, lcdslvsel(1));
|
684 |
|
|
|
685 |
|
|
-----------------------------------------------------------------------
|
686 |
|
|
-- SVGA controller ----------------------------------------------------
|
687 |
|
|
-----------------------------------------------------------------------
|
688 |
|
|
|
689 |
|
|
svga : if CFG_SVGA_ENABLE /= 0 generate -- VGA DAC
|
690 |
|
|
svga0 : svgactrl generic map(memtech => memtech, pindex => 13, paddr => 13,
|
691 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE,
|
692 |
|
|
clk0 => 40000, clk1 => 25000, clk2 => 0, clk3 => 0, burstlen => 4)
|
693 |
|
|
port map(rstn, clkm, vgaclk, apbi, apbo(13), vgao, ahbmi,
|
694 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE),
|
695 |
|
|
vgaclksel);
|
696 |
|
|
|
697 |
|
|
svgaser0: serializer generic map (length => 8)
|
698 |
|
|
port map (vgaclk3x, vgao.hsync, vgao.video_out_b, vgao.video_out_g,
|
699 |
|
|
vgao.video_out_r, vga_data(9 downto 2));
|
700 |
|
|
vga_data(1 downto 0) <= (others => '0');
|
701 |
|
|
|
702 |
|
|
vgaclkgen : altera_eek_clkgen
|
703 |
|
|
generic map (clk0_mul => 1, clk0_div => 2, clk1_mul => 4,
|
704 |
|
|
clk1_div => 5, clk_freq => BOARD_FREQ)
|
705 |
|
|
port map (lclk, vgaclk, vgaclk3x, vgaclksel, vgaclklck);
|
706 |
|
|
|
707 |
|
|
vga_blank_pad : outpad generic map (tech => padtech)
|
708 |
|
|
port map (hc_vga_blank, vgao.blank);
|
709 |
|
|
vga_comp_sync_pad : outpad generic map (tech => padtech)
|
710 |
|
|
port map (hc_vga_sync, vgao.comp_sync);
|
711 |
|
|
vga_vert_sync_pad : outpad generic map (tech => padtech)
|
712 |
|
|
port map (hc_vga_vs, vgao.vsync);
|
713 |
|
|
vga_horiz_sync_pad : outpad generic map (tech => padtech)
|
714 |
|
|
port map (hc_vga_hs, vgao.hsync);
|
715 |
|
|
vga_video_out_pad : outpadv generic map (width => 10, tech => padtech)
|
716 |
|
|
port map (hc_vga_data, vga_data);
|
717 |
|
|
vga_video_clock_pad : outpad generic map (tech => padtech)
|
718 |
|
|
port map (hc_vga_clock, vgaclk3x);
|
719 |
|
|
end generate svga;
|
720 |
|
|
|
721 |
|
|
nosvga : if CFG_SVGA_ENABLE = 0 generate
|
722 |
|
|
apbo(13) <= apb_none; vgao <= vgao_none;
|
723 |
|
|
vgaclk <= '0'; vgaclk3x <= '0'; vgaclklck <= '1';
|
724 |
|
|
end generate;
|
725 |
|
|
|
726 |
|
|
-----------------------------------------------------------------------
|
727 |
|
|
--- ETHERNET ---------------------------------------------------------
|
728 |
|
|
-----------------------------------------------------------------------
|
729 |
|
|
|
730 |
|
|
eth0 : if CFG_GRETH /= 0 generate -- Gaisler ethernet MAC
|
731 |
|
|
e1 : grethm generic map(
|
732 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE,
|
733 |
|
|
pindex => 10, paddr => 10, pirq => 10, memtech => memtech,
|
734 |
|
|
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
|
735 |
|
|
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
|
736 |
|
|
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
|
737 |
|
|
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
|
738 |
|
|
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
|
739 |
|
|
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE),
|
740 |
|
|
apbi => apbi, apbo => apbo(10), ethi => ethi, etho => etho);
|
741 |
|
|
|
742 |
|
|
emdio_pad : iopad generic map (tech => padtech)
|
743 |
|
|
port map (hc_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
|
744 |
|
|
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
|
745 |
|
|
port map (hc_tx_clk, ethi.tx_clk);
|
746 |
|
|
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
|
747 |
|
|
port map (hc_rx_clk, ethi.rx_clk);
|
748 |
|
|
erxd_pad : inpadv generic map (tech => padtech, width => 4)
|
749 |
|
|
port map (hc_rx_d, ethi.rxd(3 downto 0));
|
750 |
|
|
erxdv_pad : inpad generic map (tech => padtech)
|
751 |
|
|
port map (hc_rx_dv, ethi.rx_dv);
|
752 |
|
|
erxer_pad : inpad generic map (tech => padtech)
|
753 |
|
|
port map (hc_rx_err, ethi.rx_er);
|
754 |
|
|
erxco_pad : inpad generic map (tech => padtech)
|
755 |
|
|
port map (hc_rx_col, ethi.rx_col);
|
756 |
|
|
erxcr_pad : inpad generic map (tech => padtech)
|
757 |
|
|
port map (hc_rx_crs, ethi.rx_crs);
|
758 |
|
|
|
759 |
|
|
etxd_pad : outpadv generic map (tech => padtech, width => 4)
|
760 |
|
|
port map (hc_tx_d, etho.txd(3 downto 0));
|
761 |
|
|
etxen_pad : outpad generic map (tech => padtech)
|
762 |
|
|
port map (hc_tx_en, etho.tx_en);
|
763 |
|
|
emdc_pad : outpad generic map (tech => padtech)
|
764 |
|
|
port map (hc_mdc, etho.mdc);
|
765 |
|
|
erst_pad : outpad generic map (tech => padtech)
|
766 |
|
|
port map (hc_eth_reset_n, rawrstn);
|
767 |
|
|
end generate;
|
768 |
|
|
|
769 |
|
|
-----------------------------------------------------------------------
|
770 |
|
|
--- AHB ROM ----------------------------------------------------------
|
771 |
|
|
-----------------------------------------------------------------------
|
772 |
|
|
|
773 |
|
|
bpromgen : if CFG_AHBROMEN /= 0 generate
|
774 |
|
|
brom : entity work.ahbrom
|
775 |
|
|
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
|
776 |
|
|
port map ( rstn, clkm, ahbsi, ahbso(6));
|
777 |
|
|
end generate;
|
778 |
|
|
nobpromgen : if CFG_AHBROMEN = 0 generate
|
779 |
|
|
ahbso(6) <= ahbs_none;
|
780 |
|
|
end generate;
|
781 |
|
|
|
782 |
|
|
-----------------------------------------------------------------------
|
783 |
|
|
--- AHB RAM ----------------------------------------------------------
|
784 |
|
|
-----------------------------------------------------------------------
|
785 |
|
|
|
786 |
|
|
ahbramgen : if CFG_AHBRAMEN = 1 generate
|
787 |
|
|
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
|
788 |
|
|
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
|
789 |
|
|
port map (rstn, clkm, ahbsi, ahbso(7));
|
790 |
|
|
end generate;
|
791 |
|
|
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
|
792 |
|
|
|
793 |
|
|
-----------------------------------------------------------------------
|
794 |
|
|
--- Drive unused bus elements ---------------------------------------
|
795 |
|
|
-----------------------------------------------------------------------
|
796 |
|
|
|
797 |
|
|
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
|
798 |
|
|
ahbmo(i) <= ahbm_none;
|
799 |
|
|
end generate;
|
800 |
|
|
|
801 |
|
|
-- invert signal for input via a key
|
802 |
|
|
dsubre <= not dsubren;
|
803 |
|
|
|
804 |
|
|
-----------------------------------------------------------------------
|
805 |
|
|
--- Boot message ----------------------------------------------------
|
806 |
|
|
-----------------------------------------------------------------------
|
807 |
|
|
|
808 |
|
|
-- pragma translate_off
|
809 |
|
|
x : report_version
|
810 |
|
|
generic map (
|
811 |
|
|
msg1 => "LEON3 Altera Embedded Evaluation Kit Demonstration Design",
|
812 |
|
|
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
|
813 |
|
|
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
|
814 |
|
|
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
|
815 |
|
|
mdel => 1
|
816 |
|
|
);
|
817 |
|
|
-- pragma translate_on
|
818 |
|
|
|
819 |
|
|
end;
|