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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-altera-ep3sl150/] [config_test.h] - Blame information for rev 2

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/*
 * Processor
 */
/*
 * Integer unit
 */
#define CONFIG_IU_NWINDOWS (8)
#undef  CONFIG_IU_V8MULDIV
/*
 * Cache system
 */
#define CONFIG_ICACHE_ENABLE 1
#define CONFIG_ICACHE_SZ1 1
#undef  CONFIG_ICACHE_SZ2
#undef  CONFIG_ICACHE_SZ4
#undef  CONFIG_ICACHE_SZ8
#undef  CONFIG_ICACHE_SZ16
#undef  CONFIG_ICACHE_SZ32
#undef  CONFIG_ICACHE_SZ64
#undef  CONFIG_ICACHE_LRAM
#define CONFIG_DCACHE_ENABLE 1
#define CONFIG_DCACHE_SZ1 1
#undef  CONFIG_DCACHE_SZ2
#undef  CONFIG_DCACHE_SZ4
#undef  CONFIG_DCACHE_SZ8
#undef  CONFIG_DCACHE_SZ16
#undef  CONFIG_DCACHE_SZ32
#undef  CONFIG_DCACHE_SZ64
#undef  CONFIG_DCACHE_LRAM
/*
 * MMU
 */
#undef  CONFIG_MMU_ENABLE
/*
 * Debug Support Unit
 */
#define CONFIG_DSU_ENABLE 1
#undef  CONFIG_DSU_ITRACE
#undef  CONFIG_DSU_ATRACE
/*
 * Debug Link
 */
#define CONFIG_DSU_UART 1
#define CONFIG_DSU_ETH 1
#undef  CONFIG_DSU_ETHSZ1
#define CONFIG_DSU_ETHSZ2 1
#undef  CONFIG_DSU_ETHSZ4
#undef  CONFIG_DSU_ETHSZ8
#undef  CONFIG_DSU_ETHSZ16
/*
 * Peripherals
 */
/*
 * Memory controllers
 */
#undef  CONFIG_MCTRL_NONE
#define CONFIG_MCTRL_LEON2 1
#define CONFIG_MCTRL_SDRAM 1
/*
 * Ethernet
 */
#undef  CONFIG_ETH_ENABLE
/*
 * PCI
 */
#undef  CONFIG_PCI_ENABLE
/*
 * CAN
 */
#undef  CONFIG_CAN_ENABLE
/*
 * UARTs, timers and irq control
 */
#define CONFIG_UART1_ENABLE 1
#define CONFIG_GPT_ENABLE 1

Line No.	Rev	Author	Line
1	2	dimamali	`/*`
2			`* Processor`
3			`*/`
4			`/*`
5			`* Integer unit`
6			`*/`
7			`#define CONFIG_IU_NWINDOWS (8)`
8			`#undef CONFIG_IU_V8MULDIV`
9			`/*`
10			`* Cache system`
11			`*/`
12			`#define CONFIG_ICACHE_ENABLE 1`
13			`#define CONFIG_ICACHE_SZ1 1`
14			`#undef CONFIG_ICACHE_SZ2`
15			`#undef CONFIG_ICACHE_SZ4`
16			`#undef CONFIG_ICACHE_SZ8`
17			`#undef CONFIG_ICACHE_SZ16`
18			`#undef CONFIG_ICACHE_SZ32`
19			`#undef CONFIG_ICACHE_SZ64`
20			`#undef CONFIG_ICACHE_LRAM`
21			`#define CONFIG_DCACHE_ENABLE 1`
22			`#define CONFIG_DCACHE_SZ1 1`
23			`#undef CONFIG_DCACHE_SZ2`
24			`#undef CONFIG_DCACHE_SZ4`
25			`#undef CONFIG_DCACHE_SZ8`
26			`#undef CONFIG_DCACHE_SZ16`
27			`#undef CONFIG_DCACHE_SZ32`
28			`#undef CONFIG_DCACHE_SZ64`
29			`#undef CONFIG_DCACHE_LRAM`
30			`/*`
31			`* MMU`
32			`*/`
33			`#undef CONFIG_MMU_ENABLE`
34			`/*`
35			`* Debug Support Unit`
36			`*/`
37			`#define CONFIG_DSU_ENABLE 1`
38			`#undef CONFIG_DSU_ITRACE`
39			`#undef CONFIG_DSU_ATRACE`
40			`/*`
41			`* Debug Link`
42			`*/`
43			`#define CONFIG_DSU_UART 1`
44			`#define CONFIG_DSU_ETH 1`
45			`#undef CONFIG_DSU_ETHSZ1`
46			`#define CONFIG_DSU_ETHSZ2 1`
47			`#undef CONFIG_DSU_ETHSZ4`
48			`#undef CONFIG_DSU_ETHSZ8`
49			`#undef CONFIG_DSU_ETHSZ16`
50			`/*`
51			`* Peripherals`
52			`*/`
53			`/*`
54			`* Memory controllers`
55			`*/`
56			`#undef CONFIG_MCTRL_NONE`
57			`#define CONFIG_MCTRL_LEON2 1`
58			`#define CONFIG_MCTRL_SDRAM 1`
59			`/*`
60			`* Ethernet`
61			`*/`
62			`#undef CONFIG_ETH_ENABLE`
63			`/*`
64			`* PCI`
65			`*/`
66			`#undef CONFIG_PCI_ENABLE`
67			`/*`
68			`* CAN`
69			`*/`
70			`#undef CONFIG_CAN_ENABLE`
71			`/*`
72			`* UARTs, timers and irq control`
73			`*/`
74			`#define CONFIG_UART1_ENABLE 1`
75			`#define CONFIG_GPT_ENABLE 1`

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-altera-ep3sl150/] [config_test.h] - Blame information for rev 2