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dimamali |
current_design leon3mp
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| 2 |
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set_operating_conditions -library ut025sf25v af_max
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set sys_clk_freq 80.0
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set pci_clk_freq 33.3
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set eth_clk_freq 25.0
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set spw_clk_freq 200.0
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set clock_skew 0.10
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| 9 |
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set input_setup 2.0
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set output_delay 6.0
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| 12 |
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set sys_peri [expr 1000.0 / $sys_clk_freq]
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set spw_peri [expr 1000.0 / $spw_clk_freq]
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set pci_peri [expr 1000.0 / $pci_clk_freq]
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set eth_peri [expr 1000.0 / $eth_clk_freq]
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set input_delay [expr $sys_peri - $input_setup]
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set tdelay [expr $output_delay + 1]
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| 19 |
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create_clock -name "clk" -period $sys_peri {"core0/clk" }
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set_dont_touch_network clk
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create_clock -name "spw_txclk" -period $spw_peri { "core0/spw_clk"}
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set_dont_touch_network spw_txclk
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| 23 |
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create_clock -name "pci_clk" -period $pci_peri { "core0/pciclk"}
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| 24 |
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set_dont_touch_network pci_clk
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| 25 |
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create_clock -name "etx_clk" -period $eth_peri { "core0/etx_clk" }
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set_dont_touch_network etx_clk
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create_clock -name "erx_clk" -period $eth_peri { "core0/erx_clk" }
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set_dont_touch_network erx_clk
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| 29 |
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| 30 |
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create_clock -name "spw_rxclk0" -period $spw_peri { "core0/leon3core0/grspw0_0/grspwc0/rxclko[0]" }
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| 31 |
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set_dont_touch_network spw_rxclk0
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| 32 |
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create_clock -name "spw_rxclk1" -period $spw_peri { "core0/leon3core0/grspw0_1/grspwc0/rxclko[0]" }
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| 33 |
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set_dont_touch_network spw_rxclk1
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| 34 |
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create_clock -name "spw_rxclk2" -period $spw_peri { "core0/leon3core0/grspw0_2/grspwc0/rxclko[0]" }
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| 35 |
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set_dont_touch_network spw_rxclk2
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| 36 |
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create_clock -name "spw_rxclk3" -period $spw_peri { "core0/leon3core0/grspw0_3/grspwc0/rxclko[0]" }
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| 37 |
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set_dont_touch_network spw_rxclk3
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| 38 |
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| 39 |
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set_false_path -from resetn
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| 40 |
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set_false_path -from test
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| 41 |
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set_false_path -from resetn
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| 42 |
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set_false_path -from test
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| 43 |
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set_false_path -from rxd1
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| 44 |
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set_false_path -from dsubre
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| 45 |
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set_false_path -from dsuen
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| 46 |
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| 47 |
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set_false_path -from clk -to spw_txclk
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| 48 |
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set_false_path -to clk -from spw_txclk
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| 49 |
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set_false_path -from clk -to spw_rxclk0
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| 50 |
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set_false_path -to clk -from spw_rxclk0
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| 51 |
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set_false_path -from clk -to spw_rxclk1
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| 52 |
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set_false_path -to clk -from spw_rxclk1
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| 53 |
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set_false_path -from clk -to spw_rxclk2
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| 54 |
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set_false_path -to clk -from spw_rxclk2
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| 55 |
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set_false_path -from clk -to spw_rxclk3
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| 56 |
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set_false_path -to clk -from spw_rxclk3
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| 57 |
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set_false_path -from spw_txclk -to spw_rxclk0
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| 58 |
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set_false_path -to spw_txclk -from spw_rxclk0
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| 59 |
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set_false_path -from spw_txclk -to spw_rxclk1
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| 60 |
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set_false_path -to spw_txclk -from spw_rxclk1
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| 61 |
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set_false_path -from spw_txclk -to spw_rxclk2
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| 62 |
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set_false_path -to spw_txclk -from spw_rxclk2
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| 63 |
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set_false_path -from spw_txclk -to spw_rxclk3
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| 64 |
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set_false_path -to spw_txclk -from spw_rxclk3
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| 65 |
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set_false_path -to clk -from etx_clk
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| 66 |
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set_false_path -to etx_clk -from clk
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| 67 |
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set_false_path -to clk -from erx_clk
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| 68 |
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set_false_path -to erx_clk -from clk
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| 69 |
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set_false_path -to pci_clk -from clk
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| 70 |
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set_false_path -to clk -from pci_clk
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| 71 |
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| 72 |
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set_input_delay $input_delay -clock clk { \
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gpio\[*\] data\[*\] brdyn bexcn rxd1 cb\[*\] }
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| 75 |
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set_max_delay $output_delay -to { errorn wdogn \
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gpio\[*\] data\[*\] txd1 cb\[*\] }
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| 78 |
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set_max_delay $output_delay -to { \
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| 79 |
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wdogn writen romsn\[*\] read oen iosn rwen\[*\] ramsn\[*\] \
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ramoen\[*\] sdcsn\[*\] sdwen sdrasn sdcasn \
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| 81 |
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sddqm\[*\] address\[*\] \
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}
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| 83 |
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| 84 |
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set_false_path -to dsuact
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| 85 |
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set_ideal_network test
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