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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-avnet-3s1500/] [leon3mp.ucf] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
#Spartan-3 Evaluation Board Constraints File
2
 
3
#Clocks
4
NET "clk_socket" LOC = "AB12"  | IOSTANDARD = LVCMOS33; #OSC2 (SOCKET)
5
NET "clk_66mhz"  LOC = "A11";  #OSC1 (66MHZ)
6
NET clk_66mhz PERIOD = 15.000 ;
7
OFFSET = OUT : 12.000 : AFTER clk_66mhz;
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NET video_clk PERIOD = 39.000 ;
9
 
10
# Enable for ISE10
11
#NET "video_clk" CLOCK_DEDICATED_ROUTE = FALSE;
12
#NET "phy_rxck" CLOCK_DEDICATED_ROUTE = FALSE;
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#NET "phy_txck" CLOCK_DEDICATED_ROUTE = FALSE;
14
 
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#NET "clk"              TNM_NET = "clk";
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#NET "clk40"            TNM_NET = "clk40";
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#TIMESPEC "TS_clk_clk40" = FROM "clk" TO "clk40" TIG;
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#TIMESPEC "TS_clk40_clk" = FROM "clk40" TO "clk" TIG;
19
 
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NET pci_clk PERIOD = 30.000 ;
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OFFSET = OUT : 11.000 : AFTER pci_clk ;
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OFFSET = IN : 7.000 : BEFORE pci_clk ;
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NET  "pci_clk"      LOC = "AA12";
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NET pci_gnt OFFSET = IN : 10.000 : BEFORE pci_clk ;
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NET pci_req OFFSET = OUT : 12.000 : AFTER pci_clk ;
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NET pci_rst TIG ;
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NET phy_txck PERIOD = 40.000 ;
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NET phy_rxck PERIOD = 40.000 ;
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OFFSET = OUT : 15.000 : AFTER phy_txck ;
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OFFSET = IN : 10.000 : BEFORE phy_txck ;
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OFFSET = IN : 10.000 : BEFORE phy_rxck ;
33
 
34
#LEDs
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NET "leds(0)" LOC = "U12";
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NET "leds(1)" LOC = "V12";
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NET "leds(2)" LOC = "Y12";
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NET "leds(3)" LOC = "Y13";
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NET "leds(4)" LOC = "AB13";
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NET "leds(5)" LOC = "AA13";
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NET "leds(6)" LOC = "V13";
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NET "leds(7)" LOC = "AB14";
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44
#Switches (DIP switches (4) and Pushbuttons (2))
45
NET "switches(0)" LOC = "W4"  | IOSTANDARD = LVCMOS33; # SWITCH(0) (SW2:1)
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NET "switches(1)" LOC = "W3"  | IOSTANDARD = LVCMOS33; # SWITCH(1) (SW2:2)
47
NET "switches(2)" LOC = "Y3"  | IOSTANDARD = LVCMOS33; # SWITCH(2) (SW2:3)
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NET "switches(3)" LOC = "Y2"  | IOSTANDARD = LVCMOS33; # SWITCH(3) (SW2:4)
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NET "switches(4)" LOC = "Y1"  | IOSTANDARD = LVCMOS33; # SWITCH_PB1 (SW3)
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NET "switches(5)" LOC = "W2"  | IOSTANDARD = LVCMOS33; # SWITCH_PB2 (SW4)
51
 
52
# PS2 Ports (Mouse and Keyboard)
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NET "msclk"     LOC = "W14"; # JS2
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NET "msdata"    LOC = "W13";
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NET "msclk"     PULLUP;
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NET "msdata"    PULLUP;
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NET "kbclk"     LOC = "U17"; # JS1
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NET "kbdata"    LOC = "U16";
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NET "kbclk"     PULLUP;
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NET "kbdata"    PULLUP;
62
 
63
#SRAM
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NET "sram_a(0)" LOC = "E22"; #ADDR0
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NET "sram_a(1)" LOC = "E21";
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NET "sram_a(2)" LOC = "D21";
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NET "sram_a(3)" LOC = "E20";
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NET "sram_a(4)" LOC = "D22";
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NET "sram_a(5)" LOC = "D20";
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NET "sram_a(6)" LOC = "C22";
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NET "sram_a(7)" LOC = "D19";
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NET "sram_a(8)" LOC = "C20";
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NET "sram_a(9)" LOC = "C21";
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NET "sram_a(10)" LOC = "F18";
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NET "sram_a(11)" LOC = "G18";
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NET "sram_a(12)" LOC = "G19";
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NET "sram_a(13)" LOC = "E18";
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NET "sram_a(14)" LOC = "F19";
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NET "sram_a(15)" LOC = "F20";
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NET "sram_a(16)" LOC = "E19";
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NET "sram_a(17)" LOC = "F21";  #ADDR17
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NET "sram_a(18)" LOC = "F17";
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NET "sram_a(19)" LOC = "F16";
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NET "sram_a(20)" LOC = "E16";
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NET "sram_a(21)" LOC = "E13";
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NET "sram_a(22)" LOC = "F13";
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NET "sram_a(23)" LOC = "A12";
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NET "sram_a(24)" LOC = "F12";
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#NET "sdwen" LOC = "L20";
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NET "sdclk" LOC = "L21";
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NET "sdcsn" LOC = "B20";
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NET "casn"  LOC = "C19";
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NET "rasn"  LOC = "B19";
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NET "sdcke" LOC = "A19";
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NET "can_txd" LOC = "U6";
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NET "can_rxd" LOC = "Y4";
99
 
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NET "sram_ben_l(0)" LOC = "K21"; #BE0
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NET "sram_ben_l(1)" LOC = "K22";
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NET "sram_ben_l(2)" LOC = "G22";
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NET "sram_ben_l(3)" LOC = "K20"; #BE3
104
 
105
NET "sram_cs_l(0)" LOC = "G21";
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NET "sram_cs_l(1)" LOC = "L20";
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NET "sram_oe_l" LOC = "G17";
108
NET "sram_we_l" LOC = "K19";
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NET "flash_cs_l" LOC = "L18";
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NET "flash_rst_l" LOC = "L19";
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NET "sram_dq(0)" LOC = "U19"; #DATA0
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NET "sram_dq(1)" LOC = "T21";
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NET "sram_dq(2)" LOC = "U20";
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NET "sram_dq(3)" LOC = "U21";
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NET "sram_dq(4)" LOC = "V21";
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NET "sram_dq(5)" LOC = "V22";
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NET "sram_dq(6)" LOC = "W22";
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NET "sram_dq(7)" LOC = "V20";
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NET "sram_dq(8)" LOC = "Y19";
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NET "sram_dq(9)" LOC = "W19";
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NET "sram_dq(10)" LOC = "V19";
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NET "sram_dq(11)" LOC = "Y20";
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NET "sram_dq(12)" LOC = "Y21";
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NET "sram_dq(13)" LOC = "Y22";
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NET "sram_dq(14)" LOC = "W20";
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NET "sram_dq(15)" LOC = "W21";
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NET "sram_dq(16)" LOC = "M17";
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NET "sram_dq(17)" LOC = "L17";
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NET "sram_dq(18)" LOC = "M19";
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NET "sram_dq(19)" LOC = "M18";
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NET "sram_dq(20)" LOC = "M20";
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NET "sram_dq(21)" LOC = "N19";
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NET "sram_dq(22)" LOC = "M21";
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NET "sram_dq(23)" LOC = "N20";
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NET "sram_dq(24)" LOC = "T22";
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NET "sram_dq(25)" LOC = "U18";
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NET "sram_dq(26)" LOC = "T18";
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NET "sram_dq(27)" LOC = "R18";
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NET "sram_dq(28)" LOC = "T17";
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NET "sram_dq(29)" LOC = "N21";
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NET "sram_dq(30)" LOC = "N22";
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NET "sram_dq(31)" LOC = "M22"; #DATA31
144
 
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# UART
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NET "tx" LOC = "C3";
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NET "rx" LOC = "C4";
148
 
149
# Ethernet PHY
150
 
151
NET "phy_txck"    LOC = "C12";
152
NET "phy_rxck"    LOC = "B12";
153
NET "phy_crs"     LOC = "E12";
154
NET "phy_rxdv"    LOC = "B14";
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NET "phy_rxd(0)"  LOC = "B15";
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NET "phy_rxd(1)"  LOC = "A15";
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NET "phy_rxd(2)"  LOC = "D15";
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NET "phy_rxd(3)"  LOC = "E15";
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NET "phy_col"     LOC = "D13";
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NET "phy_rxer"    LOC = "A14";
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NET "phy_txen"    LOC = "E14";
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NET "phy_txd(0)"  LOC = "B13";
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NET "phy_txd(1)"  LOC = "A13";
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NET "phy_txd(2)"  LOC = "C13";
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NET "phy_txd(3)"  LOC = "D12";
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NET "phy_reset_l"    PULLUP;
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NET "phy_reset_l" LOC = "E4";
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NET "phy_mdc"     LOC = "C17";
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NET "phy_mdio"    LOC = "B17";
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NET "phy_txer"    LOC = "D14";
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# Video DAC
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NET "video_clk"     LOC = "B11" | IOSTANDARD = LVCMOS33;
174
NET "horiz_sync"    LOC = "E11";
175
NET "vert_sync"     LOC = "D11";
176
NET "comp_sync"     LOC = "A3";
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NET "blank"         LOC = "A4";
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NET "video_out(0)"  LOC = "E9"; # Blue(0)
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NET "video_out(1)"  LOC = "F9"; # Blue(1)
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NET "video_out(2)"  LOC = "D7"; # Blue(2)
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NET "video_out(3)"  LOC = "C7"; # Blue(3)
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NET "video_out(4)"  LOC = "E7"; # Blue(4)
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NET "video_out(5)"  LOC = "F7"; # Blue(5)
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NET "video_out(6)"  LOC = "E6"; # Blue(6)
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NET "video_out(7)"  LOC = "F6"; # Blue(7)
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NET "video_out(8)"  LOC = "F10";        # Greeen(0)
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NET "video_out(9)"  LOC = "D10";
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NET "video_out(10)" LOC = "A10";
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NET "video_out(11)" LOC = "D9";
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NET "video_out(12)" LOC = "A9";
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NET "video_out(13)" LOC = "B9";
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NET "video_out(14)" LOC = "A8";
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NET "video_out(15)" LOC = "B8"; # Green(7)
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NET "video_out(16)" LOC = "D6"; # Red(0)
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NET "video_out(17)" LOC = "C6";
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NET "video_out(18)" LOC = "B6";
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NET "video_out(19)" LOC = "D5";
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NET "video_out(20)" LOC = "A5";
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NET "video_out(21)" LOC = "B5";
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NET "video_out(22)" LOC = "C5";
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NET "video_out(23)" LOC = "B4"; # Red(7)
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203
# Comparator
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NET "ADC_CMP_OUT" LOC = "V18";
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NET "ADC_ANA_REF" LOC = "U13";
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NET "ADC_ANA_OUT" LOC = "Y16";
207
 
208
# EEPROM
209
NET "sda" LOC = "AA14"; # FPGA_D0
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NET "scl" LOC = "W12";  # FPGA_INIT#
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212
# Dual 7 Segment LED
213
NET "disp_seg1(7)" LOC = "AB15";        #0
214
NET "disp_seg1(6)" LOC = "AB18";        #1
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NET "disp_seg1(5)" LOC = "V17"; #2
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NET "disp_seg1(4)" LOC = "U14"; #3
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NET "disp_seg1(3)" LOC = "V14"; #4
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NET "disp_seg1(2)" LOC = "AA15";        #5
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NET "disp_seg1(1)" LOC = "Y18"; #6
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NET "disp_seg1(0)" LOC = "AA18";        #7
221
 
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NET "disp_seg2(7)" LOC = "W17"; #0
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NET "disp_seg2(6)" LOC = "Y17"; #1
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NET "disp_seg2(5)" LOC = "W18"; #2
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NET "disp_seg2(4)" LOC = "V16"; #3
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NET "disp_seg2(3)" LOC = "W16"; #4
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NET "disp_seg2(2)" LOC = "AA17";        #5
228
NET "disp_seg2(1)" LOC = "AA20";        #6
229
NET "disp_seg2(0)" LOC = "AB20";        #7
230
 
231
# PCI 32-bit
232
#NET  "pci_rst"     LOC = "E4"  ;
233
#
234
NET  "pci_ad(31)" LOC = "D2"  ;
235
NET  "pci_ad(30)" LOC = "D3"  ;
236
NET  "pci_ad(29)" LOC = "E3"  ;
237
NET  "pci_ad(28)" LOC = "F4"  ;
238
NET  "pci_ad(27)" LOC = "E2"  ;
239
NET  "pci_ad(26)" LOC = "E1"  ;
240
NET  "pci_ad(25)" LOC = "F5"  ;
241
NET  "pci_ad(24)" LOC = "G6"  ;
242
NET  "pci_ad(23)" LOC = "F3"  ;
243
NET  "pci_ad(22)" LOC = "F2"  ;
244
NET  "pci_ad(21)" LOC = "G5"  ;
245
NET  "pci_ad(20)" LOC = "H5"  ;
246
NET  "pci_ad(19)" LOC = "G2"  ;
247
NET  "pci_ad(18)" LOC = "G1"  ;
248
NET  "pci_ad(17)" LOC = "K4"  ;
249
NET  "pci_ad(16)" LOC = "K3"  ;
250
NET  "pci_cbe(3)" LOC = "K2"  ;
251
NET  "pci_cbe(2)" LOC = "K1"  ;
252
#
253
NET  "pci_req"    LOC = "L6"  ;
254
NET  "pci_gnt"    LOC = "L5" | IOSTANDARD = PCI33_3 ;
255
NET  "pci_par"    LOC = "L4"  ;
256
NET  "pci_idsel"  LOC = "L3"  ;
257
NET  "pci_frame"  LOC = "L2"  ;
258
NET  "pci_irdy"   LOC = "L1"  ;
259
NET  "pci_trdy"   LOC = "M1"  ;
260
NET  "pci_devsel" LOC = "M2"  ;
261
NET  "pci_stop"   LOC = "M3"  ;
262
NET  "pci_perr"   LOC = "M4"  ;
263
NET  "pci_serr"   LOC = "M5"  ;
264
NET  "pci_inta"   LOC = "M6"  ;
265
#
266
NET  "pci_cbe(1)" LOC = "N1"  ;
267
NET  "pci_cbe(0)" LOC = "N2"  ;
268
NET  "pci_ad(15)" LOC = "N3"  ;
269
NET  "pci_ad(14)" LOC = "N4"  ;
270
NET  "pci_ad(13)" LOC = "T1"  ;
271
NET  "pci_ad(12)" LOC = "T2"  ;
272
NET  "pci_ad(11)" LOC = "U2"  ;
273
NET  "pci_ad(10)" LOC = "U3"  ;
274
NET  "pci_ad(9)"  LOC = "T4"  ;
275
NET  "pci_ad(8)"  LOC = "U4"  ;
276
NET  "pci_ad(7)"  LOC = "T5"  ;
277
NET  "pci_ad(6)"  LOC = "T6"  ;
278
NET  "pci_ad(5)"  LOC = "V1"  ;
279
NET  "pci_ad(4)"  LOC = "V2"  ;
280
NET  "pci_ad(3)"  LOC = "V3"  ;
281
NET  "pci_ad(2)"  LOC = "V4"  ;
282
NET  "pci_ad(1)"  LOC = "U5"  ;
283
NET  "pci_ad(0)"  LOC = "V5"  ;

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