OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-digilent-xup/] [prom.S] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
 
2
/* Template boot-code for LEON3 test benches */
3
 
4
#ifndef STACKSIZE
5
#define STACKSIZE 0x00002000
6
#endif
7
 
8
#include "prom.h"
9
 
10
        .seg    "text"
11
        .proc   0
12
        .align  4
13
        .global start
14
start:
15
 
16
        flush
17
        set 0x10e0, %g1         ! init IU
18
        mov %g1, %psr
19
        mov %g0, %wim
20
        mov %g0, %tbr
21
        mov %g0, %y
22
        nop
23
        set  0x81000f, %g1
24
        sta %g1, [%g0] 2
25
 
26
2:
27
        mov %asr17, %g3
28
        and %g3, 0x1f, %g3
29
        mov %g0, %g4
30
        mov %g0, %g5
31
        mov %g0, %g6
32
        mov %g0, %g7
33
1:
34
        mov %g0, %l0
35
        mov %g0, %l1
36
        mov %g0, %l2
37
        mov %g0, %l3
38
        mov %g0, %l4
39
        mov %g0, %l5
40
        mov %g0, %l6
41
        mov %g0, %l7
42
        mov %g0, %o0
43
        mov %g0, %o1
44
        mov %g0, %o2
45
        mov %g0, %o3
46
        mov %g0, %o4
47
        mov %g0, %o5
48
        mov %g0, %o6
49
        mov %g0, %o7
50
        subcc %g3, 1, %g3
51
        bge 1b
52
        save
53
 
54
        mov     2, %g1
55
        mov     %g1, %wim
56
        set 0x10e0, %g1         ! enable traps
57
        mov %g1, %psr
58
        nop; nop; nop;
59
 
60
        mov %psr, %g1
61
        srl %g1, 12, %g1
62
        andcc %g1, 1, %g0
63
        be 1f
64
        nop
65
 
66
        set _fsrxx, %g3
67
        ld [%g3], %fsr
68
        ldd [%g3], %f0
69
        ldd [%g3], %f2
70
        ldd [%g3], %f4
71
        ldd [%g3+8], %f6
72
        ldd [%g3], %f8
73
        ldd [%g3], %f10
74
        ldd [%g3], %f12
75
        ldd [%g3], %f14
76
        ldd [%g3], %f16
77
        ldd [%g3], %f18
78
        ldd [%g3], %f20
79
        ldd [%g3], %f22
80
        ldd [%g3], %f24
81
        ldd [%g3], %f26
82
        ldd [%g3], %f28
83
        ba  1f
84
        ldd [%g3], %f30
85
 
86
.align  8
87
_fsrxx:
88
        .word 0
89
        .word 0
90
 
91
 
92
1:      set STACKSIZE, %g2
93
        mov %g0, %g1
94
 
95
/*
96
        set 0x80000d00, %g4
97
!       set 0x40000000+114*4, %g5
98
        set 0x400005E4, %g5
99
        set 0x405685E4, %g6
100
        st %g5, [%g4]
101
!       add %g5, 0x200, %g5
102
        st %g6, [%g4+4]
103
        set 0x1a0005, %g5
104
        st %g5, [%g4+8]
105
4:
106
        ba 4b
107
        nop
108
*/
109
 
110
3:      set RAMSTART+ RAMSIZE-32, %fp
111
        sub %fp, %g1, %fp
112
        sub %fp, 96, %sp
113
 
114
        set RAMSTART, %g1
115
 
116
        jmp %g1
117
        nop
118
 
119
.align  32

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.