URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [r5_reg_cls/] [_primary.vhd] - Blame information for rev 2

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library verilog;
use verilog.vl_types.all;
entity r5_reg_cls is
    port(
        r5_i            : in     vl_logic_vector(4 downto 0);
        r5_o            : out    vl_logic_vector(4 downto 0);
        clk             : in     vl_logic;
        cls             : in     vl_logic;
        hold            : in     vl_logic
    );
end r5_reg_cls;

Line No.	Rev	Author	Line
1	2	dimamali	`library verilog;`
2			`use verilog.vl_types.all;`
3			`entity r5_reg_cls is`
4			`port(`
5			`r5_i : in vl_logic_vector(4 downto 0);`
6			`r5_o : out vl_logic_vector(4 downto 0);`
7			`clk : in vl_logic;`
8			`cls : in vl_logic;`
9			`hold : in vl_logic`
10			`);`
11			`end r5_reg_cls;`

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [gaisler/] [r5_reg_cls/] [_primary.vhd] - Blame information for rev 2