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Number of processors

CONFIG_PROC_NUM

  The number of processor cores. The LEON3MP design can accomodate

  up to 4 LEON3 processor cores. Use 1 unless you know what you are

  doing ...

Number of SPARC register windows

CONFIG_IU_NWINDOWS

  The SPARC architecture (and LEON) allows 2 - 32 register windows.

  However, any number except 8 will require that you modify and

  recompile your run-time system or kernel. Unless you know what

  you are doing, use 8.

SPARC V8 multiply and divide instruction

CONFIG_IU_V8MULDIV

  If you say Y here, the SPARC V8 multiply and divide instructions

  will be implemented. The instructions are: UMUL, UMULCC, SMUL,

  SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent

  integer multiplications and divisions, significant performance

  increase can be achieved. Emulated floating-point operations will

  also benefit from this option.

  By default, the gcc compiler does not emit multiply or divide

  instructions and your code must be compiled with -mv8 to see any

  performance increase. On the other hand, code compiled with -mv8

  will generate an illegal instruction trap when executed on processors

  with this option disabled.

  The divider consumes approximately 2 kgates, the multiplier 6 kgates.

Multiplier latency

CONFIG_IU_MUL_LATENCY_4

  The multiplier used for UMUL/SMUL instructions is implemented

  with a 16x16 multiplier which is iterated 4 times. This leads

  to a 4-cycle latency for multiply operations. To improve timing,

  a pipeline stage can be inserted into the 16x16 multiplier which

  will lead to a 5-cycle latency for the multiply oprations.

Multiplier latency

CONFIG_IU_MUL_MAC

  If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)

  instructions will be enabled. The instructions implement a

  single-cycle 16x16->32 bits multiply with a 40-bits accumulator.

  The details of these instructions can be found in the LEON manual,

Single vector trapping

CONFIG_IU_SVT

  Single-vector trapping is a SPARC V8e option to reduce code-size

  in small applications. If enabled, the processor will jump to

  the address of trap 0 (tt = 0x00) for all traps. No trap table

  is then needed. The trap type is present in %psr.tt and must

  be decoded by the O/S. Saves 4 Kbyte of code, but increases

  trap and interrupt overhead. Currently, the only O/S supporting

  this option is eCos. To enable SVT, the O/S must also set bit 13

  in %asr17.

Load latency

CONFIG_IU_LDELAY

  Defines the pipeline load delay (= pipeline cycles before the data

  from a load instruction is available for the next instruction).

  One cycle gives best performance, but might create a critical path

  on targets with slow (data) cache memories. A 2-cycle delay can

  improve timing but will reduce performance with about 5%.

Reset address

CONFIG_IU_RSTADDR

  By default, a SPARC processor starts execution at address 0.

  With this option, any 4-kbyte aligned reset start address can be

  choosen. Keep at 0 unless you really know what you are doing.

Power-down

CONFIG_PWD

  Say Y here to enable the power-down feature of the processor.

  Might reduce the maximum frequency slightly on FPGA targets.

  For details on the power-down operation, see the LEON3 manual.

Hardware watchpoints

CONFIG_IU_WATCHPOINTS

  The processor can have up to 4 hardware watchpoints, allowing to

  create both data and instruction breakpoints at any memory location,

  also in PROM. Each watchpoint will use approximately 500 gates.

  Use 0 to disable the watchpoint function.

Floating-point enable

CONFIG_FPU_ENABLE

  Say Y here to enable the floating-point interface for the MEIKO

  or GRFPU. Note that no FPU's are provided with the GPL version

  of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial

  cores and must be obtained separately.

FPU selection

CONFIG_FPU_GRFPU

  Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun

  Meiko FPU core. All cores  are fully IEEE-754 compatible and support

  all SPARC FPU instructions.

GRFPU Multiplier

CONFIG_FPU_GRFPU_INFMUL

  On FPGA targets choose inferred multiplier. For ASIC implementations

  choose between Synopsys Design Ware (DW) multiplier or Module

  Generator (ModGen) multiplier. DW multiplier gives better results

  (smaller area  and better timing) but requires DW license. ModGen

  multiplier is part of GRLIB and does not require license.

Shared GRFPU

CONFIG_FPU_GRFPU_SH

  If enabled multiple CPU cores will share one GRFPU.

GRFPC Configuration

CONFIG_FPU_GRFPC0

  Configures the GRFPU-LITE controller.

  In simple configuration controller executes FP instructions

  in parallel with  integer instructions. FP operands are fetched

  in the register file stage and the result is written in the write

  stage. This option uses least area resources.

  Data forwarding configuration gives ~ 10 % higher FP performance than

  the simple configuration by adding data forwarding between the pipeline

  stages.

  Non-blocking controller allows FP load and store instructions to

  execute in parallel with FP instructions. The performance increase is

  ~ 20 % for FP applications. This option uses most logic resources and

  is suitable for ASIC implementations.

Floating-point netlist

CONFIG_FPU_NETLIST

  Say Y here to use a VHDL netlist of the GRFPU-Lite. This is

  only available in certain versions of grlib.

Enable Instruction cache

CONFIG_ICACHE_ENABLE

  The instruction cache should always be enabled to allow

  maximum performance. Some low-end system might want to

  save area and disable the cache, but this will reduce

  the performance with a factor of 2 - 3.

Enable Data cache

CONFIG_DCACHE_ENABLE

  The data cache should always be enabled to allow

  maximum performance. Some low-end system might want to

  save area and disable the cache, but this will reduce

  the performance with a factor of 2 at least.

Instruction cache associativity

CONFIG_ICACHE_ASSO1

  The instruction cache can be implemented as a multi-set cache with

  1 - 4 sets. Higher associativity usually increases the cache hit

  rate and thereby the performance. The downside is higher power

  consumption and increased gate-count for tag comparators.

  Note that a 1-set cache is effectively a direct-mapped cache.

Instruction cache set size

CONFIG_ICACHE_SZ1

  The size of each set in the instuction cache (kbytes). Valid values

  are 1 - 64 in binary steps. Note that the full range is only supported

  by the generic and virtex2 targets. Most target packages are limited

  to 2 - 16 kbyte. Large set size gives higher performance but might

  affect the maximum frequency (on ASIC targets). The total instruction

  cache size is the number of set multiplied with the set size.

Instruction cache line size

CONFIG_ICACHE_LZ16

  The instruction cache line size. Can be set to either 16 or 32

  bytes per line. Instruction caches typically benefit from larger

  line sizes, but on small caches it migh be better with 16 bytes/line

  to limit eviction miss rate.

Instruction cache replacement algorithm

CONFIG_ICACHE_ALGORND

  Cache replacement algorithm for caches with 2 - 4 sets. The 'random'

  algorithm selects the set to evict randomly. The least-recently-used

  (LRR) algorithm evicts the set least recently replaced. The least-

  recently-used (LRU) algorithm evicts the set least recently accessed.

  The random algorithm uses a simple 1- or 2-bit counter to select

  the eviction set and has low area overhead. The LRR scheme uses one

  extra bit in the tag ram and has therefore also low area overhead.

  However, the LRR scheme can only be used with 2-set caches. The LRU

  scheme has typically the best performance but also highest area overhead.

  A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops

  per line, and a 4-set LRU uses 5 flip-flops per line to store the access

  history.

Instruction cache locking

CONFIG_ICACHE_LOCK

  Say Y here to enable cache locking in the instruction cache.

  Locking can be done on cache-line level, but will increase the

  width of the tag ram with one bit. If you don't know what

  locking is good for, it is safe to say N.

Data cache associativity

CONFIG_DCACHE_ASSO1

  The data cache can be implemented as a multi-set cache with

  1 - 4 sets. Higher associativity usually increases the cache hit

  rate and thereby the performance. The downside is higher power

  consumption and increased gate-count for tag comparators.

  Note that a 1-set cache is effectively a direct-mapped cache.

Data cache set size

CONFIG_DCACHE_SZ1

  The size of each set in the data cache (kbytes). Valid values are

  1 - 64 in binary steps. Note that the full range is only supported

  by the generic and virtex2 targets. Most target packages are limited

  to 2 - 16 kbyte. A large cache gives higher performance but the

  data cache is timing critical an a too large setting might affect

  the maximum frequency (on ASIC targets). The total data cache size

  is the number of set multiplied with the set size.

Data cache line size

CONFIG_DCACHE_LZ16

  The data cache line size. Can be set to either 16 or 32 bytes per

  line. A smaller line size gives better associativity and higher

  cache hit rate, but requires a larger tag memory.

Data cache replacement algorithm

CONFIG_DCACHE_ALGORND

  See the explanation for instruction cache replacement algorithm.

Data cache locking

CONFIG_DCACHE_LOCK

  Say Y here to enable cache locking in the data cache.

  Locking can be done on cache-line level, but will increase the

  width of the tag ram with one bit. If you don't know what

  locking is good for, it is safe to say N.

Data cache snooping

CONFIG_DCACHE_SNOOP

  Say Y here to enable data cache snooping on the AHB bus. Is only

  useful if you have additional AHB masters such as the DSU or a

  target PCI interface. Note that the target technology must support

  dual-port RAMs for this option to be enabled. Dual-port RAMS are

  currently supported on Virtex/2, Virage and Actel targets.

Data cache snooping implementation

CONFIG_DCACHE_SNOOP_FAST

  The default snooping implementation is 'slow', which works if you

  don't have AHB slaves in cacheable areas capable of zero-waitstates

  non-sequential write accesses. Otherwise use 'fast' and suffer a

  few kgates extra area. This option is currently only needed in

  multi-master systems with the SSRAM or DDR memory controllers.

Separate snoop tags

CONFIG_DCACHE_SNOOP_SEPTAG

  Enable a separate memory to store the data tags used for snooping.

  This is necessary when snooping support is wanted in systems

  with MMU, typically for SMP systems. In this case, the snoop

  tags will contain the physical tag address while the normal

  tags contain the virtual tag address. This option can also be

  together with the 'fast snooping' option to enable snooping

  support on technologies without dual-port RAMs. In such case,

  the snoop tag RAM will be implemented using a two-port RAM.

Fixed cacheability map

CONFIG_CACHE_FIXED

  If this variable is 0, the cacheable memory regions are defined

  by the AHB plug&play information (default). To overriden the

  plug&play settings, this variable can be set to indicate which

  areas should be cached. The value is treated as a 16-bit hex value

  with each bit defining if a 256 Mbyte segment should be cached or not.

  The right-most (LSB) bit defines the cacheability of AHB address

  3840 - 4096 MByte. If the bit is set, the corresponding area is

  cacheable. A value of 00F3 defines address 0 - 0x20000000 and

  0x40000000 - 0x80000000 as cacheable.

Local data ram

CONFIG_DCACHE_LRAM

  Say Y here to add a local ram to the data cache controller.

  Accesses to the ram (load/store) will be performed at 0 waitstates

  and store data will never be written back to the AHB bus.

Size of local data ram

CONFIG_DCACHE_LRAM_SZ1

  Defines the size of the local data ram in Kbytes. Note that most

  technology libraries do not support larger rams than 16 Kbyte.

Start address of local data ram

CONFIG_DCACHE_LRSTART

  Defines the 8 MSB bits of start address of the local data ram.

  By default set to 8f (start address = 0x8f000000), but any value

  (except 0) is possible. Note that the local data ram 'shadows'

  a 16 Mbyte block of the address space.

MMU enable

CONFIG_MMU_ENABLE

  Say Y here to enable the Memory Management Unit.

MMU split icache/dcache table lookaside buffer

CONFIG_MMU_COMBINED

  Select "combined" for a combined icache/dcache table lookaside buffer,

  "split" for a split icache/dcache table lookaside buffer

MMU tlb replacement scheme

CONFIG_MMU_REPARRAY

  Select "LRU" to use the "least recently used" algorithm for TLB

  replacement, or "Increment" for a simple incremental replacement

  scheme.

Combined i/dcache tlb

CONFIG_MMU_I2

  Select the number of entries for the instruction TLB, or the

  combined icache/dcache TLB if such is used.

Split tlb, dcache

CONFIG_MMU_D2

  Select the number of entries for the dcache TLB.

Fast writebuffer

CONFIG_MMU_FASTWB

  Only selectable if split tlb is enabled. In case fast writebuffer is

  enabled the tlb hit will be made concurrent to the cache hit. This

  leads to higher store performance, but increased power and area.

DSU enable

CONFIG_DSU_ENABLE

  The debug support unit (DSU) allows non-intrusive debugging and tracing

  of both executed instructions and AHB transfers. If you want to enable

  the DSU, say Y here and select the configuration below.

Trace buffer enable

CONFIG_DSU_TRACEBUF

  Say Y to enable the trace buffer. The buffer is not necessary for

  debugging, only for tracing instructions and data transfers.

Enable instruction tracing

CONFIG_DSU_ITRACE

  If you say Y here, an instruction trace buffer will be implemented

  in each processor. The trace buffer will trace executed instructions

  and their results, and place them in a circular buffer. The buffer

  can be read out by any AHB master, and in particular by the debug

  communication link.

Size of trace buffer

CONFIG_DSU_ITRACESZ1

  Select the buffer size (in kbytes) for the instruction trace buffer.

  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus

  need 2 kbyte.

Enable AHB tracing

CONFIG_DSU_ATRACE

  If you say Y here, an AHB trace buffer will be implemented in the

  debug support unit processor. The AHB buffer will trace all transfers

  on the AHB bus and save them in a circular buffer. The trace buffer

  can be read out by any AHB master, and in particular by the debug

  communication link.

Size of trace buffer

CONFIG_DSU_ATRACESZ1

  Select the buffer size (in kbytes) for the AHB trace buffer.

  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus

  need 2 kbyte.

LEON3FT enable

CONFIG_LEON3FT_EN

  Say Y here to use the fault-tolerant LEON3FT core instead of the

  standard non-FT LEON3.

IU Register file protection

CONFIG_IUFT_NONE

  Select the FT implementation in the LEON3FT integer unit

  register file. The options include parity, parity with

  sparing, 7-bit BCH and TMR.

FPU Register file protection

CONFIG_FPUFT_EN

  Say Y to enable SEU protection of the FPU register file.

  The GRFPU will be protected using 8-bit parity without restart, while

  the GRFPU-Lite will be protected with 4-bit parity with restart. If

  disabled the FPU register file will be implemented using flip-flops.

Cache memory error injection

CONFIG_RF_ERRINJ

  Say Y here to enable error injection in to the IU/FPU regfiles.

  Affects only simulation.

Cache memory protection

CONFIG_CACHE_FT_EN

  Enable SEU error-correction in the cache memories.

Cache memory error injection

CONFIG_CACHE_ERRINJ

  Say Y here to enable error injection in to the cache memories.

  Affects only simulation.

Leon3ft netlist

CONFIG_LEON3_NETLIST

  Say Y here to use a VHDL netlist of the LEON3FT. This is

  only available in certain versions of grlib.

IU assembly printing

CONFIG_IU_DISAS

  Enable printing of executed instructions to the console.

IU assembly printing in netlist

CONFIG_IU_DISAS_NET

  Enable printing of executed instructions to the console also

  when simulating a netlist. NOTE: with this option enabled, it

  will not be possible to pass place&route.

32-bit program counters

CONFIG_DEBUG_PC32

  Since the LSB 2 bits of the program counters always are zero, they are

  normally not implemented. If you say Y here, the program counters will

  be implemented with full 32 bits, making debugging of the VHDL model

  much easier. Turn of this option for synthesis or you will be wasting

  area.

On-chip ram

CONFIG_AHBRAM_ENABLE

  Say Y here to add a block on on-chip ram to the AHB bus. The ram

  provides 0-waitstates read access and 0/1 waitstates write access.

  All AHB burst types are supported, as well as 8-, 16- and 32-bit

  data size.

On-chip ram size

CONFIG_AHBRAM_SZ1

  Set the size of the on-chip AHB ram. The ram is infered/instantiated

  as four byte-wide ram slices to allow byte and half-word write

  accesses. It is therefore essential that the target package can

  infer byte-wide rams. This is currently supported on the generic,

  virtex, virtex2, proasic and axellerator targets.

On-chip ram address

CONFIG_AHBRAM_START

  Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy

  a 1 Mbyte slot at the selected address. Default is A00, corresponding

  to AHB address 0xA0000000.