Subversion Repositories mips_enhanced

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# Clocks

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define_clock            -name {clk_100}  -freq 130.000 -route 1.0 -clockgroup default_clkgroup

define_clock            -name {phy_tx_clk}  -freq 25.000 -clockgroup phy_tx_clkgroup -route 10.000

#define_clock            -name {phy_gtx_clk}  -freq 125.000 -clockgroup phy_gtx_clkgroup -route 2.000

define_clock            -name {leon3mp|egtx_clk}  -freq 125.000 -clockgroup phy_egtx_clkgroup -route 2.000

define_clock            -name {phy_rx_clk}  -freq 125.000 -clockgroup phy_rx_clkgroup -route 2.000

define_clock            -name {leon3mp|clkgen0.clkin}  -freq 100.000 -route 2.0 -clockgroup ahb_clkgroup

#define_clock            -name {leon3mp|eth1.e1.m100.u0.rxclk}  -freq 25.000 -route 10.0 -clockgroup rx100_clkgroup

#define_clock            -name {leon3mp|eth1.e1.m1000.u0.rxclk}  -freq 100.000 -route 2.0 -clockgroup rx1000_clkgroup

define_clock            -name {ddr2spa|ddr_phy0.ddr_phy0.xc4v.ddr_phy0.mclkfx} -freq 200.000 -route 1.0 -clockgroup ddr_clkgroup

define_clock            -name {clk_200}  -freq 200.000 -route 1.0 -clockgroup ddr_clkgroup

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# Clock to Clock

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#define_clock_delay           -rise {clk_100mhz} -fall {clk_100mhz} -false

#define_clock_delay -rise ddr2spa|ddr_phy0.ddr_phy0.xc4v.ddr_phy0.mclkfx -rise leon3mp|clkgen0.xc5l.v.clk0B_derived_clock -false

#define_clock_delay -rise ddr2spa|ddr_phy0.ddr_phy0.xc4v.ddr_phy0.clk_90ro -rise leon3mp|clkgen0.xc5l.v.clk0B_derived_clock -false

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# Inputs/Outputs

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define_output_delay -disable     -default  10.00 -improve 0.00 -route 0.00 -ref {clk:r}

define_input_delay -disable      -default  10.00 -improve 0.00 -route 0.00 -ref {clk:r}

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# Registers

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# Multicycle Path

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# False Path

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# Path Delay

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# Attributes

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define_global_attribute          syn_useioff {1}

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# I/O standards

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# Compile Points

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# Other Constraints

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