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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: greth_gen
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-- File: greth_gen.vhd
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-- Author: Marko Isomaki
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-- Description: Generic Ethernet MAC
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------------------------------------------------------------------------------
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library ieee;
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library grlib;
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use ieee.std_logic_1164.all;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library eth;
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use eth.ethcomp.all;
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entity greth_gen is
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generic(
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memtech : integer := 0;
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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mdcscaler : integer range 0 to 255 := 25;
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enable_mdio : integer range 0 to 1 := 0;
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fifosize : integer range 4 to 64 := 8;
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nsync : integer range 1 to 2 := 2;
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edcl : integer range 0 to 1 := 0;
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edclbufsz : integer range 1 to 64 := 1;
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macaddrh : integer := 16#00005E#;
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macaddrl : integer := 16#000000#;
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ipaddrh : integer := 16#c0a8#;
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ipaddrl : integer := 16#0035#;
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phyrstadr : integer range 0 to 31 := 0;
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rmii : integer range 0 to 1 := 0;
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oepol : integer range 0 to 1 := 0;
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scanen : integer range 0 to 1 := 0);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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--ahb mst in
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hgrant : in std_ulogic;
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hready : in std_ulogic;
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hresp : in std_logic_vector(1 downto 0);
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hrdata : in std_logic_vector(31 downto 0);
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--ahb mst out
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hbusreq : out std_ulogic;
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hlock : out std_ulogic;
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htrans : out std_logic_vector(1 downto 0);
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haddr : out std_logic_vector(31 downto 0);
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hwrite : out std_ulogic;
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hsize : out std_logic_vector(2 downto 0);
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hburst : out std_logic_vector(2 downto 0);
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hprot : out std_logic_vector(3 downto 0);
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hwdata : out std_logic_vector(31 downto 0);
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--apb slv in
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psel : in std_ulogic;
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penable : in std_ulogic;
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paddr : in std_logic_vector(31 downto 0);
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pwrite : in std_ulogic;
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pwdata : in std_logic_vector(31 downto 0);
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--apb slv out
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prdata : out std_logic_vector(31 downto 0);
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--irq
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irq : out std_logic;
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--ethernet input signals
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rmii_clk : in std_ulogic;
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tx_clk : in std_ulogic;
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rx_clk : in std_ulogic;
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rxd : in std_logic_vector(3 downto 0);
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rx_dv : in std_ulogic;
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rx_er : in std_ulogic;
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rx_col : in std_ulogic;
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rx_crs : in std_ulogic;
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mdio_i : in std_ulogic;
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phyrstaddr : in std_logic_vector(4 downto 0);
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--ethernet output signals
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reset : out std_ulogic;
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txd : out std_logic_vector(3 downto 0);
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tx_en : out std_ulogic;
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tx_er : out std_ulogic;
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mdc : out std_ulogic;
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mdio_o : out std_ulogic;
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mdio_oe : out std_ulogic;
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--scantest
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testrst : in std_ulogic;
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testen : in std_ulogic
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);
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end entity;
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architecture rtl of greth_gen is
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function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
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begin
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if (edcl = 1) then
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return ebufsize;
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else
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return fifosize;
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end if;
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end function;
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constant fabits : integer := log2(fifosize);
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type szvct is array (0 to 6) of integer;
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constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
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constant eabits : integer := log2(edclbufsz) + 8;
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constant bufsize : std_logic_vector(2 downto 0) :=
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conv_std_logic_vector(log2(edclbufsz), 3);
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constant ebufsize : integer := ebuf(log2(edclbufsz));
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constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
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constant txfabits : integer := log2(txfifosize);
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--rx ahb fifo
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signal rxrenable : std_ulogic;
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signal rxraddress : std_logic_vector(10 downto 0);
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signal rxwrite : std_ulogic;
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signal rxwdata : std_logic_vector(31 downto 0);
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signal rxwaddress : std_logic_vector(10 downto 0);
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signal rxrdata : std_logic_vector(31 downto 0);
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--tx ahb fifo
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signal txrenable : std_ulogic;
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signal txraddress : std_logic_vector(10 downto 0);
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signal txwrite : std_ulogic;
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signal txwdata : std_logic_vector(31 downto 0);
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signal txwaddress : std_logic_vector(10 downto 0);
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signal txrdata : std_logic_vector(31 downto 0);
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--edcl buf
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signal erenable : std_ulogic;
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signal eraddress : std_logic_vector(15 downto 0);
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signal ewritem : std_ulogic;
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signal ewritel : std_ulogic;
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signal ewaddressm : std_logic_vector(15 downto 0);
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signal ewaddressl : std_logic_vector(15 downto 0);
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signal ewdata : std_logic_vector(31 downto 0);
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signal erdata : std_logic_vector(31 downto 0);
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begin
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ethc0: grethc
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generic map(
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ifg_gap => ifg_gap,
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attempt_limit => attempt_limit,
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backoff_limit => backoff_limit,
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mdcscaler => mdcscaler,
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enable_mdio => enable_mdio,
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fifosize => fifosize,
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nsync => nsync,
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edcl => edcl,
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edclbufsz => edclbufsz,
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macaddrh => macaddrh,
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macaddrl => macaddrl,
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ipaddrh => ipaddrh,
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ipaddrl => ipaddrl,
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phyrstadr => phyrstadr,
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rmii => rmii,
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oepol => oepol,
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scanen => scanen)
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port map(
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rst => rst,
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clk => clk,
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--ahb mst in
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hgrant => hgrant,
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hready => hready,
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hresp => hresp,
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hrdata => hrdata,
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--ahb mst out
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hbusreq => hbusreq,
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hlock => hlock,
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htrans => htrans,
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haddr => haddr,
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hwrite => hwrite,
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hsize => hsize,
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hburst => hburst,
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hprot => hprot,
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hwdata => hwdata,
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--apb slv in
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psel => psel,
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penable => penable,
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paddr => paddr,
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pwrite => pwrite,
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pwdata => pwdata,
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--apb slv out
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prdata => prdata,
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--irq
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irq => irq,
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--rx ahb fifo
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rxrenable => rxrenable,
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rxraddress => rxraddress,
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rxwrite => rxwrite,
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rxwdata => rxwdata,
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rxwaddress => rxwaddress,
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rxrdata => rxrdata,
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--tx ahb fifo
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txrenable => txrenable,
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txraddress => txraddress,
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txwrite => txwrite,
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txwdata => txwdata,
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txwaddress => txwaddress,
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txrdata => txrdata,
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--edcl buf
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erenable => erenable,
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eraddress => eraddress,
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ewritem => ewritem,
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ewritel => ewritel,
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ewaddressm => ewaddressm,
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ewaddressl => ewaddressl,
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ewdata => ewdata,
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erdata => erdata,
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--ethernet input signals
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rmii_clk => rmii_clk,
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tx_clk => tx_clk,
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rx_clk => rx_clk,
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rxd => rxd(3 downto 0),
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rx_dv => rx_dv,
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rx_er => rx_er,
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rx_col => rx_col,
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rx_crs => rx_crs,
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mdio_i => mdio_i,
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phyrstaddr => phyrstaddr,
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--ethernet output signals
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reset => reset,
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txd => txd(3 downto 0),
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tx_en => tx_en,
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tx_er => tx_er,
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mdc => mdc,
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mdio_o => mdio_o,
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mdio_oe => mdio_oe,
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--scantest
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testrst => testrst,
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testen => testen);
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-------------------------------------------------------------------------------
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-- FIFOS ----------------------------------------------------------------------
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-------------------------------------------------------------------------------
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tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
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dbits => 32, sepclk => 0)
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port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
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txwrite, txwaddress(txfabits-1 downto 0), txwdata);
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rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
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dbits => 32, sepclk => 0)
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port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
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rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
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-------------------------------------------------------------------------------
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-- EDCL buffer ram ------------------------------------------------------------
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-------------------------------------------------------------------------------
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edclram : if (edcl = 1) generate
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rloopm : for i in 0 to 1 generate
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r0 : syncram_2p generic map (memtech, eabits, 8) port map(
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clk, erenable, eraddress(eabits-1 downto 0), erdata(i*8+23 downto i*8+16), clk,
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ewritem, ewaddressm(eabits-1 downto 0), ewdata(i*8+23 downto i*8+16));
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end generate;
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rloopl : for i in 0 to 1 generate
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r0 : syncram_2p generic map (memtech, eabits, 8) port map(
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clk, erenable, eraddress(eabits-1 downto 0), erdata(i*8+7 downto i*8), clk,
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ewritel, ewaddressl(eabits-1 downto 0), ewdata(i*8+7 downto i*8));
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end generate;
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end generate;
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end architecture;
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