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https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
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Author |
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1 |
2 |
dimamali |
CAN interface enable
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2 |
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CONFIG_CAN_ENABLE
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3 |
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Say Y here to enable the CAN interace from OpenCores. The core has one
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4 |
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AHB slave interface for accessing the control registers. The CAN core
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5 |
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ir register-compatible with the SAJ1000 core from Philips.
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6 |
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7 |
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CAN register address
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8 |
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CONFIG_CANIO
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9 |
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The control registers of the CAN core occupy 4 kbyte, and are
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10 |
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mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting
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11 |
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defines at which address in the I/O area the registers appear (HADDR[19:8]).
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12 |
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13 |
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CAN interrupt
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14 |
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CONFIG_CANIRQ
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15 |
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Defines which interrupt number the CAN core will generate.
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16 |
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17 |
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CAN loob-back testing
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18 |
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CONFIG_CANLOOP
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19 |
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If you say Y here, the receiver and trasmitter of the CAN core will
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20 |
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be connected together in a loop-back fashion. This will make it
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21 |
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possible to perform loop-back test, but not data will be sent
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22 |
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or received from the outside. ONLY for testing!
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23 |
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24 |
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CAN Synchronous reset
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25 |
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CONFIG_CAN_SYNCRST
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26 |
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If you say Y here, the CAN core will be implemented with
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27 |
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synchronous reset rather than asynchronous. This is needed
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28 |
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when the target library does not implement registers with
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29 |
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async reset. Unless you know what you are doing, say N.
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30 |
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31 |
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CAN FT memories
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32 |
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CONFIG_CAN_FT
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33 |
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If you say Y here, the CAN FIFOs will be implemented using
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34 |
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SEU protected RAM blocks. Only applicable to the FT version
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35 |
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of grlib.
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