Subversion Repositories mips_enhanced

------------------------------------------------------------------------------

--  This file is a part of the GRLIB VHDL IP LIBRARY

--  Copyright (C) 2003, Gaisler Research

--

--  This program is free software; you can redistribute it and/or modify

--  it under the terms of the GNU General Public License as published by

--  the Free Software Foundation; either version 2 of the License, or

--  (at your option) any later version.

--

--  This program is distributed in the hope that it will be useful,

--  but WITHOUT ANY WARRANTY; without even the implied warranty of

--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--  GNU General Public License for more details.

--

--  You should have received a copy of the GNU General Public License

--  along with this program; if not, write to the Free Software

--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-----------------------------------------------------------------------------

-- Entity:  ddrsp32a

-- File:    ddrsp32a.vhd

-- Author:  Jiri Gaisler - Gaisler Research

-- Description: 32-bit DDR266 memory controller with asych AHB interface

------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

library grlib;

use grlib.amba.all;

use grlib.stdlib.all;

library gaisler;

use grlib.devices.all;

use gaisler.memctrl.all;

library techmap;

use techmap.gencomp.all;

entity ddrsp32a is

  generic (

    memtech : integer := 0;

    hindex  : integer := 0;

    haddr   : integer := 0;

    hmask   : integer := 16#f00#;

    ioaddr  : integer := 16#000#;

    iomask  : integer := 16#fff#;

    MHz     : integer := 100;

    col     : integer := 9;

    Mbyte   : integer := 8;

    fast    : integer := 0;

    pwron   : integer := 0;

    oepol   : integer := 0;

    mobile  : integer := 0;

    confapi : integer := 0;

    conf0   : integer := 0;

    conf1   : integer := 0;

    regoutput : integer := 0

  );

  port (

    rst     : in  std_ulogic;

    clk_ddr : in  std_ulogic;

    clk_ahb : in  std_ulogic;

    ahbsi   : in  ahb_slv_in_type;

    ahbso   : out ahb_slv_out_type;

    sdi     : in  sdctrl_in_type;

    sdo     : out sdctrl_out_type

  );

end;

architecture rtl of ddrsp32a is

constant REVISION  : integer := 0;

constant CMD_PRE  : std_logic_vector(2 downto 0) := "010";

constant CMD_REF  : std_logic_vector(2 downto 0) := "100";

constant CMD_LMR  : std_logic_vector(2 downto 0) := "110";

constant CMD_EMR  : std_logic_vector(2 downto 0) := "111";

constant PM_PD    : std_logic_vector(2 downto 0) := "001";

constant PM_SR    : std_logic_vector(2 downto 0) := "010";

constant PM_CKS   : std_logic_vector(2 downto 0) := "100";

constant PM_DPD   : std_logic_vector(2 downto 0) := "101";

constant abuf : integer := 6;

constant hconfig : ahb_config_type := (

  4 => ahb_membar(haddr, '1', '1', hmask),

  5 => ahb_iobar(ioaddr, iomask),

  others => zero32);

type mcycletype is (midle, active, ext, leadout);

type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);

type sdcycletype is (act1, act2, act3, rd1, rd2, rd2a, rd3, rd3a, rd4, rd5, rd6, rd7, rd8,

                     wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2,

                     sref, cks, pd, dpd, srr1, srr2, srr3);

type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);

-- sdram configuration register

type sdram_cfg_type is record

  command     : std_logic_vector(2 downto 0);

  csize       : std_logic_vector(1 downto 0);

  bsize       : std_logic_vector(2 downto 0);

  trcd        : std_ulogic;  -- tCD : 2/3 clock cycles

  trfc        : std_logic_vector(2 downto 0);

  trp         : std_ulogic;  -- precharge to activate: 2/3 clock cycles

  refresh     : std_logic_vector(11 downto 0);

  renable     : std_ulogic;

  dllrst      : std_ulogic;

  refon       : std_ulogic;

  cke         : std_ulogic;

  pasr        : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)

  tcsr        : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)

  ds          : std_logic_vector(5 downto 0); -- ds(1:0) (ds(3:2) used to detect update)

  pmode       : std_logic_vector(2 downto 0); -- Power-Saving mode

  mobileen    : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled

  txsr        : std_logic_vector(3 downto 0); -- Exit Self Refresh timing

  txp         : std_logic; -- Exit Power-Down timing

  tcke        : std_logic; -- Clock enable timing

  cl          : std_logic; -- CAS latency 2/3 (0/1)

  conf        : std_logic_vector(63 downto 0); -- PHY control

end record;

type access_param is record

  haddr         : std_logic_vector(31 downto 0);

  size          : std_logic_vector(1 downto 0);

  hwrite        : std_ulogic;

  hio           : std_ulogic;

end record;

-- local registers

type ahb_reg_type is record

  hready        : std_ulogic;

  hsel          : std_ulogic;

  hio           : std_ulogic;

  startsd       : std_ulogic;

  ready         : std_ulogic;

  ready2        : std_ulogic;

  write         : std_logic_vector(1 downto 0);

  state         : ahb_state_type;

  haddr         : std_logic_vector(31 downto 0);

  hrdata        : std_logic_vector(31 downto 0);

  hwdata        : std_logic_vector(31 downto 0);

  hwrite        : std_ulogic;

  htrans        : std_logic_vector(1 downto 0);

  hresp         : std_logic_vector(1 downto 0);

  raddr         : std_logic_vector(abuf-1 downto 0);

  size          : std_logic_vector(1 downto 0);

  acc           : access_param;

end record;

type ddr_reg_type is record

  startsd       : std_ulogic;

  startsdold    : std_ulogic;

  burst         : std_ulogic;

  hready        : std_ulogic;

  bdrive        : std_ulogic;

  qdrive        : std_ulogic;

  nbdrive       : std_ulogic;

  mstate        : mcycletype;

  sdstate       : sdcycletype;

  cmstate       : mcycletype;

  istate        : icycletype;

  trfc          : std_logic_vector(3 downto 0);

  refresh       : std_logic_vector(11 downto 0);

  sdcsn         : std_logic_vector(1  downto 0);

  sdwen         : std_ulogic;

  rasn          : std_ulogic;

  casn          : std_ulogic;

  dqm           : std_logic_vector(7 downto 0);

  dqm_dly       : std_logic_vector(7 downto 0);   -- *** ??? delay ctrl

  wdata         : std_logic_vector(63 downto 0);    -- *** ??? delay ctrl

  address       : std_logic_vector(15 downto 2);  -- memory address

  ba            : std_logic_vector(1  downto 0);

  waddr         : std_logic_vector(abuf-1 downto 0);

  cfg           : sdram_cfg_type;

  hrdata        : std_logic_vector(63 downto 0);

  idlecnt       : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode 

  ck            : std_logic_vector(2 downto 0); -- Clock stop signal, 0 = clock stoped, 1 = clock running

  txp           : std_logic;

  tcke          : std_logic;

  sref_tmpcom   : std_logic_vector(2 downto 0); -- Save SD command when exit sref

  extdqs        : std_logic; -- Extend dqs postamble

  sdo_bdrive    : std_logic; -- *** ??? delay ctrl

  sdo_qdrive    : std_logic; -- *** ??? delay ctrl

  ck_dly        : std_logic_vector(2 downto 0); -- *** ??? delay ctrl

  cke_dly       : std_logic; -- *** ??? delay ctrl

end record;

signal vcc : std_ulogic;

signal r, ri : ddr_reg_type;

signal ra, rai : ahb_reg_type;

signal rbdrive, ribdrive : std_logic_vector(31 downto 0);

signal rdata, wdata : std_logic_vector(63 downto 0);

signal ddr_rst : std_logic;

signal ddr_rst_gen  : std_logic_vector(3 downto 0);

attribute syn_preserve : boolean;

attribute syn_preserve of rbdrive : signal is true;

begin

  vcc <= '1';

  ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain

  ahb_ctrl : process(rst, ahbsi, r, ra, rdata)

  variable v       : ahb_reg_type;              -- local variables for registers

  variable startsd : std_ulogic;

  variable dout    : std_logic_vector(31 downto 0);

  begin

    v := ra; v.hresp := HRESP_OKAY; v.write := "00";

    if ra.raddr(0) = '0' then v.hrdata := rdata(63 downto 32);

    else v.hrdata := rdata(31 downto 0); end if;

    v.ready := not (ra.startsd xor r.startsdold);

    v.ready2 := ra.ready;

    if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then

      v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;

      v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;

      if ahbsi.htrans(1) = '1' then

        v.hio := ahbsi.hmbsel(1);

        v.hsel := '1'; v.hready := '0';

      end if;

    end if;

    if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;

    case ra.state is

    when midle =>

      if ((v.hsel and v.htrans(1)) = '1') then

        if v.hwrite = '0' then

          v.state := rhold; v.startsd := not ra.startsd;

        else

          v.state := dwrite; v.hready := '1';

          v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);

        end if;

      end if;

      v.raddr := ra.haddr(7 downto 2);

      v.ready := '0'; v.ready2 := '0';

      if ahbsi.hready = '1' then

        v.acc := (v.haddr, v.size, v.hwrite, v.hio);

      end if;

    when rhold =>

      v.raddr := ra.haddr(7 downto 2);

      if ra.ready2 = '1' then

        v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;

      end if;

    when dread =>

      v.raddr := ra.raddr + 1; v.hready := '1';

      if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or

          (ra.raddr(2 downto 0) = "000")

      then v.state := midle; v.hready := '0'; end if;

      v.acc := (v.haddr, v.size, v.hwrite, v.hio);

    when dwrite =>

      v.raddr := ra.haddr(7 downto 2); v.hready := '1';

      v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);

      if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or

          (ra.haddr(4 downto 2) = "111")

      then

        v.startsd := not ra.startsd; v.state := whold1;

        v.write := "00"; v.hready := '0';

      end if;

    when whold1 =>

      v.state := whold2; v.ready := '0';

    when whold2 =>

      if ra.ready = '1' then

        v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);

      end if;

    end case;

    v.hwdata := ahbsi.hwdata;

    if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then

      if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;

    end if;

    dout := ra.hrdata(31 downto 0);

    if rst = '0' then

      v.hsel      := '0';

      v.hready    := '1';

      v.state     := midle;

      v.startsd   := '0';

      v.hio       := '0';

    end if;

    rai <= v;

    ahbso.hready  <= ra.hready;

    ahbso.hresp   <= ra.hresp;

    ahbso.hrdata  <= dout;

    ahbso.hcache  <= not ra.hio;

  end process;

  ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)

  variable v       : ddr_reg_type;            -- local variables for registers

  variable startsd : std_ulogic;

  variable dqm     : std_logic_vector(7 downto 0);

  variable raddr   : std_logic_vector(13 downto 0);

  variable adec    : std_ulogic;

  variable rams    : std_logic_vector(1 downto 0);

  variable ba      : std_logic_vector(1 downto 0);

  variable haddr   : std_logic_vector(31 downto 0);

  variable hsize   : std_logic_vector(1 downto 0);

  variable hwrite  : std_ulogic;

  variable htrans  : std_logic_vector(1 downto 0);

  variable hready  : std_ulogic;

  variable vbdrive : std_logic_vector(31 downto 0);

  variable bdrive  : std_ulogic;

  variable writecfg: std_ulogic;

  variable regsd1   : std_logic_vector(31 downto 0);   -- data from registers

  variable regsd2   : std_logic_vector(31 downto 0);   -- data from registers

  variable regsd3   : std_logic_vector(31 downto 0);   -- data from registers

  variable arefresh : std_logic;

  begin

-- Variable default settings to avoid latches

    v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;

    v.hrdata := sdi.data(63 downto 0); v.qdrive :='0'; v.txp := '0'; v.tcke := '0';

    arefresh := '0';

    v.wdata := wdata;                                                               -- *** ??? delay ctrl

    v.dqm_dly := r.dqm;                                                             -- *** ??? delay ctrl

    v.ck_dly := r.ck;                                                               -- *** ??? delay ctrl

    v.cke_dly := r.cfg.cke;                                                         -- *** ??? delay ctrl

    regsd1 := (others => '0');

    regsd1(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &

                            r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &

                            r.cfg.dllrst & r.cfg.renable & r.cfg.cke;

    regsd1(11 downto 0) := r.cfg.refresh;

    regsd2 := (others => '0');

    regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);

    regsd2(14 downto 12) := conv_std_logic_vector(2, 3);

    regsd2(15) := r.cfg.mobileen(1); -- Mobile DDR support

    regsd2(19 downto 16) := conv_std_logic_vector(confapi, 4);

    regsd3 := (others => '0');

    regsd3(31) := r.cfg.mobileen(0); -- Mobile DDR enable

    regsd3(24 downto 19) := r.cfg.tcke & r.cfg.txsr & r.cfg.txp;

    regsd3(18 downto 16) := r.cfg.pmode;

    regsd3( 7 downto  0) := r.cfg.ds(2 downto 0) & r.cfg.tcsr(1 downto 0)

                            & r.cfg.pasr(2 downto 0);

    if ra.acc.haddr(4) = '1' and confapi /= 0 then

      regsd2(31 downto 0) := r.cfg.conf(31 downto 0);

      regsd3(31 downto 0) := r.cfg.conf(63 downto 32);

    end if;

-- generate DQM from address and write size

    case ra.acc.size is

    when "00" =>

      case ra.acc.haddr(2 downto 0) is

      when "000" => dqm := "01111111";

      when "001" => dqm := "10111111";

      when "010" => dqm := "11011111";

      when "011" => dqm := "11101111";

      when "100" => dqm := "11110111";

      when "101" => dqm := "11111011";

      when "110" => dqm := "11111101";

      when others => dqm := "11111110";

      end case;

    when "01" =>

      case ra.acc.haddr(2 downto 1) is

      when "00"   => dqm := "00111111";

      when "01"   => dqm := "11001111";

      when "10"   => dqm := "11110011";

      when others => dqm := "11111100";

      end case;

    when others => dqm := "00000000";

    end case;

    v.startsd := ra.startsd;

-- main FSM

    case r.mstate is

    when midle =>

      if  r.startsd = '1' then

        if (r.sdstate = sidle) and (r.cfg.command = "000") and

           (r.cmstate = midle)

        then

          startsd := '1'; v.mstate := active;

        end if;

      end if;

    when others => null;

    end case;

    startsd := r.startsd xor r.startsdold;

-- generate row and column address size

    haddr := ra.acc.haddr;

    haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);

    case r.cfg.csize is

    when "00" => raddr := haddr(24 downto 11);

    when "01" => raddr := haddr(25 downto 12);

    when "10" => raddr := haddr(26 downto 13);

    when others => raddr := haddr(27 downto 14);

    end case;

-- generate bank address

    ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &

          genmux(r.cfg.bsize, haddr(28 downto 21));

-- generate chip select

    adec := genmux(r.cfg.bsize, haddr(30 downto 23));

    rams := adec & not adec;

-- sdram access FSM

    if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;

    if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;

    case r.sdstate is

    when sidle =>

      v.extdqs := '1';

      if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)

         and (r.istate = finish)

      then

        v.address := raddr; v.ba := ba;

        if ra.acc.hio = '0' then

          v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;

        elsif ra.acc.haddr(4 downto 2) = "100" and r.cfg.mobileen(0) = '1' then v.sdstate := srr1;

        else v.sdstate := ioreg1; end if;

      elsif (r.cfg.command = "000") and (r.cmstate = midle)

            and (r.istate = finish) and r.idlecnt = "0000" and (r.cfg.mobileen(1) = '1') then

        case r.cfg.pmode is

        when PM_SR => v.cfg.cke := '0'; v.sdstate := sref;

        when PM_CKS => v.ck := (others => '0'); v.sdstate := cks;

        when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;

        when PM_DPD => v.cfg.cke := '0'; v.sdstate := dpd;

        when others =>

        end case;

        if r.cfg.pmode /= "000" then v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; end if; -- Extend trfc for mobile ddr

      end if;

      v.waddr := ra.acc.haddr(7 downto 2);

    when act1 =>

      v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;  -- Extend trfc for mobile ddr

      if r.cfg.trcd = '1' then v.sdstate := act2; else

        v.sdstate := act3; v.hready := ra.acc.hwrite;

      end if;

      v.waddr := ra.acc.haddr(7 downto 2);

    when act2 =>

      v.sdstate := act3; v.hready := ra.acc.hwrite;

    when act3 =>

      v.casn := '0';

      v.address := ra.acc.haddr(14 downto 12) & '0' & ra.acc.haddr(11 downto 3) & '0';

      v.dqm := dqm;

      if ra.acc.hwrite = '1' then

        v.waddr := r.waddr + 2; v.waddr(0) := '0';

        v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';

        if (r.waddr /= ra.raddr) then v.hready := '1';

          if r.waddr(0) = '1' then v.dqm(7 downto 4) := (others => '1'); end if;

        else

          if r.waddr(0) = '0' then v.dqm(3 downto 0) := (others => '1');

          else v.dqm(7 downto 4) := (others => '1'); end if;

        end if;

      else v.sdstate := rd1; end if;

    when wr1 =>

      v.sdwen := '1';  v.casn := '1';  v.qdrive := '1';

      v.waddr := r.waddr + 2; v.dqm(7 downto 4) := (others => '0');

      v.address(8 downto 3) := r.waddr;

      if (r.waddr <= ra.raddr) and (r.waddr(5 downto 1) /= "00000") and (r.hready = '1')

      then

        v.extdqs := '0';

        v.hready := '1';

        if (r.hready = '1') and (r.waddr(2 downto 0) = "000") then

          v.sdwen := '0'; v.casn := '0'; v.extdqs := '1';

        end if;

        if  (r.waddr = ra.raddr) and (r.waddr /= "000000") and (r.waddr(0) = '0') then

          v.dqm(3 downto 0) := (others => '1');

        end if;

      else

        v.sdstate := wr2;

        v.dqm := (others => '1'); --v.bdrive := '1'; 

        v.startsdold := r.startsd;

      end if;

    when wr2 =>

      v.sdstate := wr3; v.qdrive := '1';

    when wr3 =>

      v.sdstate := wr4a; v.qdrive := '1';

    when wr4a =>

      v.bdrive := '1';

      v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';

    when wr4 =>

      v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; --v.qdrive := '0';

      if r.extdqs = '1' then v.qdrive := '1'; else v.qdrive := '0'; end if;

      v.sdstate := wr5;

    when wr5 =>

      v.sdstate := sidle;

      v.qdrive := '0';

      v.idlecnt := (others => '1');

    when rd1 =>

      v.casn := '1'; v.sdstate := rd7;

--      if ra.acc.haddr(4 downto 2) = "011" then 

--        v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";

--      end if;

    when rd7 =>

      v.casn := '1'; v.sdstate := rd2;

--      if ra.acc.haddr(4 downto 2) = "010" then 

--        v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";

--      end if;

    when rd2 =>

      --v.casn := '1'; v.sdstate := rd3;

      v.casn := '1';

      if regoutput = 1 then v.sdstate := rd2a; else v.sdstate := rd3; end if; -- delay if registered output

--      if ra.acc.haddr(4 downto 2) = "001" then 

--        v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";

--      end if;

--      if v.sdwen = '0' then v.dqm := (others => '1'); end if;

    when rd2a => -- delay if registered output

    v.sdstate := rd3;

    when rd3 =>

      if r.cfg.cl = '0' then -- CL = 2

        if fast = 0 then v.startsdold := r.startsd; end if;

        v.sdstate := rd4; v.hready := '1'; v.casn := '1';

      else -- CL = 3

        v.sdstate := rd3a; v.hready := '0'; v.casn := '1';

      end if;

--      if r.sdwen = '0' then

--        v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');

--      elsif ra.acc.haddr(4 downto 2) = "000" then 

--        v.casn := '0'; v.burst := '1'; v.address(5) := '1';

--        v.waddr := v.address(8 downto 3);

--      end if;

      if v.hready = '1' then v.waddr := r.waddr + 2; end if;

    when rd3a =>

      if fast = 0 then v.startsdold := r.startsd; end if;

      v.sdstate := rd4; v.hready := '1'; v.casn := '1';

      if v.hready = '1' then v.waddr := r.waddr + 2; end if;

    when rd4 =>

      v.hready := '1'; v.casn := '1';

--      if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')

--      then

--        v.burst := '0';

      if (r.sdcsn = "11") or (r.waddr(2 downto 1) = "11") then

        v.dqm := (others => '1'); v.burst := '0';

        if fast /= 0 then v.startsdold := r.startsd; end if;

        if (r.sdcsn /= "11") then

          v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;

        else

          if r.cfg.trp = '1' then v.sdstate := rd6;

          else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;

        end if;

      end if;

      if v.hready = '1' then v.waddr := r.waddr + 2; end if;

    when rd5 =>

      if r.cfg.trp = '1' then v.sdstate := rd6;

      else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;

      v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';

      v.dqm := (others => '1');