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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [leon3/] [mmulrue.vhd] - Blame information for rev 2

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1 2 dimamali
------------------------------------------------------------------------------
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--  This file is a part of the GRLIB VHDL IP LIBRARY
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--  Copyright (C) 2003, Gaisler Research
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--
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--  This program is free software; you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation; either version 2 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program; if not, write to the Free Software
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--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-----------------------------------------------------------------------------
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-- Entity:      mmulrue
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-- File:        mmulrue.vhd
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-- Author:      Konrad Eisele, Jiri Gaisler, Gaisler Research
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-- Description: MMU LRU logic
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.libiu.all;
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use gaisler.libcache.all;
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use gaisler.leon3.all;
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use gaisler.mmuconfig.all;
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use gaisler.mmuiface.all;
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entity mmulrue is
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  generic (
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    position : integer;
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    entries  : integer := 8 );
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  port (
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    rst    : in std_logic;
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    clk    : in std_logic;
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    lruei  : in mmulrue_in_type;
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    lrueo  : out mmulrue_out_type );
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end mmulrue;
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architecture rtl of mmulrue is
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  constant entries_log : integer := log2(entries);
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  type lru_rtype is record
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    pos      : std_logic_vector(entries_log-1 downto 0);
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    movetop  : std_logic;
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    -- pragma translate_off
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    dummy  : std_logic;
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    -- pragma translate_on
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  end record;
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  signal c,r   : lru_rtype;
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begin
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  p0: process (rst, r, c, lruei)
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    variable v : lru_rtype;
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    variable ov : mmulrue_out_type;
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  begin
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    v := r; ov := mmulrue_out_none;
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    -- #init
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    if (r.movetop) = '1' then
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      if (lruei.fromleft) = '0' then
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        v.pos := lruei.left(entries_log-1 downto 0);
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        v.movetop := '0';
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      end if;
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    elsif (lruei.fromright) = '1' then
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      v.pos := lruei.right(entries_log-1 downto 0);
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      v.movetop := not lruei.clear;
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    end if;
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    if (lruei.touch and not lruei.clear) = '1' then  -- touch request
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      if (v.pos = lruei.pos(entries_log-1 downto 0)) then     -- check
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          v.movetop := '1';
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      end if;
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    end if;
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    if ((rst) = '0') or (lruei.flush = '1') then
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      v.pos := conv_std_logic_vector(position, entries_log);
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      v.movetop := '0';
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    end if;
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    --# Drive signals
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    ov.pos(entries_log-1 downto 0) := r.pos;
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    ov.movetop := r.movetop;
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    lrueo <= ov;
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    c <= v;
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  end process p0;
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  p1: process (clk)
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  begin if rising_edge(clk) then r <= c; end if;
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  end process p1;
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end rtl;
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