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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [memctrl/] [sdctrl.in.help] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
SDRAM controller enable
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CONFIG_SDCTRL
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  Say Y here to enabled a 32/64-bit PC133 SDRAM controller.
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SDRAM controller inverted clock
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CONFIG_SDCTRL_INVCLK
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  If you say Y here, the SDRAM clock will be inverted in respect to the
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  system clock and the SDRAM signals. This will limit the SDRAM frequency
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  to 50/66 MHz, but has the benefit that you will not need a PLL to
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  generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets,
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  say N and tell your foundry to balance the SDRAM clock output.
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64-bit data bus
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CONFIG_SDCTRL_BUS64
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  Say Y here to enable 64-bit data bus.
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Page burst enable
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CONFIG_SDCTRL_PAGE
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  Say Y here to enable SDRAM page burst operation. This will implement
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  read operations using page bursts rather than 8-word bursts and save
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  about 500 gates (100 LUTs). Note that not all SDRAM supports page
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  burst, so use this option with care.
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Programmable page burst enable
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CONFIG_SDCTRL_PROGPAGE
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  Say Y here to enable programmable SDRAM page burst operation. This
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  will allow to dynamically enable/disable page burst by setting
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  bit 17 in MCFG2.
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