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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [vlog/] [core1.v.bak] - Blame information for rev 2

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`include "mips789_defs.v"
 
module mips_core (
        clk,rst,zz_ins_i,iack_o,qa,qb,wb_din_o,rdaddra_o,rdaddrb_o,wb_addr_o,wb_we_o,
       zz_pc_o,dmem_ctl_ur_o,alu_ur_o,dmem_data_ur_o,dout,size,branch,hold,imds,dmds,asi_pass2, pc_next
    );
 
    input clk;
    wire clk;
    input rst;
    wire rst;
    input [31:0] zz_ins_i;
    wire [31:0] zz_ins_i;
         wire [31:0] zz_ins_o;
    input [31:0] dout;
    wire [31:0] dout;
         input [31:0] qa;
         wire [31:0] qa;
         input [31:0] qb;
         wire [31:0] qb;
    output [31:0] zz_pc_o;
    wire [31:0] zz_pc_o;
    output iack_o;
    wire iack_o;
    wire [31:0] cop_addr_o;
    output [4:0] dmem_ctl_ur_o;
    output [31:0] alu_ur_o;
    output [31:0] dmem_data_ur_o;
    wire [4:0] dmem_ctl_ur_o;
    wire [31:0] alu_ur_o;
    wire [31:0] dmem_data_ur_o;
         output [31:0] wb_din_o;
         wire [31:0] wb_din_o;
         output [4:0] rdaddra_o;
         wire [4:0] rdaddra_o;
         output [4:0] rdaddrb_o;
         wire [4:0] rdaddrb_o;
         output [4:0] wb_addr_o;
         wire [4:0] wb_addr_o;
         output wb_we_o;
         wire wb_we_o;
         output [1:0] size;
         wire [1:0] size;
         output branch;
         wire branch;
         input hold;
         wire hold;
         input imds;
         wire imds;
         input dmds;
         wire dmds;
         output [4:0] asi_pass2;
         output [31:0] pc_next;
 
         wire [31:0] pc_next;
    wire load;
         wire load_o;
         wire [4:0]rt_o;
    wire NET1375;
    wire NET1572;
    wire NET1606;
    wire NET1640;
    wire NET21531;
    wire NET457;
    wire NET767;
    wire [2:0] BUS109;
    wire [2:0] BUS1158;
    wire [2:0] BUS117;
    wire [2:0] BUS1196;
    wire [31:0] BUS15471;
    wire [4:0] BUS1724;
    wire [4:0] BUS1726;
    wire [4:0] BUS18211;
    wire [2:0] BUS197;
    wire [2:0] BUS2140;
    wire [2:0] BUS2156;
    wire [31:0] BUS22401;
    wire [31:0] BUS24839;
    wire [31:0] BUS27031;
    wire [2:0] BUS271;
    wire [31:0] BUS28013;
    wire [1:0] BUS371;
    wire [31:0] BUS422;
    wire [1:0] BUS5832;
    wire [1:0] BUS5840;
    wire [2:0] BUS5993;
    wire [4:0] BUS6275;
    wire [31:0] BUS7101;
    wire [31:0] BUS7117;
    wire [31:0] BUS7160;
    wire [31:0] BUS7219;
    wire [31:0] BUS7231;
    wire [4:0] BUS748;
    wire [4:0] BUS756;
    wire [4:0] BUS775;
    wire [31:0] BUS7772;
    wire [31:0] BUS7780;
    wire [31:0] BUS9884;
         wire [4:0] asi_o;
         wire [4:0] asi_pass1;
         wire [4:0] asi_pass2;
         wire [4:0] rdaddra1;
         wire [4:0] rdaddrb1;
 
 
 
    assign NET21531 = NET1572 | iack_o;
 
    rf_stage iRF_stage
             (   .hold(hold),
                 .clk(clk),
                 .cmp_ctl_i(BUS109),
                 .ext_ctl_i(BUS117),
                 .ext_o(BUS7219),
                 .fw_alu_i(cop_addr_o),
                 .fw_cmp_rs(BUS2140),
                 .fw_cmp_rt(BUS2156),
                 .fw_mem_i(wb_din_o),
                 .iack_o(iack_o),
                 .id2ra_ctl_clr_o(NET1606),
                 .id2ra_ctl_cls_o(NET1572),
                 .id_cmd(BUS197),
                 .ins_i(zz_ins_o),
                 .pc_gen_ctl(BUS271),
                                          .branch(branch),
                 .pc_i(zz_pc_o),
                 .pc_next(pc_next),
                 .ra2ex_ctl_clr_o(NET1640),
                 .rd_index_o(BUS775),
                 .rd_sel_i(BUS371),
                 .rs_n_o(BUS748),
                 .rs_o(BUS24839),
                 .rst_i(rst),
                 .rt_n_o(BUS756),
                 .rt_o(BUS7160),
                 .wb_din_i(wb_din_o),
                 .zz_spc_i(BUS28013),
                                          .rdaddra1(rdaddra1),
                                          .rdaddrb1(rdaddrb1),
                                          .qa(qa),
                                          .qb(qb)
             );
 
 
 
    exec_stage iexec_stage
               (.hold(hold),
                   .alu_func(BUS6275),
                   .alu_ur_o(alu_ur_o),
                   .clk(clk),
                   .dmem_data_ur_o(dmem_data_ur_o),
                   .dmem_fw_ctl(BUS5993),
                   .ext_i(BUS7231),
                   .fw_alu(cop_addr_o),
                   .fw_dmem(wb_din_o),
                   .muxa_ctl_i(BUS5832),
                   .muxa_fw_ctl(BUS1158),
                   .muxb_ctl_i(BUS5840),
                   .muxb_fw_ctl(BUS1196),
                   .pc_i(zz_pc_o),
                   .rs_i(BUS7101),
                   .rst(rst),
                   .rt_i(BUS7117),
                   .spc_cls_i(NET21531),
                   .zz_spc_o(BUS28013)
               );
 
 
 
    r32_reg alu_pass0
            (.hold(hold),
                .clk(clk),
                .r32_i(alu_ur_o),
                .r32_o(cop_addr_o)
            );
 
 
 
    r32_reg alu_pass1
            (.hold(hold),
                .clk(clk),
                .r32_i(cop_addr_o),
                .r32_o(BUS422)
            );
 
        r32_inst_reg instruction
            (    .hold(hold),
                                         .branch(branch),
                                         .imds(imds),
                .clk(clk),
                .r32_i(zz_ins_i),
                .r32_o(zz_ins_o)
            );
 
 
 
//    or32 cop_data_or
//         (
//             .a(cop_dout),
//             .b(BUS7772),
//             .c(BUS7780)
//         );
 
 
 
//    r32_reg cop_data_reg
//            (
//                .clk(clk),
//                .r32_i(BUS9884),
//                .r32_o(cop_data_o)
//            );
 
 
 
/*    r32_reg cop_dout_reg
            (.hold(hold),
                .clk(clk),
                .r32_i(dout),
                .r32_o(BUS7780)
            );
        */
 
        r32_data_reg cop_dout_reg
            (    .hold(hold),
                                         .dmds(dmds),
                .clk(clk),
                .r32_i(dout),
                .r32_o(BUS7780)
            );
 
 
 
    decode_pipe decoder_pipe
                (.hold(hold),
                                                  .rt1(rt_o),
                                                  .load(load_o),
                                                  .load_o(load),
                    .alu_func_o(BUS6275),
                                                  .size(size),
                    .alu_we_o(NET767),
                    .clk(clk),
                    .cmp_ctl_o(BUS109),
                    .dmem_ctl_ur_o(dmem_ctl_ur_o),
                    .ext_ctl_o(BUS117),
                    .fsm_dly(BUS197),
                    .id2ra_ctl_clr(NET1606),
                    .id2ra_ctl_cls(NET1572),
                    .ins_i(zz_ins_o),
                    .muxa_ctl_o(BUS5832),
                    .muxb_ctl_o(BUS5840),
                    .pc_gen_ctl_o(BUS271),
                    .ra2ex_ctl_clr(NET1640),
                    .rd_sel_o(BUS371),
                    .wb_mux_ctl_o(NET457),
                    .wb_we_o(wb_we_o),
                                                  .asi(asi_o)
                );
 
 
 
    r32_reg ext_reg
            (.hold(hold),
                .clk(clk),
                .r32_i(BUS7219),
                .r32_o(BUS7231)
            );
 
 
 
    forward iforward
            (.hold(hold),
                .alu_rs_fw(BUS1158),
                .alu_rt_fw(BUS1196),
                .alu_we(NET767),
                .clk(clk),
                .cmp_rs_fw(BUS2140),
                .cmp_rt_fw(BUS2156),
                .dmem_fw(BUS5993),
                .fw_alu_rn(BUS1724),
                .fw_mem_rn(wb_addr_o),
                .mem_We(wb_we_o),
                .rns_i(BUS748),
                .rnt_i(BUS756)
            );
 
 
 
    r32_reg pc
            (.hold(hold),
                .clk(clk),
                .r32_i(pc_next),
                .r32_o(zz_pc_o)
            );
 
 
 
    r5_reg rnd_pass0
           (.hold(hold),
               .clk(clk),
               .r5_i(BUS775),
               .r5_o(BUS1726)
           );
 
 
 
    r5_reg rnd_pass1
           (.hold(hold),
               .clk(clk),
               .r5_i(BUS1726),
               .r5_o(BUS1724)
           );
 
 
 
    r5_reg rnd_pass2
           (.hold(hold),
               .clk(clk),
               .r5_i(BUS1724),
               .r5_o(wb_addr_o)
           );
 
 
 
    r32_reg rs_reg
            (.hold(hold),
                .clk(clk),
                .r32_i(BUS24839),
                .r32_o(BUS7101)
            );
 
 
 
    r32_reg rt_reg
            (.hold(hold),
                .clk(clk),
                .r32_i(BUS7160),
                .r32_o(BUS7117)
            );
 
 
 
    wb_mux wb_mux
           (
               .alu_i(BUS422),
               .dmem_i(BUS7780),
               .sel(NET457),
               .wb_o(wb_din_o)
           );
 
         hazard_unit ihazard_unit
                        (.hold(hold),
                                        .clk(clk),
                                        .rt(rdaddrb_o),
                                        .load(load),
                                        .load_o(load_o),
                                        .rt_o(rt_o)
                        );
 
                        r4_asi_reg reg_asi_pass1
            (    .hold(hold),
                .clk(clk),
                .r4_i(asi_o),
                .r4_o(asi_pass1)
            );
 
                        r4_asi_reg reg_asi_pass2
            (    .hold(hold),
                .clk(clk),
                .r4_i(asi_pass1),
                .r4_o(asi_pass2)
            );
 
                        r4_rdaddr_reg reg_rdaddra
            (    .hold(hold),
                .clk(clk),
                .r4_i(rdaddra1),
                .r4_o(rdaddra_o)
            );
 
                                r4_rdaddr_reg reg_rdaddrb
            (    .hold(hold),
                .clk(clk),
                .r4_i(rdaddrb1),
                .r4_o(rdaddrb_o)
            );
 
 
endmodule

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [vlog/] [core1.v.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`include "mips789_defs.v"
2
3			`module mips_core (`
4			`clk,rst,zz_ins_i,iack_o,qa,qb,wb_din_o,rdaddra_o,rdaddrb_o,wb_addr_o,wb_we_o,`
5			`zz_pc_o,dmem_ctl_ur_o,alu_ur_o,dmem_data_ur_o,dout,size,branch,hold,imds,dmds,asi_pass2, pc_next`
6			`);`
7
8			`input clk;`
9			`wire clk;`
10			`input rst;`
11			`wire rst;`
12			`input [31:0] zz_ins_i;`
13			`wire [31:0] zz_ins_i;`
14			`wire [31:0] zz_ins_o;`
15			`input [31:0] dout;`
16			`wire [31:0] dout;`
17			`input [31:0] qa;`
18			`wire [31:0] qa;`
19			`input [31:0] qb;`
20			`wire [31:0] qb;`
21			`output [31:0] zz_pc_o;`
22			`wire [31:0] zz_pc_o;`
23			`output iack_o;`
24			`wire iack_o;`
25			`wire [31:0] cop_addr_o;`
26			`output [4:0] dmem_ctl_ur_o;`
27			`output [31:0] alu_ur_o;`
28			`output [31:0] dmem_data_ur_o;`
29			`wire [4:0] dmem_ctl_ur_o;`
30			`wire [31:0] alu_ur_o;`
31			`wire [31:0] dmem_data_ur_o;`
32			`output [31:0] wb_din_o;`
33			`wire [31:0] wb_din_o;`
34			`output [4:0] rdaddra_o;`
35			`wire [4:0] rdaddra_o;`
36			`output [4:0] rdaddrb_o;`
37			`wire [4:0] rdaddrb_o;`
38			`output [4:0] wb_addr_o;`
39			`wire [4:0] wb_addr_o;`
40			`output wb_we_o;`
41			`wire wb_we_o;`
42			`output [1:0] size;`
43			`wire [1:0] size;`
44			`output branch;`
45			`wire branch;`
46			`input hold;`
47			`wire hold;`
48			`input imds;`
49			`wire imds;`
50			`input dmds;`
51			`wire dmds;`
52			`output [4:0] asi_pass2;`
53			`output [31:0] pc_next;`
54
55			`wire [31:0] pc_next;`
56			`wire load;`
57			`wire load_o;`
58			`wire [4:0]rt_o;`
59			`wire NET1375;`
60			`wire NET1572;`
61			`wire NET1606;`
62			`wire NET1640;`
63			`wire NET21531;`
64			`wire NET457;`
65			`wire NET767;`
66			`wire [2:0] BUS109;`
67			`wire [2:0] BUS1158;`
68			`wire [2:0] BUS117;`
69			`wire [2:0] BUS1196;`
70			`wire [31:0] BUS15471;`
71			`wire [4:0] BUS1724;`
72			`wire [4:0] BUS1726;`
73			`wire [4:0] BUS18211;`
74			`wire [2:0] BUS197;`
75			`wire [2:0] BUS2140;`
76			`wire [2:0] BUS2156;`
77			`wire [31:0] BUS22401;`
78			`wire [31:0] BUS24839;`
79			`wire [31:0] BUS27031;`
80			`wire [2:0] BUS271;`
81			`wire [31:0] BUS28013;`
82			`wire [1:0] BUS371;`
83			`wire [31:0] BUS422;`
84			`wire [1:0] BUS5832;`
85			`wire [1:0] BUS5840;`
86			`wire [2:0] BUS5993;`
87			`wire [4:0] BUS6275;`
88			`wire [31:0] BUS7101;`
89			`wire [31:0] BUS7117;`
90			`wire [31:0] BUS7160;`
91			`wire [31:0] BUS7219;`
92			`wire [31:0] BUS7231;`
93			`wire [4:0] BUS748;`
94			`wire [4:0] BUS756;`
95			`wire [4:0] BUS775;`
96			`wire [31:0] BUS7772;`
97			`wire [31:0] BUS7780;`
98			`wire [31:0] BUS9884;`
99			`wire [4:0] asi_o;`
100			`wire [4:0] asi_pass1;`
101			`wire [4:0] asi_pass2;`
102			`wire [4:0] rdaddra1;`
103			`wire [4:0] rdaddrb1;`
104
105
106
107			`assign NET21531 = NET1572 \| iack_o;`
108
109			`rf_stage iRF_stage`
110			`( .hold(hold),`
111			`.clk(clk),`
112			`.cmp_ctl_i(BUS109),`
113			`.ext_ctl_i(BUS117),`
114			`.ext_o(BUS7219),`
115			`.fw_alu_i(cop_addr_o),`
116			`.fw_cmp_rs(BUS2140),`
117			`.fw_cmp_rt(BUS2156),`
118			`.fw_mem_i(wb_din_o),`
119			`.iack_o(iack_o),`
120			`.id2ra_ctl_clr_o(NET1606),`
121			`.id2ra_ctl_cls_o(NET1572),`
122			`.id_cmd(BUS197),`
123			`.ins_i(zz_ins_o),`
124			`.pc_gen_ctl(BUS271),`
125			`.branch(branch),`
126			`.pc_i(zz_pc_o),`
127			`.pc_next(pc_next),`
128			`.ra2ex_ctl_clr_o(NET1640),`
129			`.rd_index_o(BUS775),`
130			`.rd_sel_i(BUS371),`
131			`.rs_n_o(BUS748),`
132			`.rs_o(BUS24839),`
133			`.rst_i(rst),`
134			`.rt_n_o(BUS756),`
135			`.rt_o(BUS7160),`
136			`.wb_din_i(wb_din_o),`
137			`.zz_spc_i(BUS28013),`
138			`.rdaddra1(rdaddra1),`
139			`.rdaddrb1(rdaddrb1),`
140			`.qa(qa),`
141			`.qb(qb)`
142			`);`
143
144
145
146			`exec_stage iexec_stage`
147			`(.hold(hold),`
148			`.alu_func(BUS6275),`
149			`.alu_ur_o(alu_ur_o),`
150			`.clk(clk),`
151			`.dmem_data_ur_o(dmem_data_ur_o),`
152			`.dmem_fw_ctl(BUS5993),`
153			`.ext_i(BUS7231),`
154			`.fw_alu(cop_addr_o),`
155			`.fw_dmem(wb_din_o),`
156			`.muxa_ctl_i(BUS5832),`
157			`.muxa_fw_ctl(BUS1158),`
158			`.muxb_ctl_i(BUS5840),`
159			`.muxb_fw_ctl(BUS1196),`
160			`.pc_i(zz_pc_o),`
161			`.rs_i(BUS7101),`
162			`.rst(rst),`
163			`.rt_i(BUS7117),`
164			`.spc_cls_i(NET21531),`
165			`.zz_spc_o(BUS28013)`
166			`);`
167
168
169
170			`r32_reg alu_pass0`
171			`(.hold(hold),`
172			`.clk(clk),`
173			`.r32_i(alu_ur_o),`
174			`.r32_o(cop_addr_o)`
175			`);`
176
177
178
179			`r32_reg alu_pass1`
180			`(.hold(hold),`
181			`.clk(clk),`
182			`.r32_i(cop_addr_o),`
183			`.r32_o(BUS422)`
184			`);`
185
186			`r32_inst_reg instruction`
187			`( .hold(hold),`
188			`.branch(branch),`
189			`.imds(imds),`
190			`.clk(clk),`
191			`.r32_i(zz_ins_i),`
192			`.r32_o(zz_ins_o)`
193			`);`
194
195
196
197			`// or32 cop_data_or`
198			`// (`
199			`// .a(cop_dout),`
200			`// .b(BUS7772),`
201			`// .c(BUS7780)`
202			`// );`
203
204
205
206			`// r32_reg cop_data_reg`
207			`// (`
208			`// .clk(clk),`
209			`// .r32_i(BUS9884),`
210			`// .r32_o(cop_data_o)`
211			`// );`
212
213
214
215			`/* r32_reg cop_dout_reg`
216			`(.hold(hold),`
217			`.clk(clk),`
218			`.r32_i(dout),`
219			`.r32_o(BUS7780)`
220			`);`
221			`*/`
222
223			`r32_data_reg cop_dout_reg`
224			`( .hold(hold),`
225			`.dmds(dmds),`
226			`.clk(clk),`
227			`.r32_i(dout),`
228			`.r32_o(BUS7780)`
229			`);`
230
231
232
233			`decode_pipe decoder_pipe`
234			`(.hold(hold),`
235			`.rt1(rt_o),`
236			`.load(load_o),`
237			`.load_o(load),`
238			`.alu_func_o(BUS6275),`
239			`.size(size),`
240			`.alu_we_o(NET767),`
241			`.clk(clk),`
242			`.cmp_ctl_o(BUS109),`
243			`.dmem_ctl_ur_o(dmem_ctl_ur_o),`
244			`.ext_ctl_o(BUS117),`
245			`.fsm_dly(BUS197),`
246			`.id2ra_ctl_clr(NET1606),`
247			`.id2ra_ctl_cls(NET1572),`
248			`.ins_i(zz_ins_o),`
249			`.muxa_ctl_o(BUS5832),`
250			`.muxb_ctl_o(BUS5840),`
251			`.pc_gen_ctl_o(BUS271),`
252			`.ra2ex_ctl_clr(NET1640),`
253			`.rd_sel_o(BUS371),`
254			`.wb_mux_ctl_o(NET457),`
255			`.wb_we_o(wb_we_o),`
256			`.asi(asi_o)`
257			`);`
258
259
260
261			`r32_reg ext_reg`
262			`(.hold(hold),`
263			`.clk(clk),`
264			`.r32_i(BUS7219),`
265			`.r32_o(BUS7231)`
266			`);`
267
268
269
270			`forward iforward`
271			`(.hold(hold),`
272			`.alu_rs_fw(BUS1158),`
273			`.alu_rt_fw(BUS1196),`
274			`.alu_we(NET767),`
275			`.clk(clk),`
276			`.cmp_rs_fw(BUS2140),`
277			`.cmp_rt_fw(BUS2156),`
278			`.dmem_fw(BUS5993),`
279			`.fw_alu_rn(BUS1724),`
280			`.fw_mem_rn(wb_addr_o),`
281			`.mem_We(wb_we_o),`
282			`.rns_i(BUS748),`
283			`.rnt_i(BUS756)`
284			`);`
285
286
287
288			`r32_reg pc`
289			`(.hold(hold),`
290			`.clk(clk),`
291			`.r32_i(pc_next),`
292			`.r32_o(zz_pc_o)`
293			`);`
294
295
296
297			`r5_reg rnd_pass0`
298			`(.hold(hold),`
299			`.clk(clk),`
300			`.r5_i(BUS775),`
301			`.r5_o(BUS1726)`
302			`);`
303
304
305
306			`r5_reg rnd_pass1`
307			`(.hold(hold),`
308			`.clk(clk),`
309			`.r5_i(BUS1726),`
310			`.r5_o(BUS1724)`
311			`);`
312
313
314
315			`r5_reg rnd_pass2`
316			`(.hold(hold),`
317			`.clk(clk),`
318			`.r5_i(BUS1724),`
319			`.r5_o(wb_addr_o)`
320			`);`
321
322
323
324			`r32_reg rs_reg`
325			`(.hold(hold),`
326			`.clk(clk),`
327			`.r32_i(BUS24839),`
328			`.r32_o(BUS7101)`
329			`);`
330
331
332
333			`r32_reg rt_reg`
334			`(.hold(hold),`
335			`.clk(clk),`
336			`.r32_i(BUS7160),`
337			`.r32_o(BUS7117)`
338			`);`
339
340
341
342			`wb_mux wb_mux`
343			`(`
344			`.alu_i(BUS422),`
345			`.dmem_i(BUS7780),`
346			`.sel(NET457),`
347			`.wb_o(wb_din_o)`
348			`);`
349
350			`hazard_unit ihazard_unit`
351			`(.hold(hold),`
352			`.clk(clk),`
353			`.rt(rdaddrb_o),`
354			`.load(load),`
355			`.load_o(load_o),`
356			`.rt_o(rt_o)`
357			`);`
358
359			`r4_asi_reg reg_asi_pass1`
360			`( .hold(hold),`
361			`.clk(clk),`
362			`.r4_i(asi_o),`
363			`.r4_o(asi_pass1)`
364			`);`
365
366			`r4_asi_reg reg_asi_pass2`
367			`( .hold(hold),`
368			`.clk(clk),`
369			`.r4_i(asi_pass1),`
370			`.r4_o(asi_pass2)`
371			`);`
372
373			`r4_rdaddr_reg reg_rdaddra`
374			`( .hold(hold),`
375			`.clk(clk),`
376			`.r4_i(rdaddra1),`
377			`.r4_o(rdaddra_o)`
378			`);`
379
380			`r4_rdaddr_reg reg_rdaddrb`
381			`( .hold(hold),`
382			`.clk(clk),`
383			`.r4_i(rdaddrb1),`
384			`.r4_o(rdaddrb_o)`
385			`);`
386
387
388			`endmodule`