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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [spw/] [comp/] [spwcomp.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
3 
--  Copyright (C) 2003, Gaisler Research
4 
--
5 
--  This program is free software; you can redistribute it and/or modify
6 
--  it under the terms of the GNU General Public License as published by
7 
--  the Free Software Foundation; either version 2 of the License, or
8 
--  (at your option) any later version.
9 
--
10 
--  This program is distributed in the hope that it will be useful,
11 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
--  GNU General Public License for more details.
14 
--
15 
--  You should have received a copy of the GNU General Public License
16 
--  along with this program; if not, write to the Free Software
17 
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18 
-----------------------------------------------------------------------------
19 
library ieee;
20 
use ieee.std_logic_1164.all;
21 
 
22 
package spwcomp is
23 
  component grspwc2 is
24 
    generic(
25 
      nsync        : integer range 1 to 2  := 1;
26 
      rmap         : integer range 0 to 1  := 0;
27 
      rmapcrc      : integer range 0 to 1  := 0;
28 
      fifosize1    : integer range 4 to 32 := 32;
29 
      fifosize2    : integer range 16 to 64 := 64;
30 
      rxunaligned  : integer range 0 to 1 := 0;
31 
      rmapbufs     : integer range 2 to 8 := 4;
32 
      scantest     : integer range 0 to 1 := 0;
33 
      ports        : integer range 1 to 2 := 1;
34 
      dmachan      : integer range 1 to 4 := 1;
35 
      tech         : integer
36 
    );
37 
    port(
38 
      rst          : in  std_ulogic;
39 
      clk          : in  std_ulogic;
40 
      txclk        : in  std_ulogic;
41 
      --ahb mst in
42 
      hgrant       : in  std_ulogic;
43 
      hready       : in  std_ulogic;
44 
      hresp        : in  std_logic_vector(1 downto 0);
45 
      hrdata       : in  std_logic_vector(31 downto 0);
46 
      --ahb mst out
47 
      hbusreq      : out  std_ulogic;
48 
      hlock        : out  std_ulogic;
49 
      htrans       : out  std_logic_vector(1 downto 0);
50 
      haddr        : out  std_logic_vector(31 downto 0);
51 
      hwrite       : out  std_ulogic;
52 
      hsize        : out  std_logic_vector(2 downto 0);
53 
      hburst       : out  std_logic_vector(2 downto 0);
54 
      hprot        : out  std_logic_vector(3 downto 0);
55 
      hwdata       : out  std_logic_vector(31 downto 0);
56 
      --apb slv in
57 
      psel       : in   std_ulogic;
58 
      penable    : in   std_ulogic;
59 
      paddr      : in   std_logic_vector(31 downto 0);
60 
      pwrite     : in   std_ulogic;
61 
      pwdata     : in   std_logic_vector(31 downto 0);
62 
      --apb slv out
63 
      prdata     : out  std_logic_vector(31 downto 0);
64 
      --spw in
65 
      di           : in   std_logic_vector(1 downto 0);
66 
      si           : in   std_logic_vector(1 downto 0);
67 
      --spw out
68 
      do           : out  std_logic_vector(1 downto 0);
69 
      so           : out  std_logic_vector(1 downto 0);
70 
      --time iface
71 
      tickin       : in   std_ulogic;
72 
      tickout      : out  std_ulogic;
73 
      --irq
74 
      irq          : out  std_logic;
75 
      --misc
76 
      clkdiv10     : in   std_logic_vector(7 downto 0);
77 
      dcrstval     : in   std_logic_vector(9 downto 0);
78 
      timerrstval  : in   std_logic_vector(11 downto 0);
79 
      --rmapen
80 
      rmapen       : in   std_ulogic;
81 
      --clk bufs
82 
      rxclki       : in   std_logic_vector(1 downto 0);
83 
      nrxclki      : in   std_logic_vector(1 downto 0);
84 
      rxclko       : out  std_logic_vector(1 downto 0);
85 
      --rx ahb fifo
86 
      rxrenable    : out  std_ulogic;
87 
      rxraddress   : out  std_logic_vector(4 downto 0);
88 
      rxwrite      : out  std_ulogic;
89 
      rxwdata      : out  std_logic_vector(31 downto 0);
90 
      rxwaddress   : out  std_logic_vector(4 downto 0);
91 
      rxrdata      : in   std_logic_vector(31 downto 0);
92 
      --tx ahb fifo
93 
      txrenable    : out  std_ulogic;
94 
      txraddress   : out  std_logic_vector(4 downto 0);
95 
      txwrite      : out  std_ulogic;
96 
      txwdata      : out  std_logic_vector(31 downto 0);
97 
      txwaddress   : out  std_logic_vector(4 downto 0);
98 
      txrdata      : in   std_logic_vector(31 downto 0);
99 
      --nchar fifo
100 
      ncrenable    : out  std_ulogic;
101 
      ncraddress   : out  std_logic_vector(5 downto 0);
102 
      ncwrite      : out  std_ulogic;
103 
      ncwdata      : out  std_logic_vector(8 downto 0);
104 
      ncwaddress   : out  std_logic_vector(5 downto 0);
105 
      ncrdata      : in   std_logic_vector(8 downto 0);
106 
      --rmap buf
107 
      rmrenable    : out  std_ulogic;
108 
      rmraddress   : out  std_logic_vector(7 downto 0);
109 
      rmwrite      : out  std_ulogic;
110 
      rmwdata      : out  std_logic_vector(7 downto 0);
111 
      rmwaddress   : out  std_logic_vector(7 downto 0);
112 
      rmrdata      : in   std_logic_vector(7 downto 0);
113 
      linkdis      : out  std_ulogic;
114 
      testclk      : in   std_ulogic := '0';
115 
      testrst      : in   std_ulogic := '0';
116 
      testen       : in   std_ulogic := '0'
117 
    );
118 
  end component;
119 
 
120 
  component grspwc is
121 
    generic(
122 
      sysfreq      : integer := 40000;
123 
      usegen       : integer range 0 to 1  := 1;
124 
      nsync        : integer range 1 to 2  := 1;
125 
      rmap         : integer range 0 to 1  := 0;
126 
      rmapcrc      : integer range 0 to 1  := 0;
127 
      fifosize1    : integer range 4 to 32 := 32;
128 
      fifosize2    : integer range 16 to 64 := 64;
129 
      rxunaligned  : integer range 0 to 1 := 0;
130 
      rmapbufs     : integer range 2 to 8 := 4;
131 
      scantest     : integer range 0 to 1 := 0;
132 
      ports        : integer range 1 to 2 := 1;
133 
      tech         : integer
134 
    );
135 
    port(
136 
      rst          : in  std_ulogic;
137 
      clk          : in  std_ulogic;
138 
      txclk        : in  std_ulogic;
139 
      --ahb mst in
140 
      hgrant       : in  std_ulogic;
141 
      hready       : in  std_ulogic;
142 
      hresp        : in  std_logic_vector(1 downto 0);
143 
      hrdata       : in  std_logic_vector(31 downto 0);
144 
      --ahb mst out
145 
      hbusreq      : out  std_ulogic;
146 
      hlock        : out  std_ulogic;
147 
      htrans       : out  std_logic_vector(1 downto 0);
148 
      haddr        : out  std_logic_vector(31 downto 0);
149 
      hwrite       : out  std_ulogic;
150 
      hsize        : out  std_logic_vector(2 downto 0);
151 
      hburst       : out  std_logic_vector(2 downto 0);
152 
      hprot        : out  std_logic_vector(3 downto 0);
153 
      hwdata       : out  std_logic_vector(31 downto 0);
154 
      --apb slv in
155 
      psel       : in   std_ulogic;
156 
      penable    : in   std_ulogic;
157 
      paddr      : in   std_logic_vector(31 downto 0);
158 
      pwrite     : in   std_ulogic;
159 
      pwdata     : in   std_logic_vector(31 downto 0);
160 
      --apb slv out
161 
      prdata     : out  std_logic_vector(31 downto 0);
162 
      --spw in
163 
      di           : in   std_logic_vector(1 downto 0);
164 
      si           : in   std_logic_vector(1 downto 0);
165 
      --spw out
166 
      do           : out  std_logic_vector(1 downto 0);
167 
      so           : out  std_logic_vector(1 downto 0);
168 
      --time iface
169 
      tickin       : in   std_ulogic;
170 
      tickout      : out  std_ulogic;
171 
      --irq
172 
      irq          : out  std_logic;
173 
      --misc
174 
      clkdiv10     : in   std_logic_vector(7 downto 0);
175 
      dcrstval     : in   std_logic_vector(9 downto 0);
176 
      timerrstval  : in   std_logic_vector(11 downto 0);
177 
      --rmapen
178 
      rmapen       : in   std_ulogic;
179 
      --clk bufs
180 
      rxclki       : in   std_logic_vector(1 downto 0);
181 
      nrxclki      : in   std_logic_vector(1 downto 0);
182 
      rxclko       : out  std_logic_vector(1 downto 0);
183 
      --rx ahb fifo
184 
      rxrenable    : out  std_ulogic;
185 
      rxraddress   : out  std_logic_vector(4 downto 0);
186 
      rxwrite      : out  std_ulogic;
187 
      rxwdata      : out  std_logic_vector(31 downto 0);
188 
      rxwaddress   : out  std_logic_vector(4 downto 0);
189 
      rxrdata      : in   std_logic_vector(31 downto 0);
190 
      --tx ahb fifo
191 
      txrenable    : out  std_ulogic;
192 
      txraddress   : out  std_logic_vector(4 downto 0);
193 
      txwrite      : out  std_ulogic;
194 
      txwdata      : out  std_logic_vector(31 downto 0);
195 
      txwaddress   : out  std_logic_vector(4 downto 0);
196 
      txrdata      : in   std_logic_vector(31 downto 0);
197 
      --nchar fifo
198 
      ncrenable    : out  std_ulogic;
199 
      ncraddress   : out  std_logic_vector(5 downto 0);
200 
      ncwrite      : out  std_ulogic;
201 
      ncwdata      : out  std_logic_vector(8 downto 0);
202 
      ncwaddress   : out  std_logic_vector(5 downto 0);
203 
      ncrdata      : in   std_logic_vector(8 downto 0);
204 
      --rmap buf
205 
      rmrenable    : out  std_ulogic;
206 
      rmraddress   : out  std_logic_vector(7 downto 0);
207 
      rmwrite      : out  std_ulogic;
208 
      rmwdata      : out  std_logic_vector(7 downto 0);
209 
      rmwaddress   : out  std_logic_vector(7 downto 0);
210 
      rmrdata      : in   std_logic_vector(7 downto 0);
211 
      linkdis      : out  std_ulogic;
212 
      testclk      : in   std_ulogic := '0';
213 
      testrst      : in   std_ulogic := '0';
214 
      testen       : in   std_ulogic := '0'
215 
    );
216 
  end component;
217 
 
218 
  component grspwc_axcelerator is
219 
    port(
220 
      rst          : in  std_ulogic;
221 
      clk          : in  std_ulogic;
222 
      txclk        : in  std_ulogic;
223 
      --ahb mst in
224 
      hgrant       : in  std_ulogic;
225 
      hready       : in  std_ulogic;
226 
      hresp        : in  std_logic_vector(1 downto 0);
227 
      hrdata       : in  std_logic_vector(31 downto 0);
228 
      --ahb mst out
229 
      hbusreq      : out  std_ulogic;
230 
      hlock        : out  std_ulogic;
231 
      htrans       : out  std_logic_vector(1 downto 0);
232 
      haddr        : out  std_logic_vector(31 downto 0);
233 
      hwrite       : out  std_ulogic;
234 
      hsize        : out  std_logic_vector(2 downto 0);
235 
      hburst       : out  std_logic_vector(2 downto 0);
236 
      hprot        : out  std_logic_vector(3 downto 0);
237 
      hwdata       : out  std_logic_vector(31 downto 0);
238 
      --apb slv in
239 
      psel         : in   std_ulogic;
240 
      penable      : in   std_ulogic;
241 
      paddr        : in   std_logic_vector(31 downto 0);
242 
      pwrite       : in   std_ulogic;
243 
      pwdata       : in   std_logic_vector(31 downto 0);
244 
      --apb slv out
245 
      prdata       : out  std_logic_vector(31 downto 0);
246 
      --spw in
247 
      di           : in   std_logic_vector(1 downto 0);
248 
      si           : in   std_logic_vector(1 downto 0);
249 
      --spw out
250 
      do           : out  std_logic_vector(1 downto 0);
251 
      so           : out  std_logic_vector(1 downto 0);
252 
      --time iface
253 
      tickin       : in   std_ulogic;
254 
      tickout      : out  std_ulogic;
255 
      --irq
256 
      irq          : out  std_logic;
257 
      --misc
258 
      clkdiv10     : in   std_logic_vector(7 downto 0);
259 
      dcrstval     : in   std_logic_vector(9 downto 0);
260 
      timerrstval  : in   std_logic_vector(11 downto 0);
261 
      --rmapen
262 
      rmapen       : in   std_ulogic;
263 
      --clk bufs
264 
      rxclki       : in   std_logic_vector(1 downto 0);
265 
      nrxclki      : in   std_logic_vector(1 downto 0);
266 
      rxclko       : out  std_logic_vector(1 downto 0);
267 
      --rx ahb fifo
268 
      rxrenable    : out  std_ulogic;
269 
      rxraddress   : out  std_logic_vector(4 downto 0);
270 
      rxwrite      : out  std_ulogic;
271 
      rxwdata      : out  std_logic_vector(31 downto 0);
272 
      rxwaddress   : out  std_logic_vector(4 downto 0);
273 
      rxrdata      : in   std_logic_vector(31 downto 0);
274 
      --tx ahb fifo
275 
      txrenable    : out  std_ulogic;
276 
      txraddress   : out  std_logic_vector(4 downto 0);
277 
      txwrite      : out  std_ulogic;
278 
      txwdata      : out  std_logic_vector(31 downto 0);
279 
      txwaddress   : out  std_logic_vector(4 downto 0);
280 
      txrdata      : in   std_logic_vector(31 downto 0);
281 
      --nchar fifo
282 
      ncrenable    : out  std_ulogic;
283 
      ncraddress   : out  std_logic_vector(5 downto 0);
284 
      ncwrite      : out  std_ulogic;
285 
      ncwdata      : out  std_logic_vector(8 downto 0);
286 
      ncwaddress   : out  std_logic_vector(5 downto 0);
287 
      ncrdata      : in   std_logic_vector(8 downto 0);
288 
      --rmap buf
289 
      rmrenable    : out  std_ulogic;
290 
      rmraddress   : out  std_logic_vector(7 downto 0);
291 
      rmwrite      : out  std_ulogic;
292 
      rmwdata      : out  std_logic_vector(7 downto 0);
293 
      rmwaddress   : out  std_logic_vector(7 downto 0);
294 
      rmrdata      : in   std_logic_vector(7 downto 0);
295 
      linkdis      : out  std_ulogic;
296 
      testclk      : in   std_ulogic := '0';
297 
      testrst      : in   std_ulogic := '0';
298 
      testen       : in   std_ulogic := '0'
299 
    );
300 
  end component;
301 
 
302 
  component grspwc_unisim is
303 
    port(
304 
      rst          : in  std_ulogic;
305 
      clk          : in  std_ulogic;
306 
      txclk        : in  std_ulogic;
307 
      --ahb mst in
308 
      hgrant       : in  std_ulogic;
309 
      hready       : in  std_ulogic;
310 
      hresp        : in  std_logic_vector(1 downto 0);
311 
      hrdata       : in  std_logic_vector(31 downto 0);
312 
      --ahb mst out
313 
      hbusreq      : out  std_ulogic;
314 
      hlock        : out  std_ulogic;
315 
      htrans       : out  std_logic_vector(1 downto 0);
316 
      haddr        : out  std_logic_vector(31 downto 0);
317 
      hwrite       : out  std_ulogic;
318 
      hsize        : out  std_logic_vector(2 downto 0);
319 
      hburst       : out  std_logic_vector(2 downto 0);
320 
      hprot        : out  std_logic_vector(3 downto 0);
321 
      hwdata       : out  std_logic_vector(31 downto 0);
322 
      --apb slv in
323 
      psel         : in   std_ulogic;
324 
      penable      : in   std_ulogic;
325 
      paddr        : in   std_logic_vector(31 downto 0);
326 
      pwrite       : in   std_ulogic;
327 
      pwdata       : in   std_logic_vector(31 downto 0);
328 
      --apb slv out
329 
      prdata       : out  std_logic_vector(31 downto 0);
330 
      --spw in
331 
      di           : in   std_logic_vector(1 downto 0);
332 
      si           : in   std_logic_vector(1 downto 0);
333 
      --spw out
334 
      do           : out  std_logic_vector(1 downto 0);
335 
      so           : out  std_logic_vector(1 downto 0);
336 
      --time iface
337 
      tickin       : in   std_ulogic;
338 
      tickout      : out  std_ulogic;
339 
      --irq
340 
      irq          : out  std_logic;
341 
      --misc
342 
      clkdiv10     : in   std_logic_vector(7 downto 0);
343 
      dcrstval     : in   std_logic_vector(9 downto 0);
344 
      timerrstval  : in   std_logic_vector(11 downto 0);
345 
      --rmapen
346 
      rmapen       : in   std_ulogic;
347 
      --clk bufs
348 
      rxclki       : in   std_logic_vector(1 downto 0);
349 
      nrxclki      : in   std_logic_vector(1 downto 0);
350 
      rxclko       : out  std_logic_vector(1 downto 0);
351 
      --rx ahb fifo
352 
      rxrenable    : out  std_ulogic;
353 
      rxraddress   : out  std_logic_vector(4 downto 0);
354 
      rxwrite      : out  std_ulogic;
355 
      rxwdata      : out  std_logic_vector(31 downto 0);
356 
      rxwaddress   : out  std_logic_vector(4 downto 0);
357 
      rxrdata      : in   std_logic_vector(31 downto 0);
358 
      --tx ahb fifo
359 
      txrenable    : out  std_ulogic;
360 
      txraddress   : out  std_logic_vector(4 downto 0);
361 
      txwrite      : out  std_ulogic;
362 
      txwdata      : out  std_logic_vector(31 downto 0);
363 
      txwaddress   : out  std_logic_vector(4 downto 0);
364 
      txrdata      : in   std_logic_vector(31 downto 0);
365 
      --nchar fifo
366 
      ncrenable    : out  std_ulogic;
367 
      ncraddress   : out  std_logic_vector(5 downto 0);
368 
      ncwrite      : out  std_ulogic;
369 
      ncwdata      : out  std_logic_vector(8 downto 0);
370 
      ncwaddress   : out  std_logic_vector(5 downto 0);
371 
      ncrdata      : in   std_logic_vector(8 downto 0);
372 
      --rmap buf
373 
      rmrenable    : out  std_ulogic;
374 
      rmraddress   : out  std_logic_vector(7 downto 0);
375 
      rmwrite      : out  std_ulogic;
376 
      rmwdata      : out  std_logic_vector(7 downto 0);
377 
      rmwaddress   : out  std_logic_vector(7 downto 0);
378 
      rmrdata      : in   std_logic_vector(7 downto 0);
379 
      linkdis      : out  std_ulogic;
380 
      testclk      : in   std_ulogic := '0';
381 
      testrst      : in   std_ulogic := '0';
382 
      testen       : in   std_ulogic := '0'
383 
    );
384 
  end component;
385 
 
386 
  component grspw_gen is
387 
    generic(
388 
      tech         : integer := 0;
389 
      sysfreq      : integer := 10000;
390 
      usegen       : integer range 0 to 1  := 1;
391 
      nsync        : integer range 1 to 2  := 1;
392 
      rmap         : integer range 0 to 1  := 0;
393 
      rmapcrc      : integer range 0 to 1  := 0;
394 
      fifosize1    : integer range 4 to 32 := 32;
395 
      fifosize2    : integer range 16 to 64 := 64;
396 
      rxclkbuftype : integer range 0 to 2 := 0;
397 
      rxunaligned  : integer range 0 to 1 := 0;
398 
      rmapbufs     : integer range 2 to 8 := 4;
399 
      ft           : integer range 0 to 2 := 0;
400 
      scantest     : integer range 0 to 1 := 0;
401 
      techfifo     : integer range 0 to 1 := 1;
402 
      ports        : integer range 1 to 2 := 1;
403 
      memtech      : integer := 0
404 
    );
405 
    port(
406 
      rst          : in  std_ulogic;
407 
      clk          : in  std_ulogic;
408 
      txclk        : in  std_ulogic;
409 
      --ahb mst in
410 
      hgrant       : in  std_ulogic;
411 
      hready       : in  std_ulogic;
412 
      hresp        : in  std_logic_vector(1 downto 0);
413 
      hrdata       : in  std_logic_vector(31 downto 0);
414 
      --ahb mst out
415 
      hbusreq      : out  std_ulogic;
416 
      hlock        : out  std_ulogic;
417 
      htrans       : out  std_logic_vector(1 downto 0);
418 
      haddr        : out  std_logic_vector(31 downto 0);
419 
      hwrite       : out  std_ulogic;
420 
      hsize        : out  std_logic_vector(2 downto 0);
421 
      hburst       : out  std_logic_vector(2 downto 0);
422 
      hprot        : out  std_logic_vector(3 downto 0);
423 
      hwdata       : out  std_logic_vector(31 downto 0);
424 
      --apb slv in
425 
      psel       : in   std_ulogic;
426 
      penable    : in   std_ulogic;
427 
      paddr      : in   std_logic_vector(31 downto 0);
428 
      pwrite     : in   std_ulogic;
429 
      pwdata     : in   std_logic_vector(31 downto 0);
430 
      --apb slv out
431 
      prdata     : out  std_logic_vector(31 downto 0);
432 
      --spw in
433 
      di           : in   std_logic_vector(1 downto 0);
434 
      si           : in   std_logic_vector(1 downto 0);
435 
      --spw out
436 
      do           : out  std_logic_vector(1 downto 0);
437 
      so           : out  std_logic_vector(1 downto 0);
438 
      --time iface
439 
      tickin       : in   std_ulogic;
440 
      tickout      : out  std_ulogic;
441 
      --irq
442 
      irq          : out  std_logic;
443 
      --misc
444 
      clkdiv10     : in   std_logic_vector(7 downto 0);
445 
      dcrstval     : in   std_logic_vector(9 downto 0);
446 
      timerrstval  : in   std_logic_vector(11 downto 0);
447 
      --rmapen
448 
      rmapen       : in   std_ulogic;
449 
      linkdis      : out  std_ulogic;
450 
      testclk      : in   std_ulogic := '0';
451 
      testrst      : in   std_ulogic := '0';
452 
      testen       : in   std_ulogic := '0'
453 
      );
454 
  end component;
455 
 
456 
end package;

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