OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [tech/] [proasic3/] [components/] [proasic3.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali 
------------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
3 
--  Copyright (C) 2003, Gaisler Research
4 
--
5 
--  This program is free software; you can redistribute it and/or modify
6 
--  it under the terms of the GNU General Public License as published by
7 
--  the Free Software Foundation; either version 2 of the License, or
8 
--  (at your option) any later version.
9 
--
10 
--  This program is distributed in the hope that it will be useful,
11 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
--  GNU General Public License for more details.
14 
--
15 
--  You should have received a copy of the GNU General Public License
16 
--  along with this program; if not, write to the Free Software
17 
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18 
-----------------------------------------------------------------------------
19 
-- Package:     components
20 
-- File:        components.vhd
21 
-- Author:      Jiri Gaisler, Gaisler Research
22 
-- Description: Actel proasic3 RAM component declarations
23 
-----------------------------------------------------------------------------
24 
 
25 
library ieee;
26 
use ieee.std_logic_1164.all;
27 
use IEEE.VITAL_Timing.all;
28 
 
29 
package components is
30 
 
31 
-- Proasic3 rams
32 
 
33 
  component RAM4K9
34 
    generic (abits : integer range 9 to 12 := 9);
35 
    port(
36 
        ADDRA0, ADDRA1, ADDRA2, ADDRA3, ADDRA4, ADDRA5, ADDRA6, ADDRA7,
37 
        ADDRA8, ADDRA9, ADDRA10, ADDRA11 : in std_logic;
38 
        ADDRB0, ADDRB1, ADDRB2, ADDRB3, ADDRB4, ADDRB5, ADDRB6, ADDRB7,
39 
        ADDRB8, ADDRB9, ADDRB10, ADDRB11 : in std_logic;
40 
        BLKA, WENA, PIPEA, WMODEA, WIDTHA0, WIDTHA1, WENB, BLKB,
41 
        PIPEB, WMODEB, WIDTHB1, WIDTHB0 : in std_logic;
42 
        DINA0, DINA1, DINA2, DINA3, DINA4, DINA5, DINA6, DINA7, DINA8 : in std_logic;
43 
        DINB0, DINB1, DINB2, DINB3, DINB4, DINB5, DINB6, DINB7, DINB8 : in std_logic;
44 
        RESET, CLKA, CLKB : in std_logic;
45 
        DOUTA0, DOUTA1, DOUTA2, DOUTA3, DOUTA4, DOUTA5, DOUTA6, DOUTA7, DOUTA8 : out std_logic;
46 
        DOUTB0, DOUTB1, DOUTB2, DOUTB3, DOUTB4, DOUTB5, DOUTB6, DOUTB7, DOUTB8 : out std_logic
47 
    );
48 
  end component;
49 
 
50 
  component RAM512X18
51 
    port(
52 
      RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
53 
      WADDR8, WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
54 
      WD17, WD16, WD15, WD14, WD13, WD12, WD11, WD10, WD9,
55 
      WD8, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0 : in std_logic;
56 
      REN, WEN, RESET, RW0, RW1, WW1, WW0, PIPE, RCLK, WCLK : in std_logic;
57 
      RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
58 
      RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic
59 
    );
60 
  end component;
61 
 
62 
  component PLL
63 
  generic(
64 
     VCOFREQUENCY      :  Real    := 0.0;
65 
     f_CLKA_LOCK       :  Integer := 3; -- Number of CLKA pulses after which LOCK is raised
66 
 
67 
     TimingChecksOn    :  Boolean          := True;
68 
     InstancePath      :  String           := "*";
69 
     Xon               :  Boolean          := False;
70 
     MsgOn             :  Boolean          := True;
71 
 
72 
     tipd_CLKA         :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
73 
     tipd_EXTFB        :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
74 
     tipd_POWERDOWN    :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
75 
     tipd_OADIV0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
76 
     tipd_OADIV1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
77 
     tipd_OADIV2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
78 
     tipd_OADIV3       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
79 
     tipd_OADIV4       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
80 
     tipd_OAMUX0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
81 
     tipd_OAMUX1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
82 
     tipd_OAMUX2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
83 
     tipd_DLYGLA0      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
84 
     tipd_DLYGLA1      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
85 
     tipd_DLYGLA2      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
86 
     tipd_DLYGLA3      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
87 
     tipd_DLYGLA4      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
88 
     tipd_OBDIV0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
89 
     tipd_OBDIV1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
90 
     tipd_OBDIV2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
91 
     tipd_OBDIV3       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
92 
     tipd_OBDIV4       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
93 
     tipd_OBMUX0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
94 
     tipd_OBMUX1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
95 
     tipd_OBMUX2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
96 
     tipd_DLYYB0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
97 
     tipd_DLYYB1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
98 
     tipd_DLYYB2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
99 
     tipd_DLYYB3       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
100 
     tipd_DLYYB4       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
101 
     tipd_DLYGLB0      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
102 
     tipd_DLYGLB1      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
103 
     tipd_DLYGLB2      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
104 
     tipd_DLYGLB3      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
105 
     tipd_DLYGLB4      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
106 
     tipd_OCDIV0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
107 
     tipd_OCDIV1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
108 
     tipd_OCDIV2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
109 
     tipd_OCDIV3       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
110 
     tipd_OCDIV4       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
111 
     tipd_OCMUX0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
112 
     tipd_OCMUX1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
113 
     tipd_OCMUX2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
114 
     tipd_DLYYC0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
115 
     tipd_DLYYC1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
116 
     tipd_DLYYC2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
117 
     tipd_DLYYC3       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
118 
     tipd_DLYYC4       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
119 
     tipd_DLYGLC0      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
120 
     tipd_DLYGLC1      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
121 
     tipd_DLYGLC2      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
122 
     tipd_DLYGLC3      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
123 
     tipd_DLYGLC4      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
124 
     tipd_FINDIV0      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
125 
     tipd_FINDIV1      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
126 
     tipd_FINDIV2      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
127 
     tipd_FINDIV3      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
128 
     tipd_FINDIV4      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
129 
     tipd_FINDIV5      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
130 
     tipd_FINDIV6      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
131 
     tipd_FBDIV0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
132 
     tipd_FBDIV1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
133 
     tipd_FBDIV2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
134 
     tipd_FBDIV3       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
135 
     tipd_FBDIV4       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
136 
     tipd_FBDIV5       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
137 
     tipd_FBDIV6       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
138 
     tipd_FBDLY0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
139 
     tipd_FBDLY1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
140 
     tipd_FBDLY2       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
141 
     tipd_FBDLY3       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
142 
     tipd_FBDLY4       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
143 
     tipd_FBSEL0       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
144 
     tipd_FBSEL1       :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
145 
     tipd_XDLYSEL      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
146 
     tipd_VCOSEL0      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
147 
     tipd_VCOSEL1      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
148 
     tipd_VCOSEL2      :  VitalDelayType01 := ( 0.000 ns,0.000 ns );
149 
 
150 
     tpd_CLKA_GLA      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
151 
     tpd_EXTFB_GLA     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
152 
     tpd_POWERDOWN_GLA :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
153 
     tpd_CLKA_GLB      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
154 
     tpd_EXTFB_GLB     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
155 
     tpd_POWERDOWN_GLB :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
156 
     tpd_CLKA_GLC      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
157 
     tpd_EXTFB_GLC     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
158 
     tpd_POWERDOWN_GLC :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
159 
     tpd_CLKA_YB       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
160 
     tpd_EXTFB_YB      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
161 
     tpd_POWERDOWN_YB  :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
162 
     tpd_CLKA_YC       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
163 
     tpd_EXTFB_YC      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
164 
     tpd_POWERDOWN_YC  :  VitalDelayType01 := ( 0.100 ns, 0.100 ns);
165 
     tpd_CLKA_LOCK     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns));
166 
 
167 
 
168 
  port (
169 
     CLKA         :  in    STD_ULOGIC;
170 
     EXTFB        :  in    STD_ULOGIC;
171 
     POWERDOWN    :  in    STD_ULOGIC;
172 
     OADIV0       :  in    STD_ULOGIC;
173 
     OADIV1       :  in    STD_ULOGIC;
174 
     OADIV2       :  in    STD_ULOGIC;
175 
     OADIV3       :  in    STD_ULOGIC;
176 
     OADIV4       :  in    STD_ULOGIC;
177 
     OAMUX0       :  in    STD_ULOGIC;
178 
     OAMUX1       :  in    STD_ULOGIC;
179 
     OAMUX2       :  in    STD_ULOGIC;
180 
     DLYGLA0      :  in    STD_ULOGIC;
181 
     DLYGLA1      :  in    STD_ULOGIC;
182 
     DLYGLA2      :  in    STD_ULOGIC;
183 
     DLYGLA3      :  in    STD_ULOGIC;
184 
     DLYGLA4      :  in    STD_ULOGIC;
185 
     OBDIV0       :  in    STD_ULOGIC;
186 
     OBDIV1       :  in    STD_ULOGIC;
187 
     OBDIV2       :  in    STD_ULOGIC;
188 
     OBDIV3       :  in    STD_ULOGIC;
189 
     OBDIV4       :  in    STD_ULOGIC;
190 
     OBMUX0       :  in    STD_ULOGIC;
191 
     OBMUX1       :  in    STD_ULOGIC;
192 
     OBMUX2       :  in    STD_ULOGIC;
193 
     DLYYB0       :  in    STD_ULOGIC;
194 
     DLYYB1       :  in    STD_ULOGIC;
195 
     DLYYB2       :  in    STD_ULOGIC;
196 
     DLYYB3       :  in    STD_ULOGIC;
197 
     DLYYB4       :  in    STD_ULOGIC;
198 
     DLYGLB0      :  in    STD_ULOGIC;
199 
     DLYGLB1      :  in    STD_ULOGIC;
200 
     DLYGLB2      :  in    STD_ULOGIC;
201 
     DLYGLB3      :  in    STD_ULOGIC;
202 
     DLYGLB4      :  in    STD_ULOGIC;
203 
     OCDIV0       :  in    STD_ULOGIC;
204 
     OCDIV1       :  in    STD_ULOGIC;
205 
     OCDIV2       :  in    STD_ULOGIC;
206 
     OCDIV3       :  in    STD_ULOGIC;
207 
     OCDIV4       :  in    STD_ULOGIC;
208 
     OCMUX0       :  in    STD_ULOGIC;
209 
     OCMUX1       :  in    STD_ULOGIC;
210 
     OCMUX2       :  in    STD_ULOGIC;
211 
     DLYYC0       :  in    STD_ULOGIC;
212 
     DLYYC1       :  in    STD_ULOGIC;
213 
     DLYYC2       :  in    STD_ULOGIC;
214 
     DLYYC3       :  in    STD_ULOGIC;
215 
     DLYYC4       :  in    STD_ULOGIC;
216 
     DLYGLC0      :  in    STD_ULOGIC;
217 
     DLYGLC1      :  in    STD_ULOGIC;
218 
     DLYGLC2      :  in    STD_ULOGIC;
219 
     DLYGLC3      :  in    STD_ULOGIC;
220 
     DLYGLC4      :  in    STD_ULOGIC;
221 
     FINDIV0      :  in    STD_ULOGIC;
222 
     FINDIV1      :  in    STD_ULOGIC;
223 
     FINDIV2      :  in    STD_ULOGIC;
224 
     FINDIV3      :  in    STD_ULOGIC;
225 
     FINDIV4      :  in    STD_ULOGIC;
226 
     FINDIV5      :  in    STD_ULOGIC;
227 
     FINDIV6      :  in    STD_ULOGIC;
228 
     FBDIV0       :  in    STD_ULOGIC;
229 
     FBDIV1       :  in    STD_ULOGIC;
230 
     FBDIV2       :  in    STD_ULOGIC;
231 
     FBDIV3       :  in    STD_ULOGIC;
232 
     FBDIV4       :  in    STD_ULOGIC;
233 
     FBDIV5       :  in    STD_ULOGIC;
234 
     FBDIV6       :  in    STD_ULOGIC;
235 
     FBDLY0       :  in    STD_ULOGIC;
236 
     FBDLY1       :  in    STD_ULOGIC;
237 
     FBDLY2       :  in    STD_ULOGIC;
238 
     FBDLY3       :  in    STD_ULOGIC;
239 
     FBDLY4       :  in    STD_ULOGIC;
240 
     FBSEL0       :  in    STD_ULOGIC;
241 
     FBSEL1       :  in    STD_ULOGIC;
242 
     XDLYSEL      :  in    STD_ULOGIC;
243 
     VCOSEL0      :  in    STD_ULOGIC;
244 
     VCOSEL1      :  in    STD_ULOGIC;
245 
     VCOSEL2      :  in    STD_ULOGIC;
246 
     GLA          :  out   STD_ULOGIC;
247 
     LOCK         :  out   STD_ULOGIC;
248 
     GLB          :  out   STD_ULOGIC;
249 
     YB           :  out   STD_ULOGIC;
250 
     GLC          :  out   STD_ULOGIC;
251 
     YC           :  out   STD_ULOGIC);
252 
  end component;
253 
 
254 
  component CLKBUF port(Y : out std_logic; PAD : in std_logic); end component;
255 
  component CLKBUF_LVCMOS18 port(Y : out std_logic; PAD : in std_logic); end component;
256 
  component CLKBUF_LVCMOS25 port(Y : out std_logic; PAD : in std_logic); end component;
257 
  component CLKBUF_LVCMOS33 port(Y : out std_logic; PAD : in std_logic); end component;
258 
  component CLKBUF_LVCMOS5 port(Y : out std_logic; PAD : in std_logic); end component;
259 
  component CLKBUF_PCI port(Y : out std_logic; PAD : in std_logic); end component;
260 
  component CLKINT port( A : in std_logic; Y :out std_logic); end component;
261 
  component PLLINT port( A : in std_logic; Y :out std_logic); end component;
262 
 
263 
 component UJTAG
264 
   port(
265 
      UTDO           :  in    STD_ULOGIC;
266 
      TMS            :  in    STD_ULOGIC;
267 
      TDI            :  in    STD_ULOGIC;
268 
      TCK            :  in    STD_ULOGIC;
269 
      TRSTB          :  in    STD_ULOGIC;
270 
      UIREG0         :  out   STD_ULOGIC;
271 
      UIREG1         :  out   STD_ULOGIC;
272 
      UIREG2         :  out   STD_ULOGIC;
273 
      UIREG3         :  out   STD_ULOGIC;
274 
      UIREG4         :  out   STD_ULOGIC;
275 
      UIREG5         :  out   STD_ULOGIC;
276 
      UIREG6         :  out   STD_ULOGIC;
277 
      UIREG7         :  out   STD_ULOGIC;
278 
      UTDI           :  out   STD_ULOGIC;
279 
      URSTB          :  out   STD_ULOGIC;
280 
      UDRCK          :  out   STD_ULOGIC;
281 
      UDRCAP         :  out   STD_ULOGIC;
282 
      UDRSH          :  out   STD_ULOGIC;
283 
      UDRUPD         :  out   STD_ULOGIC;
284 
      TDO            :  out   STD_ULOGIC);
285 
 end component;
286 
 
287 
end;
288 
 
289 
library ieee;
290 
use ieee.std_logic_1164.all;
291 
entity PLLINT is port(Y : out std_logic; A : in std_logic); end;
292 
architecture rtl of PLLINT is begin Y <= A; end;
293 
 
294 
library ieee;
295 
use ieee.std_logic_1164.all;
296 
entity CLKINT is port(Y : out std_logic; A : in std_logic); end;
297 
architecture rtl of CLKINT is begin Y <= A; end;
298 
 
299 
library ieee;
300 
use ieee.std_logic_1164.all;
301 
entity CLKBUF is port(Y : out std_logic; PAD : in std_logic); end;
302 
architecture rtl of CLKBUF is begin Y <= PAD; end;
303 
 
304 
library ieee;
305 
use ieee.std_logic_1164.all;
306 
entity CLKBUF_PCI is port(Y : out std_logic; PAD : in std_logic); end;
307 
architecture rtl of CLKBUF_PCI is begin Y <= PAD; end;
308 
 
309 
library ieee;
310 
use ieee.std_logic_1164.all;
311 
use ieee.numeric_std.all;
312 
 
313 
entity RAM4K9 is generic (abits : integer range 9 to 12 := 9);
314 
    port(
315 
        ADDRA0, ADDRA1, ADDRA2, ADDRA3, ADDRA4, ADDRA5, ADDRA6, ADDRA7,
316 
        ADDRA8, ADDRA9, ADDRA10, ADDRA11 : in std_logic;
317 
        ADDRB0, ADDRB1, ADDRB2, ADDRB3, ADDRB4, ADDRB5, ADDRB6, ADDRB7,
318 
        ADDRB8, ADDRB9, ADDRB10, ADDRB11 : in std_logic;
319 
        BLKA, WENA, PIPEA, WMODEA, WIDTHA0, WIDTHA1, WENB, BLKB,
320 
        PIPEB, WMODEB, WIDTHB1, WIDTHB0 : in std_logic;
321 
        DINA0, DINA1, DINA2, DINA3, DINA4, DINA5, DINA6, DINA7, DINA8 : in std_logic;
322 
        DINB0, DINB1, DINB2, DINB3, DINB4, DINB5, DINB6, DINB7, DINB8 : in std_logic;
323 
        RESET, CLKA, CLKB : in std_logic;
324 
        DOUTA0, DOUTA1, DOUTA2, DOUTA3, DOUTA4, DOUTA5, DOUTA6, DOUTA7, DOUTA8 : out std_logic;
325 
        DOUTB0, DOUTB1, DOUTB2, DOUTB3, DOUTB4, DOUTB5, DOUTB6, DOUTB7, DOUTB8 : out std_logic
326 
    );
327 
end ;
328 
 
329 
architecture sim of RAM4K9 is
330 
  type dwarrtype is array (9 to 12) of integer;
331 
  constant dwarr : dwarrtype := (9, 4, 2, 1);
332 
  constant dwidth : integer := dwarr(abits);
333 
  subtype memword is std_logic_vector(dwidth-1 downto 0);
334 
  type memtype is array (0 to 2**abits-1) of memword;
335 
begin
336 
  p1 : process(CLKA, CLKB, RESET)
337 
  variable mem : memtype;
338 
  variable ra, rb : std_logic_vector(11 downto 0);
339 
  variable da, db : std_logic_vector(8 downto 0);
340 
  variable qa, qb : std_logic_vector(8 downto 0);
341 
  variable qal, qbl : std_logic_vector(8 downto 0);
342 
  variable qao, qbo : std_logic_vector(8 downto 0);
343 
  begin
344 
   if rising_edge(CLKA) then
345 
     ra := ADDRA11 & ADDRA10 & ADDRA9 & ADDRA8 & ADDRA7 & ADDRA6 & ADDRA5 &
346 
        ADDRA4 & ADDRA3 & ADDRA2 & ADDRA1 & ADDRA0;
347 
     da := DINA8 & DINA7 & DINA6 & DINA5 & DINA4 & DINA3 & DINA2 &
348 
        DINA1 & DINA0;
349 
      if BLKA = '0' then
350 
        if not (is_x (ra(abits-1 downto 0))) then
351 
          qa(dwidth-1 downto 0) := mem(to_integer(unsigned(ra(abits-1 downto 0))));
352 
        else qa := (others => 'X'); end if;
353 
        if WENA = '0' and not (is_x (ra(abits-1 downto 0))) then
354 
          mem(to_integer(unsigned(ra(abits-1 downto 0)))) := da(dwidth-1 downto 0);
355 
          if WMODEA = '1' then qa := da(dwidth-1 downto 0); end if;
356 
        end if;
357 
      elsif is_x(BLKA) then qa := (others => 'X'); end if;
358 
      if PIPEA = '1' then qao := qal; else qao := qa; end if;
359 
      qal := qa;
360 
   end if;
361 
   if reset = '0' then qao := (others => '0'); end if;
362 
   (DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2,
363 
        DOUTA1, DOUTA0) <= qao;
364 
   if rising_edge(CLKB) then
365 
     rb := ADDRB11 & ADDRB10 & ADDRB9 & ADDRB8 & ADDRB7 & ADDRB6 & ADDRB5 &
366 
        ADDRB4 & ADDRB3 & ADDRB2 & ADDRB1 & ADDRB0;
367 
     db := DINB8 & DINB7 & DINB6 & DINB5 & DINB4 & DINB3 & DINB2 &
368 
        DINB1 & DINB0;
369 
      if BLKB = '0' then
370 
        if not (is_x (rb(abits-1 downto 0))) then
371 
          qb(dwidth-1 downto 0) := mem(to_integer(unsigned(rb(abits-1 downto 0))));
372 
        else qb := (others => 'X'); end if;
373 
        if WENB = '0' and not (is_x (rb(abits-1 downto 0))) then
374 
          mem(to_integer(unsigned(rb(abits-1 downto 0)))) := db(dwidth-1 downto 0);
375 
          if WMODEB = '1' then qb := db(dwidth-1 downto 0); end if;
376 
        end if;
377 
      elsif is_x(BLKB) then qb := (others => 'X'); end if;
378 
      if PIPEB = '1' then qbo := qbl; else qbo := qb; end if;
379 
      qbl := qb;
380 
   end if;
381 
   if reset = '0' then qbo := (others => '0'); end if;
382 
   (DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2,
383 
        DOUTB1, DOUTB0) <= qbo;
384 
  end process;
385 
end;
386 
 
387 
library ieee;
388 
use ieee.std_logic_1164.all;
389 
use ieee.numeric_std.all;
390 
 
391 
entity RAM512X18 is
392 
    port(
393 
      RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
394 
      WADDR8, WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
395 
      WD17, WD16, WD15, WD14, WD13, WD12, WD11, WD10, WD9,
396 
      WD8, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0 : in std_logic;
397 
      REN, WEN, RESET, RW0, RW1, WW1, WW0, PIPE, RCLK, WCLK : in std_logic;
398 
      RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
399 
      RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic
400 
    );
401 
end ;
402 
 
403 
architecture sim of RAM512X18 is
404 
  constant abits : integer := 8;
405 
  constant dwidth : integer := 18;
406 
  subtype memword is std_logic_vector(dwidth-1 downto 0);
407 
  type memtype is array (0 to 2**abits-1) of memword;
408 
begin
409 
  p1 : process(RCLK, WCLK, RESET)
410 
  variable mem : memtype;
411 
  variable ra, rb  : std_logic_vector(8 downto 0);
412 
  variable da  : std_logic_vector(17 downto 0);
413 
  variable qb  : std_logic_vector(17 downto 0);
414 
  variable qbl : std_logic_vector(17 downto 0);
415 
  variable qbo : std_logic_vector(17 downto 0);
416 
  begin
417 
   if rising_edge(WCLK) then
418 
     ra :=  '0' & WADDR7 & WADDR6 & WADDR5 &
419 
        WADDR4 & WADDR3 & WADDR2 & WADDR1 & WADDR0;
420 
     da := WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 &
421 
        Wd10 & WD9 & WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 &
422 
        WD1 & WD0;
423 
     if WEN = '0' and not (is_x (ra(abits-1 downto 0))) then
424 
       mem(to_integer(unsigned(ra(abits-1 downto 0)))) := da(dwidth-1 downto 0);
425 
     end if;
426 
   end if;
427 
   if rising_edge(RCLK) then
428 
     rb :=  '0' & RADDR7 & RADDR6 & RADDR5 &
429 
        RADDR4 & RADDR3 & RADDR2 & RADDR1 & RADDR0;
430 
      if REN = '0' then
431 
        if not (is_x (rb(abits-1 downto 0))) then
432 
          qb := mem(to_integer(unsigned(rb(abits-1 downto 0))));
433 
        else qb := (others => 'X'); end if;
434 
      elsif is_x(REN) then qb := (others => 'X'); end if;
435 
      if PIPE = '1' then qbo := qbl; else qbo := qb; end if;
436 
      qbl := qb;
437 
   end if;
438 
   if RESET = '0' then qbo := (others => '0'); end if;
439 
   (RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
440 
      RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0) <= qbo;
441 
  end process;
442 
end;
443 
 
444 
library IEEE;
445 
use IEEE.std_logic_1164.all;
446 
library IEEE;
447 
use IEEE.VITAL_Timing.all;
448 
 
449 
-- entity declaration --
450 
entity PLLPRIM is
451 
  generic (
452 
    VCOFREQUENCY       :  Real    := 0.0;
453 
    f_CLKA_LOCK        :  Integer := 3; -- Number of CLKA pulses after which LOCK is raised
454 
 
455 
    TimingChecksOn     :  Boolean          := True;
456 
    InstancePath       :  String           := "*";
457 
    Xon                :  Boolean          := False;
458 
    MsgOn              :  Boolean          := True;
459 
    EMULATED_SYSTEM_DELAY :  Time          := 2.290 ns; -- Delay Tap Additional CLK delay
460 
    IN_DIV_DELAY       :  Time             := 0.335 ns; -- Input Divider intrinsic delay
461 
    OUT_DIV_DELAY      :  Time             := 0.770 ns; -- Output Divider intrinsic delay
462 
    MUX_DELAY          :  Time             := 1.200 ns; -- MUXA/MUXB/MUXC intrinsic delay
463 
    IN_DELAY_BYP1      :  Time             := 1.523 ns; -- Input delay for CLKDIVDLY bypass mode
464 
    BYP_MUX_DELAY      :  Time             := 0.040 ns; -- Bypass MUX intrinsic delay, not used for Ys
465 
    GL_DRVR_DELAY      :  Time             := 0.060 ns; -- Global Driver intrinsic delay
466 
    Y_DRVR_DELAY       :  Time             := 0.285 ns; -- Y Driver intrinsic delay
467 
    FB_MUX_DELAY       :  Time             := 0.145 ns; -- FBSEL MUX intrinsic delay
468 
    X_MUX_DELAY        :  Time             := 0.625 ns; -- XDLYSEL MUX intrinsic delay
469 
    FIN_LOCK_DELAY     :  Time             := 0.300 ns; -- FIN to LOCK propagation delay
470 
    LOCK_OUT_DELAY     :  Time             := 0.120 ns; -- LOCK to OUT propagation delay
471 
    PROG_INIT_DELAY     : Time             := 0.535 ns;
472 
    PROG_STEP_INCREMENT : Time             := 0.200 ns;
473 
    BYP0_CLK_GL         : Time             := 0.200 ns; -- Intrinsic delay for CLKDLY bypass mode
474 
    CLKA_TO_REF_DELAY  : Time              := 0.395 ns;
475 
 
476 
    tipd_DYNSYNC       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
477 
    tipd_CLKA          :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
478 
    tipd_EXTFB         :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
479 
    tipd_POWERDOWN     :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
480 
    tipd_CLKB          :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
481 
    tipd_CLKC          :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
482 
    tipd_OADIVRST      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
483 
    tipd_OADIVHALF     :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
484 
    tipd_OADIV0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
485 
    tipd_OADIV1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
486 
    tipd_OADIV2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
487 
    tipd_OADIV3        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
488 
    tipd_OADIV4        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
489 
    tipd_OAMUX0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
490 
    tipd_OAMUX1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
491 
    tipd_OAMUX2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
492 
    tipd_DLYGLA0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
493 
    tipd_DLYGLA1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
494 
    tipd_DLYGLA2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
495 
    tipd_DLYGLA3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
496 
    tipd_DLYGLA4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
497 
    tipd_OBDIVRST      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
498 
    tipd_OBDIVHALF     :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
499 
    tipd_OBDIV0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
500 
    tipd_OBDIV1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
501 
    tipd_OBDIV2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
502 
    tipd_OBDIV3        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
503 
    tipd_OBDIV4        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
504 
    tipd_OBMUX0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
505 
    tipd_OBMUX1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
506 
    tipd_OBMUX2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
507 
    tipd_DLYYB0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
508 
    tipd_DLYYB1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
509 
    tipd_DLYYB2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
510 
    tipd_DLYYB3        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
511 
    tipd_DLYYB4        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
512 
    tipd_DLYGLB0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
513 
    tipd_DLYGLB1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
514 
    tipd_DLYGLB2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
515 
    tipd_DLYGLB3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
516 
    tipd_DLYGLB4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
517 
    tipd_OCDIVRST      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
518 
    tipd_OCDIVHALF     :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
519 
    tipd_OCDIV0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
520 
    tipd_OCDIV1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
521 
    tipd_OCDIV2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
522 
    tipd_OCDIV3        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
523 
    tipd_OCDIV4        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
524 
    tipd_OCMUX0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
525 
    tipd_OCMUX1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
526 
    tipd_OCMUX2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
527 
    tipd_DLYYC0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
528 
    tipd_DLYYC1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
529 
    tipd_DLYYC2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
530 
    tipd_DLYYC3        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
531 
    tipd_DLYYC4        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
532 
    tipd_DLYGLC0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
533 
    tipd_DLYGLC1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
534 
    tipd_DLYGLC2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
535 
    tipd_DLYGLC3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
536 
    tipd_DLYGLC4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
537 
    tipd_FINDIV0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
538 
    tipd_FINDIV1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
539 
    tipd_FINDIV2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
540 
    tipd_FINDIV3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
541 
    tipd_FINDIV4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
542 
    tipd_FINDIV5       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
543 
    tipd_FINDIV6       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
544 
    tipd_FBDIV0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
545 
    tipd_FBDIV1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
546 
    tipd_FBDIV2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
547 
    tipd_FBDIV3        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
548 
    tipd_FBDIV4        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
549 
    tipd_FBDIV5        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
550 
    tipd_FBDIV6        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
551 
    tipd_FBDLY0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
552 
    tipd_FBDLY1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
553 
    tipd_FBDLY2        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
554 
    tipd_FBDLY3        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
555 
    tipd_FBDLY4        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
556 
    tipd_FBSEL0        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
557 
    tipd_FBSEL1        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
558 
    tipd_XDLYSEL       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
559 
    tipd_VCOSEL0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
560 
    tipd_VCOSEL1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
561 
    tipd_VCOSEL2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
562 
 
563 
    tpd_CLKA_GLA       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
564 
    tpd_EXTFB_GLA      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
565 
    tpd_POWERDOWN_GLA  :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
566 
    tpd_CLKA_GLB       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
567 
    tpd_EXTFB_GLB      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
568 
    tpd_POWERDOWN_GLB  :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
569 
    tpd_CLKA_GLC       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
570 
    tpd_EXTFB_GLC      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
571 
    tpd_POWERDOWN_GLC  :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
572 
    tpd_CLKA_YB        :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
573 
    tpd_EXTFB_YB       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
574 
    tpd_POWERDOWN_YB   :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
575 
    tpd_CLKA_YC        :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
576 
    tpd_EXTFB_YC       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
577 
    tpd_POWERDOWN_YC   :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
578 
    tpd_CLKA_LOCK      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
579 
    tpd_EXTFB_LOCK     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
580 
    tpd_POWERDOWN_LOCK :  VitalDelayType01 := ( 0.100 ns, 0.100 ns )
581 
   );
582 
 
583 
  port (
584 
    DYNSYNC      : in    std_ulogic;
585 
    CLKA         : in    std_ulogic;
586 
    EXTFB        : in    std_ulogic;
587 
    POWERDOWN    : in    std_ulogic;
588 
    CLKB         : in    std_ulogic;
589 
    CLKC         : in    std_ulogic;
590 
    OADIVRST     : in    std_ulogic;
591 
    OADIVHALF    : in    std_ulogic;
592 
    OADIV0       : in    std_ulogic;
593 
    OADIV1       : in    std_ulogic;
594 
    OADIV2       : in    std_ulogic;
595 
    OADIV3       : in    std_ulogic;
596 
    OADIV4       : in    std_ulogic;
597 
    OAMUX0       : in    std_ulogic;
598 
    OAMUX1       : in    std_ulogic;
599 
    OAMUX2       : in    std_ulogic;
600 
    DLYGLA0      : in    std_ulogic;
601 
    DLYGLA1      : in    std_ulogic;
602 
    DLYGLA2      : in    std_ulogic;
603 
    DLYGLA3      : in    std_ulogic;
604 
    DLYGLA4      : in    std_ulogic;
605 
    OBDIVRST     : in    std_ulogic;
606 
    OBDIVHALF    : in    std_ulogic;
607 
    OBDIV0       : in    std_ulogic;
608 
    OBDIV1       : in    std_ulogic;
609 
    OBDIV2       : in    std_ulogic;
610 
    OBDIV3       : in    std_ulogic;
611 
    OBDIV4       : in    std_ulogic;
612 
    OBMUX0       : in    std_ulogic;
613 
    OBMUX1       : in    std_ulogic;
614 
    OBMUX2       : in    std_ulogic;
615 
    DLYYB0       : in    std_ulogic;
616 
    DLYYB1       : in    std_ulogic;
617 
    DLYYB2       : in    std_ulogic;
618 
    DLYYB3       : in    std_ulogic;
619 
    DLYYB4       : in    std_ulogic;
620 
    DLYGLB0      : in    std_ulogic;
621 
    DLYGLB1      : in    std_ulogic;
622 
    DLYGLB2      : in    std_ulogic;
623 
    DLYGLB3      : in    std_ulogic;
624 
    DLYGLB4      : in    std_ulogic;
625 
    OCDIVRST     : in    std_ulogic;
626 
    OCDIVHALF    : in    std_ulogic;
627 
    OCDIV0       : in    std_ulogic;
628 
    OCDIV1       : in    std_ulogic;
629 
    OCDIV2       : in    std_ulogic;
630 
    OCDIV3       : in    std_ulogic;
631 
    OCDIV4       : in    std_ulogic;
632 
    OCMUX0       : in    std_ulogic;
633 
    OCMUX1       : in    std_ulogic;
634 
    OCMUX2       : in    std_ulogic;
635 
    DLYYC0       : in    std_ulogic;
636 
    DLYYC1       : in    std_ulogic;
637 
    DLYYC2       : in    std_ulogic;
638 
    DLYYC3       : in    std_ulogic;
639 
    DLYYC4       : in    std_ulogic;
640 
    DLYGLC0      : in    std_ulogic;
641 
    DLYGLC1      : in    std_ulogic;
642 
    DLYGLC2      : in    std_ulogic;
643 
    DLYGLC3      : in    std_ulogic;
644 
    DLYGLC4      : in    std_ulogic;
645 
    FINDIV0      : in    std_ulogic;
646 
    FINDIV1      : in    std_ulogic;
647 
    FINDIV2      : in    std_ulogic;
648 
    FINDIV3      : in    std_ulogic;
649 
    FINDIV4      : in    std_ulogic;
650 
    FINDIV5      : in    std_ulogic;
651 
    FINDIV6      : in    std_ulogic;
652 
    FBDIV0       : in    std_ulogic;
653 
    FBDIV1       : in    std_ulogic;
654 
    FBDIV2       : in    std_ulogic;
655 
    FBDIV3       : in    std_ulogic;
656 
    FBDIV4       : in    std_ulogic;
657 
    FBDIV5       : in    std_ulogic;
658 
    FBDIV6       : in    std_ulogic;
659 
    FBDLY0       : in    std_ulogic;
660 
    FBDLY1       : in    std_ulogic;
661 
    FBDLY2       : in    std_ulogic;
662 
    FBDLY3       : in    std_ulogic;
663 
    FBDLY4       : in    std_ulogic;
664 
    FBSEL0       : in    std_ulogic;
665 
    FBSEL1       : in    std_ulogic;
666 
    XDLYSEL      : in    std_ulogic;
667 
    VCOSEL0      : in    std_ulogic;
668 
    VCOSEL1      : in    std_ulogic;
669 
    VCOSEL2      : in    std_ulogic;
670 
    GLA          : out   std_ulogic;
671 
    LOCK         : out   std_ulogic;
672 
    GLB          : out   std_ulogic;
673 
    YB           : out   std_ulogic;
674 
    GLC          : out   std_ulogic;
675 
    YC           : out   std_ulogic
676 
   );
677 
 
678 
  attribute VITAL_LEVEL0 of PLLPRIM : entity is TRUE;
679 
end PLLPRIM;
680 
 
681 
-- architecture body --
682 
library IEEE;
683 
use IEEE.VITAL_Primitives.all;
684 
architecture VITAL_ACT of PLLPRIM is
685 
attribute VITAL_LEVEL1 of VITAL_ACT : architecture is FALSE;
686 
 
687 
  signal DYNSYNC_ipd            : std_ulogic;
688 
  signal CLKA_ipd               : std_ulogic;
689 
  signal EXTFB_ipd              : std_ulogic;
690 
  signal POWERDOWN_ipd          : std_ulogic;
691 
  signal CLKB_ipd               : std_ulogic;
692 
  signal CLKC_ipd               : std_ulogic;
693 
  signal OADIVRST_ipd           : std_ulogic;
694 
  signal OADIVHALF_ipd          : std_ulogic;
695 
  signal OADIV0_ipd             : std_ulogic;
696 
  signal OADIV1_ipd             : std_ulogic;
697 
  signal OADIV2_ipd             : std_ulogic;
698 
  signal OADIV3_ipd             : std_ulogic;
699 
  signal OADIV4_ipd             : std_ulogic;
700 
  signal OAMUX0_ipd             : std_ulogic;
701 
  signal OAMUX1_ipd             : std_ulogic;
702 
  signal OAMUX2_ipd             : std_ulogic;
703 
  signal DLYGLA0_ipd            : std_ulogic;
704 
  signal DLYGLA1_ipd            : std_ulogic;
705 
  signal DLYGLA2_ipd            : std_ulogic;
706 
  signal DLYGLA3_ipd            : std_ulogic;
707 
  signal DLYGLA4_ipd            : std_ulogic;
708 
  signal OBDIVRST_ipd           : std_ulogic;
709 
  signal OBDIVHALF_ipd          : std_ulogic;
710 
  signal OBDIV0_ipd             : std_ulogic;
711 
  signal OBDIV1_ipd             : std_ulogic;
712 
  signal OBDIV2_ipd             : std_ulogic;
713 
  signal OBDIV3_ipd             : std_ulogic;
714 
  signal OBDIV4_ipd             : std_ulogic;
715 
  signal OBMUX0_ipd             : std_ulogic;
716 
  signal OBMUX1_ipd             : std_ulogic;
717 
  signal OBMUX2_ipd             : std_ulogic;
718 
  signal DLYYB0_ipd             : std_ulogic;
719 
  signal DLYYB1_ipd             : std_ulogic;
720 
  signal DLYYB2_ipd             : std_ulogic;
721 
  signal DLYYB3_ipd             : std_ulogic;
722 
  signal DLYYB4_ipd             : std_ulogic;
723 
  signal DLYGLB0_ipd            : std_ulogic;
724 
  signal DLYGLB1_ipd            : std_ulogic;
725 
  signal DLYGLB2_ipd            : std_ulogic;
726 
  signal DLYGLB3_ipd            : std_ulogic;
727 
  signal DLYGLB4_ipd            : std_ulogic;
728 
  signal OCDIVRST_ipd           : std_ulogic;
729 
  signal OCDIVHALF_ipd          : std_ulogic;
730 
  signal OCDIV0_ipd             : std_ulogic;
731 
  signal OCDIV1_ipd             : std_ulogic;
732 
  signal OCDIV2_ipd             : std_ulogic;
733 
  signal OCDIV3_ipd             : std_ulogic;
734 
  signal OCDIV4_ipd             : std_ulogic;
735 
  signal OCMUX0_ipd             : std_ulogic;
736 
  signal OCMUX1_ipd             : std_ulogic;
737 
  signal OCMUX2_ipd             : std_ulogic;
738 
  signal DLYYC0_ipd             : std_ulogic;
739 
  signal DLYYC1_ipd             : std_ulogic;
740 
  signal DLYYC2_ipd             : std_ulogic;
741 
  signal DLYYC3_ipd             : std_ulogic;
742 
  signal DLYYC4_ipd             : std_ulogic;
743 
  signal DLYGLC0_ipd            : std_ulogic;
744 
  signal DLYGLC1_ipd            : std_ulogic;
745 
  signal DLYGLC2_ipd            : std_ulogic;
746 
  signal DLYGLC3_ipd            : std_ulogic;
747 
  signal DLYGLC4_ipd            : std_ulogic;
748 
  signal FINDIV0_ipd            : std_ulogic;
749 
  signal FINDIV1_ipd            : std_ulogic;
750 
  signal FINDIV2_ipd            : std_ulogic;
751 
  signal FINDIV3_ipd            : std_ulogic;
752 
  signal FINDIV4_ipd            : std_ulogic;
753 
  signal FINDIV5_ipd            : std_ulogic;
754 
  signal FINDIV6_ipd            : std_ulogic;
755 
  signal FBDIV0_ipd             : std_ulogic;
756 
  signal FBDIV1_ipd             : std_ulogic;
757 
  signal FBDIV2_ipd             : std_ulogic;
758 
  signal FBDIV3_ipd             : std_ulogic;
759 
  signal FBDIV4_ipd             : std_ulogic;
760 
  signal FBDIV5_ipd             : std_ulogic;
761 
  signal FBDIV6_ipd             : std_ulogic;
762 
  signal FBDLY0_ipd             : std_ulogic;
763 
  signal FBDLY1_ipd             : std_ulogic;
764 
  signal FBDLY2_ipd             : std_ulogic;
765 
  signal FBDLY3_ipd             : std_ulogic;
766 
  signal FBDLY4_ipd             : std_ulogic;
767 
  signal FBSEL0_ipd             : std_ulogic;
768 
  signal FBSEL1_ipd             : std_ulogic;
769 
  signal XDLYSEL_ipd            : std_ulogic;
770 
  signal VCOSEL0_ipd            : std_ulogic;
771 
  signal VCOSEL1_ipd            : std_ulogic;
772 
  signal VCOSEL2_ipd            : std_ulogic;
773 
 
774 
  signal AOUT                   : std_logic := 'X';
775 
  signal BOUT                   : std_logic := 'X';
776 
  signal COUT                   : std_logic := 'X';
777 
 
778 
  signal PLLCLK                 : std_logic := 'X';      -- PLL Core Output Clock
779 
                                                         -- with DIVN and DIVM applied
780 
  signal CLKA_period            : Time      := 0.000 ns; -- Current CLKA period
781 
 
782 
  signal PLLCLK_pw              : Time      := 10.0 ns; -- PLLCLK pulse width
783 
  signal PLLCLK_period          : Time      := 10.0 ns;
784 
 
785 
  signal DIVN                   : Integer := 1; -- Divide by N divisor - range 1 to 128
786 
  signal DIVM                   : Integer := 1; -- Multiply by M multiplier - range 1 to 128
787 
  signal DIVU                   : Integer := 1; -- Divide by U divisor - range 1 to 32
788 
  signal DIVV                   : Integer := 1; -- Divide by V divisor - range 1 to 32
789 
  signal DIVW                   : Integer := 1; -- Divide by W divisor - range 1 to 32
790 
  signal fb_loop_div            : Integer := 1; -- Total division of feedback loop
791 
 
792 
  signal halveA                 : std_logic := 'X';
793 
  signal halveB                 : std_logic := 'X';
794 
  signal halveC                 : std_logic := 'X';
795 
 
796 
  signal CLKA2X                 : std_logic := 'X';
797 
  signal CLKB2X                 : std_logic := 'X';
798 
  signal CLKC2X                 : std_logic := 'X';
799 
 
800 
  signal UIN                    : std_logic := 'X'; -- Output of MUXA
801 
  signal VIN                    : std_logic := 'X'; -- Output of MUXB
802 
  signal WIN                    : std_logic := 'X'; -- Output of MUXC
803 
 
804 
  signal FBDELAY                : Time := 0.000 ns; -- Feedback delay
805 
  signal DTDELAY                : Time := 0.000 ns; -- Delay Tap delay
806 
  signal PLLDELAY               : Time := 0.000 ns; -- Sum of Feedback and Delay Tap delays
807 
  signal YBDELAY                : Time := 0.000 ns; -- Additional Global B Delay
808 
  signal GLBDELAY               : Time := 0.000 ns; -- Additional Global B Delay
809 
  signal YCDELAY                : Time := 0.000 ns; -- Additional Global C Delay
810 
  signal GLCDELAY               : Time := 0.000 ns; -- Additional Global C Delay
811 
  signal GLADELAY               : Time := 0.000 ns; -- Additional Global A Delay
812 
 
813 
  signal FBSEL                  : std_logic_vector( 1 downto 0 ) := "XX";
814 
  signal FBSEL_illegal          : Boolean := False; -- True when FBSEL = 00
815 
 
816 
  signal OAMUX_config           : integer := -1;
817 
  signal OBMUX_config           : integer := -1;
818 
  signal OCMUX_config           : integer := -1;
819 
 
820 
  signal internal_lock          : boolean   := false;
821 
  signal fin_period             : Time      := 0.000 ns;
822 
  signal extfbin_fin_drift      : time      := 0 ps;
823 
  signal locked                 : std_logic := '0'; -- 1 when PLL is externally locked as well as internally locked
824 
  signal locked_vco0_edges      : integer   := -1;
825 
  signal vco0_divu              : std_logic := '0';
826 
  signal vco0_divv              : std_logic := '0';
827 
  signal vco0_divw              : std_logic := '0';
828 
  signal fin                    : std_logic := '0';
829 
  signal CLKA_period_stable     : boolean   := false;
830 
 
831 
  signal using_EXTFB            : std_logic := 'X';
832 
  signal EXTFB_delay_dtrmd      : Boolean   := false;
833 
  signal calibrate_EXTFB_delay  : std_logic := '0';
834 
  signal GLA_free_running       : std_logic := '1';
835 
  signal AOUT_using_EXTFB       : std_logic := '1';
836 
  signal GLA_pw                 : time      := 10.0 ns; -- Only used for external feedback
837 
  signal GLA_EXTFB_rise_dly     : time      := 0.0 ns;  -- Only meaningful for external feedback
838 
  signal GLA_EXTFB_fall_dly     : time      := 0.0 ns;  -- Only meaningful for external feedback
839 
  signal EXTFB_period           : time      := 20.0 ns;  -- Only meaningful for external feedback
840 
  signal expected_EXTFB         : std_logic := 'X';
841 
  signal external_dly_correct   : std_logic := 'X';
842 
 
843 
  signal gla_muxed_delay        : time      := 0.000 ns;
844 
  signal glb_muxed_delay        : time      := 0.000 ns;
845 
  signal glc_muxed_delay        : time      := 0.000 ns;
846 
 
847 
  signal internal_fb_delay      : time      := 0.000 ns;
848 
  signal external_fb_delay      : time      := 0.000 ns;
849 
  signal normalized_fb_delay    : time      := 0.000 ns; -- Sum of all delays in the feedback loop from VCO to FBIN normalized to be less than or equal to fin period so that no negative delay assignments are made.
850 
 
851 
  signal CLKA_2_GLA_dly         : time      := 0.000 ns;
852 
  signal CLKA_2_GLA_bypass0_dly : time      := 0.000 ns;
853 
  signal CLKA_2_GLA_bypass1_dly : time      := 0.000 ns;
854 
  signal CLKA_2_GLB_dly         : time      := 0.000 ns;
855 
  signal CLKB_2_GLB_bypass0_dly : time      := 0.000 ns;
856 
  signal CLKB_2_GLB_bypass1_dly : time      := 0.000 ns;
857 
  signal CLKA_2_YB_dly          : time      := 0.000 ns;
858 
  signal CLKB_2_YB_bypass1_dly  : time      := 0.000 ns;
859 
  signal CLKA_2_GLC_dly         : time      := 0.000 ns;
860 
  signal CLKC_2_GLC_bypass0_dly : time      := 0.000 ns;
861 
  signal CLKC_2_GLC_bypass1_dly : time      := 0.000 ns;
862 
  signal CLKA_2_YC_dly          : time      := 0.000 ns;
863 
  signal CLKC_2_YC_bypass1_dly  : time      := 0.000 ns;
864 
  signal CLKA_2_LOCK_dly        : time      := 0.000 ns;
865 
 
866 
 
867 
  -- Use this instead of CONV_INTEGER to avoid ambiguous warnings
868 
  function ulogic2int(
869 
    vec  : std_ulogic_vector )
870 
    return integer is
871 
    variable result : integer;
872 
    variable i : integer;
873 
  begin
874 
    result := 0;
875 
    for i in vec'range loop
876 
      result := result * 2;
877 
      if vec(i) = '1' then
878 
        result := result + 1;
879 
      end if;
880 
    end loop;
881 
    return result;
882 
  end function ulogic2int;
883 
 
884 
  function output_mux_delay(
885 
    outmux      : integer;
886 
    vcobit2     : std_logic;
887 
    vcobit1     : std_logic;
888 
    fbdly_delay : time;
889 
    vco_pw      : time )
890 
    return time is
891 
    variable result : time;
892 
  begin
893 
     case outmux is
894 
        when 1  => result := IN_DELAY_BYP1;
895 
        when 2  => result := MUX_DELAY + fbdly_delay;
896 
        when 5  => if ( ( vcobit2 = '1') and ( vcobit1 = '1') ) then
897 
                         result := MUX_DELAY + ( vco_pw / 2.0 );
898 
                       else
899 
                         result := MUX_DELAY + ( vco_pw * 1.5 );
900 
                       end if;
901 
        when 6  => result := MUX_DELAY + vco_pw;
902 
        when 7  => if ( ( vcobit2 = '1') and ( vcobit1 = '1') ) then
903 
                         result := MUX_DELAY + ( vco_pw * 1.5 );
904 
                       else
905 
                         result := MUX_DELAY + ( vco_pw / 2.0 );
906 
                       end if;
907 
        when others => result := MUX_DELAY;
908 
     end case;
909 
     return result;
910 
  end function output_mux_delay;
911 
 
912 
 
913 
  function output_mux_driver(
914 
    outmux      : integer;
915 
    halved      : std_logic;
916 
    bypass      : std_logic;
917 
    bypass2x    : std_logic;
918 
    vco         : std_logic )
919 
    return std_logic is
920 
    variable result : std_logic;
921 
  begin
922 
     case outmux is
923 
        when 1  => if ( '1' = halved ) then
924 
                          result := bypass2x;
925 
                       elsif ( '0' = halved ) then
926 
                          result := bypass;
927 
                       else
928 
                          result := 'X';
929 
                       end if;
930 
        when 2  => result := vco;
931 
        when 4  => result := vco;
932 
        when 5  => result := vco;
933 
        when 6  => result := vco;
934 
        when 7  => result := vco;
935 
        when others => result := 'X';
936 
     end case;
937 
     return result;
938 
  end function output_mux_driver;
939 
 
940 
  begin
941 
 
942 
    ---------------------
943 
    --  INPUT PATH DELAYs
944 
    ---------------------
945 
    WireDelay : block
946 
 
947 
    begin
948 
 
949 
      VitalWireDelay ( DYNSYNC_ipd,   DYNSYNC,   tipd_DYNSYNC   );
950 
      VitalWireDelay ( CLKA_ipd,      CLKA,      tipd_CLKA      );
951 
      VitalWireDelay ( EXTFB_ipd,     EXTFB,     tipd_EXTFB     );
952 
      VitalWireDelay ( POWERDOWN_ipd, POWERDOWN, tipd_POWERDOWN );
953 
      VitalWireDelay ( CLKB_ipd,      CLKB,      tipd_CLKB      );
954 
      VitalWireDelay ( CLKC_ipd,      CLKC,      tipd_CLKC      );
955 
      VitalWireDelay ( OADIVRST_ipd,  OADIVRST,  tipd_OADIVRST  );
956 
      VitalWireDelay ( OADIVHALF_ipd, OADIVHALF, tipd_OADIVHALF );
957 
      VitalWireDelay ( OADIV0_ipd,    OADIV0,    tipd_OADIV0    );
958 
      VitalWireDelay ( OADIV1_ipd,    OADIV1,    tipd_OADIV1    );
959 
      VitalWireDelay ( OADIV2_ipd,    OADIV2,    tipd_OADIV2    );
960 
      VitalWireDelay ( OADIV3_ipd,    OADIV3,    tipd_OADIV3    );
961 
      VitalWireDelay ( OADIV4_ipd,    OADIV4,    tipd_OADIV4    );
962 
      VitalWireDelay ( OAMUX0_ipd,    OAMUX0,    tipd_OAMUX0    );
963 
      VitalWireDelay ( OAMUX1_ipd,    OAMUX1,    tipd_OAMUX1    );
964 
      VitalWireDelay ( OAMUX2_ipd,    OAMUX2,    tipd_OAMUX2    );
965 
      VitalWireDelay ( DLYGLA0_ipd,   DLYGLA0,   tipd_DLYGLA0   );
966 
      VitalWireDelay ( DLYGLA1_ipd,   DLYGLA1,   tipd_DLYGLA1   );
967 
      VitalWireDelay ( DLYGLA2_ipd,   DLYGLA2,   tipd_DLYGLA2   );
968 
      VitalWireDelay ( DLYGLA3_ipd,   DLYGLA3,   tipd_DLYGLA3   );
969 
      VitalWireDelay ( DLYGLA4_ipd,   DLYGLA4,   tipd_DLYGLA4   );
970 
      VitalWireDelay ( OBDIVRST_ipd,  OBDIVRST,  tipd_OBDIVRST  );
971 
      VitalWireDelay ( OBDIVHALF_ipd, OBDIVHALF, tipd_OBDIVHALF );
972 
      VitalWireDelay ( OBDIV0_ipd,    OBDIV0,    tipd_OBDIV0    );
973 
      VitalWireDelay ( OBDIV1_ipd,    OBDIV1,    tipd_OBDIV1    );
974 
      VitalWireDelay ( OBDIV2_ipd,    OBDIV2,    tipd_OBDIV2    );
975 
      VitalWireDelay ( OBDIV3_ipd,    OBDIV3,    tipd_OBDIV3    );
976 
      VitalWireDelay ( OBDIV4_ipd,    OBDIV4,    tipd_OBDIV4    );
977 
      VitalWireDelay ( OBMUX0_ipd,    OBMUX0,    tipd_OBMUX0    );
978 
      VitalWireDelay ( OBMUX1_ipd,    OBMUX1,    tipd_OBMUX1    );
979 
      VitalWireDelay ( OBMUX2_ipd,    OBMUX2,    tipd_OBMUX2    );
980 
      VitalWireDelay ( DLYYB0_ipd,    DLYYB0,    tipd_DLYYB0    );
981 
      VitalWireDelay ( DLYYB1_ipd,    DLYYB1,    tipd_DLYYB1    );
982 
      VitalWireDelay ( DLYYB2_ipd,    DLYYB2,    tipd_DLYYB2    );
983 
      VitalWireDelay ( DLYYB3_ipd,    DLYYB3,    tipd_DLYYB3    );
984 
      VitalWireDelay ( DLYYB4_ipd,    DLYYB4,    tipd_DLYYB4    );
985 
      VitalWireDelay ( DLYGLB0_ipd,   DLYGLB0,   tipd_DLYGLB0   );
986 
      VitalWireDelay ( DLYGLB1_ipd,   DLYGLB1,   tipd_DLYGLB1   );
987 
      VitalWireDelay ( DLYGLB2_ipd,   DLYGLB2,   tipd_DLYGLB2   );
988 
      VitalWireDelay ( DLYGLB3_ipd,   DLYGLB3,   tipd_DLYGLB3   );
989 
      VitalWireDelay ( DLYGLB4_ipd,   DLYGLB4,   tipd_DLYGLB4   );
990 
      VitalWireDelay ( OCDIVRST_ipd,  OCDIVRST,  tipd_OCDIVRST  );
991 
      VitalWireDelay ( OCDIVHALF_ipd, OCDIVHALF, tipd_OCDIVHALF );
992 
      VitalWireDelay ( OCDIV0_ipd,    OCDIV0,    tipd_OCDIV0    );
993 
      VitalWireDelay ( OCDIV1_ipd,    OCDIV1,    tipd_OCDIV1    );
994 
      VitalWireDelay ( OCDIV2_ipd,    OCDIV2,    tipd_OCDIV2    );
995 
      VitalWireDelay ( OCDIV3_ipd,    OCDIV3,    tipd_OCDIV3    );
996 
      VitalWireDelay ( OCDIV4_ipd,    OCDIV4,    tipd_OCDIV4    );
997 
      VitalWireDelay ( OCMUX0_ipd,    OCMUX0,    tipd_OCMUX0    );
998 
      VitalWireDelay ( OCMUX1_ipd,    OCMUX1,    tipd_OCMUX1    );
999 
      VitalWireDelay ( OCMUX2_ipd,    OCMUX2,    tipd_OCMUX2    );
1000 
      VitalWireDelay ( DLYYC0_ipd,    DLYYC0,    tipd_DLYYC0    );
1001 
      VitalWireDelay ( DLYYC1_ipd,    DLYYC1,    tipd_DLYYC1    );
1002 
      VitalWireDelay ( DLYYC2_ipd,    DLYYC2,    tipd_DLYYC2    );
1003 
      VitalWireDelay ( DLYYC3_ipd,    DLYYC3,    tipd_DLYYC3    );
1004 
      VitalWireDelay ( DLYYC4_ipd,    DLYYC4,    tipd_DLYYC4    );
1005 
      VitalWireDelay ( DLYGLC0_ipd,   DLYGLC0,   tipd_DLYGLC0   );
1006 
      VitalWireDelay ( DLYGLC1_ipd,   DLYGLC1,   tipd_DLYGLC1   );
1007 
      VitalWireDelay ( DLYGLC2_ipd,   DLYGLC2,   tipd_DLYGLC2   );
1008 
      VitalWireDelay ( DLYGLC3_ipd,   DLYGLC3,   tipd_DLYGLC3   );
1009 
      VitalWireDelay ( DLYGLC4_ipd,   DLYGLC4,   tipd_DLYGLC4   );
1010 
      VitalWireDelay ( FINDIV0_ipd,   FINDIV0,   tipd_FINDIV0   );
1011 
      VitalWireDelay ( FINDIV1_ipd,   FINDIV1,   tipd_FINDIV1   );
1012 
      VitalWireDelay ( FINDIV2_ipd,   FINDIV2,   tipd_FINDIV2   );
1013 
      VitalWireDelay ( FINDIV3_ipd,   FINDIV3,   tipd_FINDIV3   );
1014 
      VitalWireDelay ( FINDIV4_ipd,   FINDIV4,   tipd_FINDIV4   );
1015 
      VitalWireDelay ( FINDIV5_ipd,   FINDIV5,   tipd_FINDIV5   );
1016 
      VitalWireDelay ( FINDIV6_ipd,   FINDIV6,   tipd_FINDIV6   );
1017 
      VitalWireDelay ( FBDIV0_ipd,    FBDIV0,    tipd_FBDIV0    );
1018 
      VitalWireDelay ( FBDIV1_ipd,    FBDIV1,    tipd_FBDIV1    );
1019 
      VitalWireDelay ( FBDIV2_ipd,    FBDIV2,    tipd_FBDIV2    );
1020 
      VitalWireDelay ( FBDIV3_ipd,    FBDIV3,    tipd_FBDIV3    );
1021 
      VitalWireDelay ( FBDIV4_ipd,    FBDIV4,    tipd_FBDIV4    );
1022 
      VitalWireDelay ( FBDIV5_ipd,    FBDIV5,    tipd_FBDIV5    );
1023 
      VitalWireDelay ( FBDIV6_ipd,    FBDIV6,    tipd_FBDIV6    );
1024 
      VitalWireDelay ( FBDLY0_ipd,    FBDLY0,    tipd_FBDLY0    );
1025 
      VitalWireDelay ( FBDLY1_ipd,    FBDLY1,    tipd_FBDLY1    );
1026 
      VitalWireDelay ( FBDLY2_ipd,    FBDLY2,    tipd_FBDLY2    );
1027 
      VitalWireDelay ( FBDLY3_ipd,    FBDLY3,    tipd_FBDLY3    );
1028 
      VitalWireDelay ( FBDLY4_ipd,    FBDLY4,    tipd_FBDLY4    );
1029 
      VitalWireDelay ( FBSEL0_ipd,    FBSEL0,    tipd_FBSEL0    );
1030 
      VitalWireDelay ( FBSEL1_ipd,    FBSEL1,    tipd_FBSEL1    );
1031 
      VitalWireDelay ( XDLYSEL_ipd,   XDLYSEL,   tipd_XDLYSEL   );
1032 
      VitalWireDelay ( VCOSEL0_ipd,   VCOSEL0,   tipd_VCOSEL0   );
1033 
      VitalWireDelay ( VCOSEL1_ipd,   VCOSEL1,   tipd_VCOSEL1   );
1034 
      VitalWireDelay ( VCOSEL2_ipd,   VCOSEL2,   tipd_VCOSEL2   );
1035 
 
1036 
    end block WireDelay;
1037 
 
1038 
    -- #########################################################
1039 
    -- # Behavior Section
1040 
    -- #########################################################
1041 
 
1042 
    OAMUX_config <= ulogic2int( OAMUX2_ipd & OAMUX1_ipd & OAMUX0_ipd );
1043 
    OBMUX_config <= ulogic2int( OBMUX2_ipd & OBMUX1_ipd & OBMUX0_ipd );
1044 
    OCMUX_config <= ulogic2int( OCMUX2_ipd & OCMUX1_ipd & OCMUX0_ipd );
1045 
    FBSEL <= TO_X01( FBSEL1_ipd & FBSEL0_ipd );
1046 
 
1047 
    CLKA_2_GLA_dly         <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + gla_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLADELAY + GL_DRVR_DELAY;
1048 
    CLKA_2_GLA_bypass0_dly <= BYP0_CLK_GL + GLADELAY;
1049 
    CLKA_2_GLA_bypass1_dly <= gla_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLADELAY + GL_DRVR_DELAY;
1050 
 
1051 
    CLKA_2_GLB_dly         <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glb_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLBDELAY + GL_DRVR_DELAY;
1052 
    CLKB_2_GLB_bypass0_dly <= BYP0_CLK_GL + GLBDELAY;
1053 
    CLKB_2_GLB_bypass1_dly <= glb_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLBDELAY + GL_DRVR_DELAY;
1054 
    CLKA_2_YB_dly          <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glb_muxed_delay + OUT_DIV_DELAY + YBDELAY + Y_DRVR_DELAY;
1055 
    CLKB_2_YB_bypass1_dly  <= glb_muxed_delay + OUT_DIV_DELAY + YBDELAY + Y_DRVR_DELAY;
1056 
 
1057 
    CLKA_2_GLC_dly         <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glc_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLCDELAY + GL_DRVR_DELAY;
1058 
    CLKC_2_GLC_bypass0_dly <= BYP0_CLK_GL + GLCDELAY;
1059 
    CLKC_2_GLC_bypass1_dly <= glc_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLCDELAY + GL_DRVR_DELAY;
1060 
    CLKA_2_YC_dly          <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glc_muxed_delay + OUT_DIV_DELAY + YCDELAY + Y_DRVR_DELAY;
1061 
    CLKC_2_YC_bypass1_dly  <= glc_muxed_delay + OUT_DIV_DELAY + YCDELAY + Y_DRVR_DELAY;
1062 
 
1063 
    CLKA_2_LOCK_dly        <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + LOCK_OUT_DELAY;
1064 
 
1065 
    delay_LOCK: process( locked )
1066 
    begin
1067 
       if ( '1' = locked ) then
1068 
          LOCK <= transport locked after CLKA_2_LOCK_dly;
1069 
       else
1070 
          LOCK <= locked;
1071 
       end if;
1072 
    end process delay_LOCK;
1073 
 
1074 
    Deskew : process ( XDLYSEL_ipd )
1075 
      variable DelayVal             : Time := 0.000 ns;
1076 
    begin
1077 
      if (XDLYSEL_ipd = '1') then
1078 
        DelayVal := EMULATED_SYSTEM_DELAY;
1079 
      else
1080 
        DelayVal := 0.0 ns;
1081 
      end if;
1082 
      DTDELAY <= DelayVal;
1083 
    end process Deskew;
1084 
 
1085 
    GetFBDelay : process ( FBDLY0_ipd, FBDLY1_ipd, FBDLY2_ipd, FBDLY3_ipd, FBDLY4_ipd )
1086 
      variable step : integer;
1087 
    begin
1088 
      step := ulogic2int( FBDLY4_ipd & FBDLY3_ipd & FBDLY2_ipd & FBDLY1_ipd & FBDLY0_ipd );
1089 
      FBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
1090 
    end process GetFBDelay;
1091 
 
1092 
    GetGLBDelay : process ( DLYGLB0_ipd, DLYGLB1_ipd, DLYGLB2_ipd, DLYGLB3_ipd, DLYGLB4_ipd )
1093 
      variable step : integer;
1094 
    begin
1095 
      step := ulogic2int( DLYGLB4_ipd & DLYGLB3_ipd & DLYGLB2_ipd & DLYGLB1_ipd & DLYGLB0_ipd );
1096 
      if ( step = 0 ) then
1097 
        GLBDELAY <= 0.0 ns;
1098 
      else
1099 
        GLBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
1100 
      end if;
1101 
    end process GetGLBDelay;
1102 
 
1103 
    GetYBDelay : process ( DLYYB0_ipd, DLYYB1_ipd, DLYYB2_ipd, DLYYB3_ipd, DLYYB4_ipd )
1104 
      variable step : integer;
1105 
    begin
1106 
      step := ulogic2int( DLYYB4_ipd & DLYYB3_ipd & DLYYB2_ipd & DLYYB1_ipd & DLYYB0_ipd );
1107 
      YBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
1108 
    end process GetYBDelay;
1109 
 
1110 
    GetGLCDelay : process ( DLYGLC0_ipd, DLYGLC1_ipd, DLYGLC2_ipd, DLYGLC3_ipd, DLYGLC4_ipd )
1111 
      variable step : integer;
1112 
    begin
1113 
      step := ulogic2int( DLYGLC4_ipd & DLYGLC3_ipd & DLYGLC2_ipd & DLYGLC1_ipd & DLYGLC0_ipd );
1114 
      if ( step = 0 ) then
1115 
        GLCDELAY <= 0.0 ns;
1116 
      else
1117 
        GLCDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
1118 
      end if;
1119 
    end process GetGLCDelay;
1120 
 
1121 
    GetYCDelay : process ( DLYYC0_ipd, DLYYC1_ipd, DLYYC2_ipd, DLYYC3_ipd, DLYYC4_ipd )
1122 
      variable step : integer;
1123 
    begin
1124 
      step := ulogic2int( DLYYC4_ipd & DLYYC3_ipd & DLYYC2_ipd & DLYYC1_ipd & DLYYC0_ipd );
1125 
      YCDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
1126 
    end process GetYCDelay;
1127 
 
1128 
    GetGLADelay : process ( DLYGLA0_ipd, DLYGLA1_ipd, DLYGLA2_ipd, DLYGLA3_ipd, DLYGLA4_ipd )
1129 
      variable step : integer;
1130 
    begin
1131 
      step := ulogic2int( DLYGLA4_ipd & DLYGLA3_ipd & DLYGLA2_ipd & DLYGLA1_ipd & DLYGLA0_ipd );
1132 
      if ( step = 0 ) then
1133 
        GLADELAY <= 0.0 ns;
1134 
      else
1135 
        GLADELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
1136 
      end if;
1137 
    end process GetGLADelay;
1138 
 
1139 
    DIVM <= ulogic2int( FBDIV6_ipd & FBDIV5_ipd & FBDIV4_ipd & FBDIV3_ipd &
1140 
                        FBDIV2_ipd & FBDIV1_ipd & FBDIV0_ipd ) + 1;
1141 
 
1142 
    DIVN <= ulogic2int( FINDIV6_ipd & FINDIV5_ipd & FINDIV4_ipd & FINDIV3_ipd &
1143 
                        FINDIV2_ipd & FINDIV1_ipd & FINDIV0_ipd ) + 1;
1144 
 
1145 
    DIVU <= ulogic2int( OADIV4_ipd & OADIV3_ipd & OADIV2_ipd & OADIV1_ipd & OADIV0_ipd ) + 1;
1146 
 
1147 
    DIVV <= ulogic2int( OBDIV4_ipd & OBDIV3_ipd & OBDIV2_ipd & OBDIV1_ipd & OBDIV0_ipd ) + 1;
1148 
 
1149 
    DIVW <= ulogic2int( OCDIV4_ipd & OCDIV3_ipd & OCDIV2_ipd & OCDIV1_ipd & OCDIV0_ipd ) + 1;
1150 
 
1151 
    check_OADIVHALF : process
1152 
    begin
1153 
       wait on OADIVHALF_ipd, DIVU, OAMUX_config;
1154 
       if ( '1' = TO_X01( OADIVHALF_ipd ) ) then
1155 
         if ( 1 /= OAMUX_config ) then
1156 
            assert false
1157 
               report "Illegal configuration.  OADIVHALF can only be used when OAMUX = 001. OADIVHALF ignored."
1158 
               severity warning;
1159 
            halveA <= '0';
1160 
         elsif ( ( DIVU < 3 ) or ( DIVU > 29 ) or ( ( DIVU mod 2 ) /= 1 ) ) then
1161 
            assert false
1162 
               report "Illegal configuration. Only even OADIV values from 2 to 28 (inclusive) are allowed with OADIVHALF."
1163 
               severity warning;
1164 
            halveA <= 'X';
1165 
         else
1166 
            halveA <= '1';
1167 
         end if;
1168 
       elsif ( OADIVHALF_ipd'event and ( 'X' = TO_X01( OADIVHALF_ipd ) ) ) then
1169 
          assert false
1170 
             report "OADIVHALF unknown."
1171 
             severity warning;
1172 
          halveA <= 'X';
1173 
       else
1174 
          halveA <= '0';
1175 
       end if;
1176 
    end process check_OADIVHALF;
1177 
 
1178 
    check_OBDIVHALF : process
1179 
    begin
1180 
       wait on OBDIVHALF_ipd, DIVV, OBMUX_config;
1181 
       if ( '1' = TO_X01( OBDIVHALF_ipd ) ) then
1182 
         if ( 1 /= OBMUX_config ) then
1183 
            assert false
1184 
               report "Illegal configuration.  OBDIVHALF can only be used when OBMUX = 001. OBDIVHALF ignored."
1185 
               severity warning;
1186 
            halveB <= '0';
1187 
         elsif ( ( DIVV < 3 ) or ( DIVV > 29 ) or ( ( DIVV mod 2 ) /= 1 ) ) then
1188 
            assert false
1189 
               report "Illegal configuration. Only even OBDIV values from 2 to 28 (inclusive) are allowed with OBDIVHALF."
1190 
               severity warning;
1191 
            halveB <= 'X';
1192 
         else
1193 
            halveB <= '1';
1194 
         end if;
1195 
       elsif ( OBDIVHALF_ipd'event and ( 'X' = TO_X01( OBDIVHALF_ipd ) ) ) then
1196 
          assert false
1197 
             report "OBDIVHALF unknown."
1198 
             severity warning;
1199 
          halveB <= 'X';
1200 
       else
1201 
          halveB <= '0';
1202 
       end if;
1203 
    end process check_OBDIVHALF;
1204 
 
1205 
    check_OCDIVHALF : process
1206 
    begin
1207 
       wait on OCDIVHALF_ipd, DIVW, OCMUX_config;
1208 
       if ( '1' = TO_X01( OCDIVHALF_ipd ) ) then
1209 
         if ( 1 /= OCMUX_config ) then
1210 
            assert false
1211 
               report "Illegal configuration.  OCDIVHALF can only be used when OCMUX = 001. OCDIVHALF ignored."
1212 
               severity warning;
1213 
            halveC <= '0';
1214 
         elsif ( ( DIVW < 3 ) or ( DIVW > 29 ) or ( ( DIVW mod 2 ) /= 1 ) ) then
1215 
            assert false
1216 
               report "Illegal configuration. Only even OCDIV values from 2 to 28 (inclusive) are allowed with OCDIVHALF."
1217 
               severity warning;
1218 
            halveC <= 'X';
1219 
         else
1220 
            halveC <= '1';
1221 
         end if;
1222 
       elsif ( OCDIVHALF_ipd'event and ( 'X' = TO_X01( OCDIVHALF_ipd ) ) ) then
1223 
          assert false
1224 
             report "OCDIVHALF unknown."
1225 
             severity warning;
1226 
          halveC <= 'X';
1227 
       else
1228 
          halveC <= '0';
1229 
       end if;
1230 
    end process check_OCDIVHALF;
1231 
 
1232 
    gla_muxed_delay <= output_mux_delay( OAMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
1233 
    glb_muxed_delay <= output_mux_delay( OBMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
1234 
    glc_muxed_delay <= output_mux_delay( OCMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
1235 
 
1236 
    get_internal_fb_dly : process( FBSEL, FBDELAY, DTDELAY, fin_period )
1237 
       variable fb_delay : time;
1238 
    begin
1239 
       fb_delay := IN_DIV_DELAY + X_MUX_DELAY + DTDELAY + FB_MUX_DELAY;
1240 
       if ( "10" = FBSEL ) then
1241 
         fb_delay := fb_delay + FBDELAY;
1242 
       end if;
1243 
       internal_fb_delay <= fb_delay;
1244 
    end process get_internal_fb_dly;
1245 
 
1246 
    external_fb_delay <= IN_DIV_DELAY + X_MUX_DELAY + DTDELAY + FB_MUX_DELAY + GL_DRVR_DELAY + GLADELAY + BYP_MUX_DELAY + OUT_DIV_DELAY + gla_muxed_delay + GLA_EXTFB_rise_dly;
1247 
 
1248 
    normalize_fb_dly : process( using_EXTFB, internal_fb_delay, external_fb_delay, fin_period )
1249 
       variable norm : time;
1250 
    begin
1251 
       if ( using_EXTFB = '1' ) then
1252 
          norm := external_fb_delay;
1253 
       else
1254 
          norm := internal_fb_delay;
1255 
       end if;
1256 
       if ( 0 ns >= fin_period ) then
1257 
          norm := 0 ns;
1258 
       else
1259 
         while ( norm > fin_period ) loop
1260 
            norm := norm - fin_period;
1261 
         end loop;
1262 
       end if;
1263 
       normalized_fb_delay <= norm;
1264 
    end process normalize_fb_dly;
1265 
 
1266 
    check_FBSEL : process
1267 
    begin
1268 
      wait on FBSEL, OAMUX_config, OBMUX_config, OCMUX_config, DIVM, DIVU, DIVN, CLKA_period_stable, PLLCLK_period, external_fb_delay;
1269 
      if ( IS_X( FBSEL ) ) then
1270 
         FBSEL_illegal <= true;
1271 
         assert ( not FBSEL'event )
1272 
            report "Warning: FBSEL is unknown."
1273 
            severity Warning;
1274 
      elsif ( "00" = FBSEL ) then -- Grounded.
1275 
         FBSEL_illegal <= true;
1276 
         assert ( not FBSEL'event )
1277 
            report "Warning: Illegal FBSEL configuration 00."
1278 
            severity Warning;
1279 
      elsif ( "11" = FBSEL ) then -- External feedback
1280 
         if ( 2 > OAMUX_config ) then
1281 
            FBSEL_illegal <= true;
1282 
            assert  ( not ( FBSEL'event or OAMUX_config'event ) )
1283 
               report "Illegal configuration. GLA cannot be in bypass mode (OAMUX = 000 or OAMUX = 001) when using external feedback (FBSEL = 11)."
1284 
               severity Warning;
1285 
         elsif ( DIVM < 5 ) then
1286 
            FBSEL_illegal <= true;
1287 
            assert ( not ( FBSEL'event or DIVM'event ) )
1288 
               report "Error: FBDIV must be greater than 4 when using external feedback (FBSEL = 11)."
1289 
               severity Error;
1290 
         elsif ( ( DIVM * DIVU ) > 232 ) then
1291 
            FBSEL_illegal <= true;
1292 
            assert ( not ( FBSEL'event or DIVM'event or DIVU'event ) )
1293 
               report "Error: Product of FBDIV and OADIV must be less than 233 when using external feedback (FBSEL = 11)."
1294 
               severity Error;
1295 
         elsif ( ( DIVN mod DIVU ) /= 0 ) then
1296 
            FBSEL_illegal <= true;
1297 
            assert ( not ( FBSEL'event or DIVN'event or DIVU'event ) )
1298 
               report "Error: Division factor FINDIV must be a multiple of OADIV when using external feedback (FBSEL = 11)."
1299 
               severity Error;
1300 
         elsif ( CLKA_period_stable and EXTFB_delay_dtrmd and
1301 
                 ( ( 1 < OBMUX_config ) or ( 1 < OCMUX_config ) ) and
1302 
                 ( ( external_fb_delay >= CLKA_period ) or ( external_fb_delay >= PLLCLK_period ) ) ) then
1303 
            FBSEL_illegal <= true;
1304 
            assert ( not ( FBSEL'event or CLKA_period_stable'event or external_fb_delay'event or PLLCLK_period'event ) )
1305 
              report "Error: Total sum of delays in the feedback path must be less than 1 VCO period AND less than 1 CLKA period when V and/or W dividers when using external feedback (FBSEL = 11)."
1306 
               severity Error;
1307 
         else
1308 
            FBSEL_illegal <= false;
1309 
         end if;
1310 
      else
1311 
         FBSEL_illegal <= false;
1312 
      end if;
1313 
    end process check_FBSEL;
1314 
 
1315 
    -- Mimicing silicon - no need for a 50/50 duty cycle and this way fin only changes on rising edge of CLKA (except when DIVN is 1)
1316 
    gen_fin: process
1317 
      variable num_CLKA_re   : integer;
1318 
    begin
1319 
       wait until rising_edge( CLKA_ipd );
1320 
       fin <= '1';
1321 
       num_CLKA_re := 0;
1322 
       while ( 'X' /= TO_X01( CLKA_ipd ) ) loop
1323 
          wait on CLKA_ipd;
1324 
          if ( 1 = DIVN )then
1325 
             fin <= CLKA_ipd;
1326 
          elsif ( '1' = CLKA_ipd ) then
1327 
             num_CLKA_re := num_CLKA_re + 1;
1328 
             if ( ( num_CLKA_re mod DIVN  ) = 0 ) then
1329 
                fin <= '1';
1330 
                num_CLKA_re := 0;
1331 
             elsif ( ( num_CLKA_re mod DIVN ) = 1 ) then
1332 
                fin <= '0';
1333 
             end if;
1334 
          end if;
1335 
       end loop;
1336 
    end process gen_fin;
1337 
 
1338 
    GetCLKAPeriod : process ( CLKA_ipd, POWERDOWN_ipd, FBSEL_illegal, normalized_fb_delay, DIVN, DIVM, locked_vco0_edges, external_dly_correct )
1339 
      -- locked_vco0_edges is in the sensitivity list so that we periodically check for CLKA stopped
1340 
      variable re                 : Time :=  0.000 ns; -- Current CLKA rising edge
1341 
      variable CLKA_num_re_stable : Integer := -1;   -- Number of CLKA rising edges that PLL config stable
1342 
    begin
1343 
      if (( TO_X01( POWERDOWN_ipd ) = '1' ) and ( FBSEL_illegal = False ))  then
1344 
        if ( normalized_fb_delay'event or DIVN'event or DIVM'event or
1345 
             ( ( '1' = using_EXTFB ) and ( '1' /= external_dly_correct ) ) ) then
1346 
          internal_lock <= false;
1347 
          CLKA_num_re_stable := -1;
1348 
        end if;
1349 
        if ( CLKA_ipd'event and ( '1' = TO_X01( CLKA_ipd ) ) ) then
1350 
           if ( CLKA_period /= ( NOW - re ) ) then
1351 
              CLKA_period <= ( NOW - re );
1352 
              CLKA_num_re_stable := -1;
1353 
              internal_lock <= false;
1354 
              CLKA_period_stable <= false;
1355 
           else
1356 
              if ( f_CLKA_LOCK > CLKA_num_re_stable ) then
1357 
                 CLKA_num_re_stable := CLKA_num_re_stable + 1;
1358 
              elsif ( f_CLKA_LOCK = CLKA_num_re_stable ) then
1359 
                 internal_lock <=  true;
1360 
              end if;
1361 
              CLKA_period_stable <= true;
1362 
           end if;
1363 
           re := NOW;
1364 
        elsif ( CLKA_period < ( NOW - re ) ) then
1365 
           CLKA_num_re_stable := -1;
1366 
           internal_lock <= false;
1367 
           CLKA_period_stable <= false;
1368 
        end if;
1369 
      else
1370 
        CLKA_num_re_stable := -1;
1371 
        internal_lock <= false;
1372 
        CLKA_period_stable <= false;
1373 
      end if;
1374 
    end process GetCLKAPeriod;
1375 
 
1376 
    fin_period         <= CLKA_period * DIVN;
1377 
 
1378 
    GLA_pw             <= PLLCLK_pw * DIVU;
1379 
 
1380 
    extfbin_fin_drift  <= ( GLA_pw * DIVM * 2.0 ) - fin_period;
1381 
 
1382 
    PLLCLK_period      <= fin_period / real( fb_loop_div );
1383 
 
1384 
    PLLCLK_pw          <= PLLCLK_period / 2.0;
1385 
 
1386 
    calc_fb_loop_div : process( DIVM, DIVU, using_EXTFB )
1387 
    begin
1388 
       if ( using_EXTFB  = '1' ) then
1389 
           fb_loop_div <= DIVM * DIVU;
1390 
       else
1391 
           fb_loop_div <= DIVM;
1392 
       end if;
1393 
    end process calc_fb_loop_div;
1394 
 
1395 
    sync_pll : process( fin, internal_lock, DYNSYNC )
1396 
    begin
1397 
       if ( not( internal_lock ) or ( '1' = DYNSYNC ) ) then
1398 
          locked <= '0';
1399 
       elsif ( rising_edge( fin ) ) then
1400 
          locked <= '1';
1401 
       end if;
1402 
    end process sync_pll;
1403 
 
1404 
    count_locked_vco0_edges: process( locked, locked_vco0_edges )
1405 
    begin
1406 
       if ( locked'event ) then
1407 
          if ( locked = '1' ) then
1408 
            locked_vco0_edges <= 0;
1409 
          else
1410 
            locked_vco0_edges <= -1;
1411 
          end if;
1412 
       elsif ( locked = '1' ) then
1413 
          if ( ( locked_vco0_edges mod( DIVU * DIVV * DIVW * DIVM * 2 ) ) = 0 ) then
1414 
             locked_vco0_edges <= 1 after PLLCLK_pw;
1415 
          else
1416 
             locked_vco0_edges <= ( locked_vco0_edges + 1 ) after PLLCLK_pw;
1417 
          end if;
1418 
       end if;
1419 
    end process count_locked_vco0_edges;
1420 
 
1421 
    gen_vco0_div: process( locked_vco0_edges )
1422 
    begin
1423 
       if ( locked_vco0_edges = -1 ) then
1424 
          vco0_divu <= '0';
1425 
          vco0_divv <= '0';
1426 
          vco0_divw <= '0';
1427 
       else
1428 
         if ( ( locked_vco0_edges mod DIVU ) = 0 ) then
1429 
           vco0_divu <= not vco0_divu;
1430 
         end if;
1431 
         if ( ( locked_vco0_edges mod DIVV ) = 0 ) then
1432 
           vco0_divv <= not vco0_divv;
1433 
         end if;
1434 
         if ( ( locked_vco0_edges mod DIVW ) = 0 ) then
1435 
           vco0_divw <= not vco0_divw;
1436 
         end if;
1437 
       end if;
1438 
    end process gen_vco0_div;
1439 
 
1440 
    UIN <= output_mux_driver(  OAMUX_config, halveA, CLKA_ipd, CLKA2X, vco0_divu );
1441 
    VIN <= output_mux_driver(  OBMUX_config, halveB, CLKB_ipd, CLKB2X, vco0_divv );
1442 
    WIN <= output_mux_driver(  OCMUX_config, halveC, CLKC_ipd, CLKC2X, vco0_divw );
1443 
 
1444 
    double_CLKA: process( CLKA_ipd )
1445 
       variable re      : Time := 0 ns;
1446 
       variable prev_re : Time := 0 ns;
1447 
       variable period  : Time := 0 ns;
1448 
    begin
1449 
       if ( TO_X01( CLKA_ipd ) = '1' ) then
1450 
         prev_re := re;
1451 
         re := NOW;
1452 
         period := re - prev_re;
1453 
         if ( period > 0 ns ) then
1454 
            CLKA2X <= '1';
1455 
            CLKA2X <= transport '0' after ( period / 4.0 );
1456 
            CLKA2X <= transport '1' after ( period / 2.0 );
1457 
            CLKA2X <= transport '0' after ( period * 3.0 / 4.0 );
1458 
         end if;
1459 
       end if;
1460 
    end process double_CLKA;
1461 
 
1462 
    double_CLKB: process( CLKB_ipd )
1463 
       variable re      : Time := 0 ns;
1464 
       variable prev_re : Time := 0 ns;
1465 
       variable period  : Time := 0 ns;
1466 
    begin
1467 
       if ( TO_X01( CLKB_ipd ) = '1' ) then
1468 
         prev_re := re;
1469 
         re := NOW;
1470 
         period := re - prev_re;
1471 
         if ( period > 0 ns ) then
1472 
            CLKB2X <= '1';
1473 
            CLKB2X <= transport '0' after ( period / 4.0 );
1474 
            CLKB2X <= transport '1' after ( period / 2.0 );
1475 
            CLKB2X <= transport '0' after ( period * 3.0 / 4.0 );
1476 
         end if;
1477 
       end if;
1478 
    end process double_CLKB;
1479 
 
1480 
    double_CLKC: process( CLKC_ipd )
1481 
       variable re      : Time := 0 ns;
1482 
       variable prev_re : Time := 0 ns;
1483 
       variable period  : Time := 0 ns;
1484 
    begin
1485 
       if ( TO_X01( CLKC_ipd ) = '1' ) then
1486 
         prev_re := re;
1487 
         re := NOW;
1488 
         period := re - prev_re;
1489 
         if ( period > 0 ns ) then
1490 
            CLKC2X <= '1';
1491 
            CLKC2X <= transport '0' after ( period / 4.0 );
1492 
            CLKC2X <= transport '1' after ( period / 2.0 );
1493 
            CLKC2X <= transport '0' after ( period * 3.0 / 4.0 );
1494 
         end if;
1495 
       end if;
1496 
    end process double_CLKC;
1497 
 
1498 
    --
1499 
    -- AOUT Output of Divider U
1500 
    --
1501 
 
1502 
    DividerU : process ( UIN, CLKA_ipd, OADIVRST_ipd, OADIVHALF_ipd,
1503 
                         POWERDOWN_ipd )
1504 
 
1505 
      variable force_0         : Boolean  := True;
1506 
      variable num_edges       : Integer  := -1;
1507 
      variable res_post_reset1 : Integer  :=  0;
1508 
      variable fes_post_reset1 : Integer  :=  0;
1509 
      variable res_post_reset0 : Integer  :=  0;
1510 
      variable fes_post_reset0 : Integer  :=  0;
1511 
 
1512 
    begin
1513 
 
1514 
      if ( 1 = OAMUX_config ) then -- PLL core bypassed.  OADIVRST active.
1515 
 
1516 
        if ( CLKA_ipd'event ) then
1517 
          if ( TO_X01( CLKA_ipd ) = '1' and TO_X01( CLKA_ipd'last_value ) = '0' ) then
1518 
             if ( 4 > res_post_reset1 ) then
1519 
                res_post_reset1 := res_post_reset1 + 1;
1520 
             end if;
1521 
             if ( 4 > res_post_reset0 ) then
1522 
               res_post_reset0 := res_post_reset0 + 1;
1523 
             end if;
1524 
             if ( res_post_reset1 = 3 ) then
1525 
                force_0 := False;
1526 
                num_edges := -1;
1527 
             end if;
1528 
          elsif ( TO_X01( CLKA_ipd ) = '0' and TO_X01( CLKA_ipd'last_value ) = '1' ) then
1529 
             if ( 4 > fes_post_reset1 ) then
1530 
               fes_post_reset1 := fes_post_reset1 + 1;
1531 
             end if;
1532 
             if ( 4 > fes_post_reset0 ) then
1533 
               fes_post_reset0 := fes_post_reset0 + 1;
1534 
             end if;
1535 
             if ( fes_post_reset1 = 1 ) then
1536 
                force_0 := True;
1537 
             end if;
1538 
          end if;
1539 
        end if;
1540 
 
1541 
        if ( OADIVRST_ipd'event ) then
1542 
          if ( TO_X01( OADIVRST_ipd ) = '1' ) then
1543 
            if ( ( TO_X01( OADIVRST_ipd'last_value ) = '0' ) and
1544 
                 ( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
1545 
              assert false
1546 
              report "OADIVRST must be held low for at least one CLKA period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
1547 
              severity warning;
1548 
            end if;
1549 
            res_post_reset1 := 0;
1550 
            fes_post_reset1 := 0;
1551 
          elsif ( TO_X01( OADIVRST_ipd ) = '0' ) then
1552 
            if ( ( TO_X01( OADIVRST_ipd'last_value ) = '1' ) and
1553 
                 ( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
1554 
              assert false
1555 
              report "OADIVRST must be held high for at least three CLKA periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
1556 
              severity warning;
1557 
            end if;
1558 
            res_post_reset0 := 0;
1559 
            fes_post_reset0 := 0;
1560 
          else
1561 
            assert false
1562 
            report "OADIVRST is unknown. Edge alignment unpredictable."
1563 
            severity warning;
1564 
          end if;
1565 
        end if;
1566 
 
1567 
        if ( UIN'event ) then
1568 
          num_edges := num_edges + 1;
1569 
          if ( force_0 ) then
1570 
            AOUT <= '0';
1571 
          elsif ( TO_X01( UIN ) = 'X' ) then
1572 
            AOUT <= 'X';
1573 
          elsif ( ( num_edges mod DIVU ) = 0 ) then
1574 
            num_edges := 0;
1575 
            if ( TO_X01 ( AOUT ) = 'X' ) then
1576 
              AOUT <= UIN;
1577 
            else
1578 
              AOUT <= not AOUT;
1579 
            end if;
1580 
          end if;
1581 
        end if;
1582 
 
1583 
      else -- PLL not bypassed
1584 
        if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
1585 
          AOUT <= '0';
1586 
        elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
1587 
          AOUT <= UIN;
1588 
        else -- POWERDOWN unknown
1589 
          AOUT <= 'X';
1590 
        end if;
1591 
      end if;
1592 
 
1593 
    end process DividerU;
1594 
 
1595 
 
1596 
    --
1597 
    -- BOUT Output of Divider V
1598 
    --
1599 
 
1600 
    DividerV : process ( VIN, CLKB_ipd, OBDIVRST_ipd, OBDIVHALF_ipd,
1601 
                         POWERDOWN_ipd )
1602 
 
1603 
      variable force_0         : Boolean  := True;
1604 
      variable num_edges       : Integer  := -1;
1605 
      variable res_post_reset1 : Integer  :=  0;
1606 
      variable fes_post_reset1 : Integer  :=  0;
1607 
      variable res_post_reset0 : Integer  :=  0;
1608 
      variable fes_post_reset0 : Integer  :=  0;
1609 
 
1610 
    begin
1611 
 
1612 
      if ( 0 = OBMUX_config ) then
1613 
        BOUT <= 'X';
1614 
      elsif ( 1 = OBMUX_config ) then -- PLL core bypassed.  OBDIVRST active.
1615 
 
1616 
        if ( CLKB_ipd'event ) then
1617 
          if ( TO_X01( CLKB_ipd ) = '1' and TO_X01( CLKB_ipd'last_value ) = '0' ) then
1618 
             if ( 4 > res_post_reset1 ) then
1619 
               res_post_reset1 := res_post_reset1 + 1;
1620 
             end if;
1621 
             if ( 4 > res_post_reset0 ) then
1622 
               res_post_reset0 := res_post_reset0 + 1;
1623 
             end if;
1624 
             if ( res_post_reset1 = 3 ) then
1625 
                force_0 := False;
1626 
                num_edges := -1;
1627 
             end if;
1628 
          elsif ( TO_X01( CLKB_ipd ) = '0' and TO_X01( CLKB_ipd'last_value ) = '1' ) then
1629 
             if ( 4 > fes_post_reset1 ) then
1630 
               fes_post_reset1 := fes_post_reset1 + 1;
1631 
             end if;
1632 
             if ( 4 > fes_post_reset0 ) then
1633 
               fes_post_reset0 := fes_post_reset0 + 1;
1634 
             end if;
1635 
             if ( fes_post_reset1 = 1 ) then
1636 
                force_0 := True;
1637 
             end if;
1638 
          end if;
1639 
        end if;
1640 
 
1641 
        if ( OBDIVRST_ipd'event ) then
1642 
          if ( TO_X01( OBDIVRST_ipd ) = '1' ) then
1643 
            if ( ( TO_X01( OBDIVRST_ipd'last_value ) = '0' ) and
1644 
                 ( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
1645 
              assert false
1646 
              report "OBDIVRST must be held low for at least one CLKB period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
1647 
              severity warning;
1648 
            end if;
1649 
            res_post_reset1 := 0;
1650 
            fes_post_reset1 := 0;
1651 
          elsif ( TO_X01( OBDIVRST_ipd ) = '0' ) then
1652 
            if ( ( TO_X01( OBDIVRST_ipd'last_value ) = '1' ) and
1653 
                 ( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
1654 
              assert false
1655 
              report "OBDIVRST must be held high for at least three CLKB periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
1656 
              severity warning;
1657 
            end if;
1658 
            res_post_reset0 := 0;
1659 
            fes_post_reset0 := 0;
1660 
          else
1661 
            assert false
1662 
            report "OBDIVRST is unknown. Edge alignment unpredictable."
1663 
            severity warning;
1664 
          end if;
1665 
        end if;
1666 
 
1667 
        if ( VIN'event ) then
1668 
          num_edges := num_edges + 1;
1669 
          if ( force_0 ) then
1670 
            BOUT <= '0';
1671 
          elsif ( TO_X01( VIN ) = 'X' ) then
1672 
            BOUT <= 'X';
1673 
          elsif ( ( num_edges mod DIVV ) = 0 ) then
1674 
            num_edges := 0;
1675 
            if ( TO_X01 ( BOUT ) = 'X' ) then
1676 
              BOUT <= VIN;
1677 
            else
1678 
              BOUT <= not BOUT;
1679 
            end if;
1680 
          end if;
1681 
        end if;
1682 
 
1683 
      else -- PLL not bypassed
1684 
        if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
1685 
          BOUT <= '0';
1686 
        elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
1687 
          BOUT <= VIN;
1688 
        else -- POWERDOWN unknown
1689 
          BOUT <= 'X';
1690 
        end if;
1691 
      end if;
1692 
 
1693 
    end process DividerV;
1694 
 
1695 
    --
1696 
    -- COUT Output of Divider W
1697 
    --
1698 
 
1699 
    DividerW : process ( WIN, CLKC_ipd, OCDIVRST_ipd, OCDIVHALF_ipd,
1700 
                         POWERDOWN_ipd )
1701 
 
1702 
      variable force_0         : Boolean  := True;
1703 
      variable num_edges       : Integer  := -1;
1704 
      variable res_post_reset1 : Integer  :=  0;
1705 
      variable fes_post_reset1 : Integer  :=  0;
1706 
      variable res_post_reset0 : Integer  :=  0;
1707 
      variable fes_post_reset0 : Integer  :=  0;
1708 
 
1709 
    begin
1710 
 
1711 
      if ( 0 = OCMUX_config ) then
1712 
        COUT <= 'X';
1713 
      elsif ( 1 = OCMUX_config ) then -- PLL core bypassed.  OCDIVRST active.
1714 
 
1715 
        if ( CLKC_ipd'event ) then
1716 
          if ( TO_X01( CLKC_ipd ) = '1' and TO_X01( CLKC_ipd'last_value ) = '0' ) then
1717 
             if ( 4 > res_post_reset1 ) then
1718 
               res_post_reset1 := res_post_reset1 + 1;
1719 
             end if;
1720 
             if ( 4 > res_post_reset0 ) then
1721 
               res_post_reset0 := res_post_reset0 + 1;
1722 
             end if;
1723 
             if ( res_post_reset1 = 3 ) then
1724 
                force_0 := False;
1725 
                num_edges := -1;
1726 
             end if;
1727 
          elsif ( TO_X01( CLKC_ipd ) = '0' and TO_X01( CLKC_ipd'last_value ) = '1' ) then
1728 
             if ( 4 > fes_post_reset1 ) then
1729 
               fes_post_reset1 := fes_post_reset1 + 1;
1730 
             end if;
1731 
             if ( 4 > fes_post_reset0 ) then
1732 
               fes_post_reset0 := fes_post_reset0 + 1;
1733 
             end if;
1734 
             if ( fes_post_reset1 = 1 ) then
1735 
                force_0 := True;
1736 
             end if;
1737 
          end if;
1738 
        end if;
1739 
 
1740 
        if ( OCDIVRST_ipd'event ) then
1741 
          if ( TO_X01( OCDIVRST_ipd ) = '1' ) then
1742 
            if ( ( TO_X01( OCDIVRST_ipd'last_value ) = '0' ) and
1743 
                 ( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
1744 
              assert false
1745 
              report "OCDIVRST must be held low for at least one CLKC period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
1746 
              severity warning;
1747 
            end if;
1748 
            res_post_reset1 := 0;
1749 
            fes_post_reset1 := 0;
1750 
          elsif ( TO_X01( OCDIVRST_ipd ) = '0' ) then
1751 
            if ( ( TO_X01( OCDIVRST_ipd'last_value ) = '1' ) and
1752 
                 ( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
1753 
              assert false
1754 
              report "OCDIVRST must be held high for at least three CLKC periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
1755 
              severity warning;
1756 
            end if;
1757 
            res_post_reset0 := 0;
1758 
            fes_post_reset0 := 0;
1759 
          else
1760 
            assert false
1761 
            report "OCDIVRST is unknown. Edge alignment unpredictable."
1762 
            severity warning;
1763 
          end if;
1764 
        end if;
1765 
 
1766 
        if ( WIN'event ) then
1767 
          num_edges := num_edges + 1;
1768 
          if ( force_0 ) then
1769 
            COUT <= '0';
1770 
          elsif ( TO_X01( WIN ) = 'X' ) then
1771 
            COUT <= 'X';
1772 
          elsif ( ( num_edges mod DIVW ) = 0 ) then
1773 
            num_edges := 0;
1774 
            if ( TO_X01 ( COUT ) = 'X' ) then
1775 
              COUT <= WIN;
1776 
            else
1777 
              COUT <= not COUT;
1778 
            end if;
1779 
          end if;
1780 
        end if;
1781 
 
1782 
      else -- PLL not bypassed
1783 
        if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
1784 
          COUT <= '0';
1785 
        elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
1786 
          COUT <= WIN;
1787 
        else -- POWERDOWN unknown
1788 
          COUT <= 'X';
1789 
        end if;
1790 
      end if;
1791 
 
1792 
    end process DividerW;
1793 
 
1794 
    using_EXTFB <= TO_X01( FBSEL1_ipd and FBSEL0_ipd );
1795 
 
1796 
    external_dly_correct <= expected_EXTFB xnor EXTFB_ipd after 1 ps;
1797 
 
1798 
    get_EXTFB_period : process
1799 
      variable previous_re : time :=  0.000 ns; -- Previous EXTFB rising edge
1800 
    begin
1801 
      wait until rising_edge( EXTFB );
1802 
      EXTFB_period <= NOW - previous_re;
1803 
      previous_re := NOW;
1804 
    end process get_EXTFB_period;
1805 
 
1806 
    calculate_extfb_delay : process
1807 
      variable CLKA_edge : time := 0 ns;
1808 
    begin
1809 
       EXTFB_delay_dtrmd <= false;
1810 
       if ( ( '1' /= using_EXTFB ) or ( not CLKA_period_stable ) ) then
1811 
          wait until ( ( '1' = using_EXTFB ) and CLKA_period_stable );
1812 
       end if;
1813 
       wait for GLA_EXTFB_rise_dly;
1814 
       GLA_EXTFB_fall_dly <= 0 ps;
1815 
       GLA_EXTFB_rise_dly <= 0 ps;
1816 
       wait for ( CLKA_2_GLA_dly * 2);
1817 
       calibrate_EXTFB_delay <= '1';
1818 
       if ( '1' /= EXTFB_ipd ) then
1819 
          wait until ( EXTFB_ipd = '1' );
1820 
       end if;
1821 
       wait until falling_edge( CLKA_ipd );
1822 
       CLKA_edge := NOW;
1823 
       calibrate_EXTFB_delay <= '0';
1824 
       wait until falling_edge( EXTFB_ipd );
1825 
       GLA_EXTFB_fall_dly <= NOW - CLKA_edge - CLKA_2_GLA_dly;
1826 
       wait until rising_edge( CLKA_ipd );
1827 
       CLKA_edge := NOW;
1828 
       calibrate_EXTFB_delay <= '1';
1829 
       wait until rising_edge( EXTFB_ipd );
1830 
       GLA_EXTFB_rise_dly <= NOW - CLKA_edge - CLKA_2_GLA_dly;
1831 
       wait until falling_edge( CLKA_ipd );
1832 
       wait until ( CLKA_period_stable and rising_edge( fin ) );
1833 
       EXTFB_delay_dtrmd <= true;
1834 
       wait until falling_edge( expected_EXTFB );
1835 
       if ( '1' /= external_dly_correct ) then
1836 
         assert false
1837 
         report "ERROR: EXTFB must be a simple, time-delayed derivative of GLA. Simulation cannot continue until user-logic is corrected"
1838 
         severity failure;
1839 
         wait;
1840 
       end if;
1841 
       wait until ( '1' /= external_dly_correct );
1842 
    end process calculate_extfb_delay;
1843 
 
1844 
    external_feedback : process
1845 
       variable edges : integer := 1;
1846 
    begin
1847 
       wait on GLA_free_running, EXTFB_delay_dtrmd;
1848 
       if ( EXTFB_delay_dtrmd ) then
1849 
         if ( ( edges mod ( DIVM * 2 ) ) = 0 ) then
1850 
            GLA_free_running <= not GLA_free_running after ( GLA_pw - extfbin_fin_drift );
1851 
            edges := 0;
1852 
         else
1853 
            GLA_free_running <= not GLA_free_running after GLA_pw;
1854 
         end if;
1855 
         edges := edges + 1;
1856 
       else
1857 
         edges := 1;
1858 
         GLA_free_running <= '1' after GLA_pw;
1859 
       end if;
1860 
    end process external_feedback;
1861 
 
1862 
    gen_AOUT_using_EXTFB : process( AOUT, GLA_free_running, calibrate_EXTFB_delay, locked_vco0_edges, EXTFB_delay_dtrmd )
1863 
    begin
1864 
       if ( 0 <= locked_vco0_edges ) then
1865 
          AOUT_using_EXTFB <= AOUT;
1866 
       elsif ( EXTFB_delay_dtrmd ) then
1867 
          AOUT_using_EXTFB <= GLA_free_running;
1868 
       else
1869 
          AOUT_using_EXTFB <= calibrate_EXTFB_delay;
1870 
       end if;
1871 
    end process gen_AOUT_using_EXTFB;
1872 
 
1873 
    gen_expected_EXTFB: process( AOUT_using_EXTFB, EXTFB_delay_dtrmd )
1874 
    begin
1875 
       if ( not EXTFB_delay_dtrmd ) then
1876 
          expected_EXTFB <= 'X';
1877 
       elsif ( '1' = AOUT_using_EXTFB ) then
1878 
          expected_EXTFB <= transport AOUT_using_EXTFB after ( CLKA_2_GLA_dly + GLA_EXTFB_rise_dly );
1879 
       else
1880 
          expected_EXTFB <= transport AOUT_using_EXTFB after ( CLKA_2_GLA_dly + GLA_EXTFB_fall_dly );
1881 
       end if;
1882 
    end process gen_expected_EXTFB;
1883 
 
1884 
    Aoutputs: process( AOUT, CLKA_ipd, AOUT_using_EXTFB, OAMUX_config  )
1885 
    begin
1886 
        if ( 0 = OAMUX_config ) then
1887 
          GLA <= transport CLKA_ipd after CLKA_2_GLA_bypass0_dly;
1888 
        elsif ( ( 1 = OAMUX_config ) or ( 3 = OAMUX_config ) ) then
1889 
          GLA <= transport 'X' after CLKA_2_GLA_dly;
1890 
          assert ( not OAMUX_config'event )
1891 
            report "WARNING: Illegal OAMUX configuration."
1892 
            severity warning;
1893 
        elsif ( '1' = using_EXTFB ) then
1894 
          GLA <= transport AOUT_using_EXTFB after CLKA_2_GLA_dly;
1895 
        else
1896 
          GLA <= transport AOUT after CLKA_2_GLA_dly;
1897 
        end if;
1898 
    end process Aoutputs;
1899 
 
1900 
    Boutputs: process ( BOUT, CLKB_ipd, OBMUX_config )
1901 
    begin
1902 
        if ( 0 = OBMUX_config ) then
1903 
          GLB <= transport CLKB_ipd after CLKB_2_GLB_bypass0_dly;
1904 
          YB  <= 'X';
1905 
        elsif ( ( 1 = OBMUX_config ) or ( 3 = OBMUX_config ) ) then
1906 
          GLB <= transport 'X' after CLKA_2_GLB_dly;
1907 
          YB  <= transport 'X' after CLKA_2_YB_dly;
1908 
          assert ( not OBMUX_config'event )
1909 
            report "WARNING: Illegal OBMUX configuration."
1910 
            severity warning;
1911 
        else
1912 
          GLB <= transport BOUT after CLKA_2_GLB_dly;
1913 
          YB  <= transport BOUT after CLKA_2_YB_dly;
1914 
        end if;
1915 
    end process Boutputs;
1916 
 
1917 
    Coutputs: process ( COUT, CLKC_ipd, OCMUX_config )
1918 
    begin
1919 
        if ( 0 = OCMUX_config ) then
1920 
          GLC <= transport CLKC_ipd after CLKC_2_GLC_bypass0_dly;
1921 
          YC  <= 'X';
1922 
        elsif ( ( 1 = OCMUX_config ) or ( 3 = OCMUX_config ) ) then
1923 
          GLC <= transport 'X' after CLKA_2_GLC_dly;
1924 
          YC  <= transport 'X' after CLKA_2_YC_dly;
1925 
          assert ( not OCMUX_config'event )
1926 
            report "WARNING: Illegal OCMUX configuration."
1927 
            severity warning;
1928 
        else
1929 
          GLC <= transport COUT after CLKA_2_GLC_dly;
1930 
          YC  <= transport COUT after CLKA_2_YC_dly;
1931 
        end if;
1932 
    end process Coutputs;
1933 
 
1934 
  end VITAL_ACT;
1935 
 
1936 
 
1937 
library IEEE;
1938 
use IEEE.std_logic_1164.all;
1939 
library IEEE;
1940 
use IEEE.VITAL_Timing.all;
1941 
 
1942 
-- entity declaration --
1943 
 entity PLL is
1944 
  generic(
1945 
    VCOFREQUENCY      :  Real    := 0.0;
1946 
    f_CLKA_LOCK       :  Integer := 3; -- Number of CLKA pulses after which LOCK is raised
1947 
 
1948 
    TimingChecksOn    :  Boolean          := True;
1949 
    InstancePath      :  String           := "*";
1950 
    Xon               :  Boolean          := False;
1951 
    MsgOn             :  Boolean          := True;
1952 
 
1953 
    tipd_CLKA         :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1954 
    tipd_EXTFB        :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1955 
    tipd_POWERDOWN    :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1956 
    tipd_OADIV0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1957 
    tipd_OADIV1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1958 
    tipd_OADIV2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1959 
    tipd_OADIV3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1960 
    tipd_OADIV4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1961 
    tipd_OAMUX0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1962 
    tipd_OAMUX1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1963 
    tipd_OAMUX2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1964 
    tipd_DLYGLA0      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1965 
    tipd_DLYGLA1      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1966 
    tipd_DLYGLA2      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1967 
    tipd_DLYGLA3      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1968 
    tipd_DLYGLA4      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1969 
    tipd_OBDIV0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1970 
    tipd_OBDIV1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1971 
    tipd_OBDIV2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1972 
    tipd_OBDIV3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1973 
    tipd_OBDIV4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1974 
    tipd_OBMUX0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1975 
    tipd_OBMUX1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1976 
    tipd_OBMUX2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1977 
    tipd_DLYYB0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1978 
    tipd_DLYYB1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1979 
    tipd_DLYYB2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1980 
    tipd_DLYYB3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1981 
    tipd_DLYYB4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1982 
    tipd_DLYGLB0      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1983 
    tipd_DLYGLB1      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1984 
    tipd_DLYGLB2      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1985 
    tipd_DLYGLB3      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1986 
    tipd_DLYGLB4      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1987 
    tipd_OCDIV0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1988 
    tipd_OCDIV1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1989 
    tipd_OCDIV2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1990 
    tipd_OCDIV3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1991 
    tipd_OCDIV4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1992 
    tipd_OCMUX0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1993 
    tipd_OCMUX1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1994 
    tipd_OCMUX2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1995 
    tipd_DLYYC0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1996 
    tipd_DLYYC1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1997 
    tipd_DLYYC2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1998 
    tipd_DLYYC3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
1999 
    tipd_DLYYC4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2000 
    tipd_DLYGLC0      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2001 
    tipd_DLYGLC1      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2002 
    tipd_DLYGLC2      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2003 
    tipd_DLYGLC3      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2004 
    tipd_DLYGLC4      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2005 
    tipd_FINDIV0      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2006 
    tipd_FINDIV1      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2007 
    tipd_FINDIV2      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2008 
    tipd_FINDIV3      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2009 
    tipd_FINDIV4      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2010 
    tipd_FINDIV5      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2011 
    tipd_FINDIV6      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2012 
    tipd_FBDIV0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2013 
    tipd_FBDIV1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2014 
    tipd_FBDIV2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2015 
    tipd_FBDIV3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2016 
    tipd_FBDIV4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2017 
    tipd_FBDIV5       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2018 
    tipd_FBDIV6       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2019 
    tipd_FBDLY0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2020 
    tipd_FBDLY1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2021 
    tipd_FBDLY2       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2022 
    tipd_FBDLY3       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2023 
    tipd_FBDLY4       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2024 
    tipd_FBSEL0       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2025 
    tipd_FBSEL1       :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2026 
    tipd_XDLYSEL      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2027 
    tipd_VCOSEL0      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2028 
    tipd_VCOSEL1      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2029 
    tipd_VCOSEL2      :  VitalDelayType01 := ( 0.000 ns, 0.000 ns );
2030 
 
2031 
    tpd_CLKA_GLA      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2032 
    tpd_EXTFB_GLA     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2033 
    tpd_POWERDOWN_GLA :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2034 
    tpd_CLKA_GLB      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2035 
    tpd_EXTFB_GLB     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2036 
    tpd_POWERDOWN_GLB :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2037 
    tpd_CLKA_GLC      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2038 
    tpd_EXTFB_GLC     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2039 
    tpd_POWERDOWN_GLC :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2040 
    tpd_CLKA_YB       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2041 
    tpd_EXTFB_YB      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2042 
    tpd_POWERDOWN_YB  :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2043 
    tpd_CLKA_YC       :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2044 
    tpd_EXTFB_YC      :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2045 
    tpd_POWERDOWN_YC  :  VitalDelayType01 := ( 0.100 ns, 0.100 ns );
2046 
    tpd_CLKA_LOCK     :  VitalDelayType01 := ( 0.100 ns, 0.100 ns )
2047 
   );
2048 
 
2049 
  port (
2050 
    CLKA         : in    std_ulogic;
2051 
    EXTFB        : in    std_ulogic;
2052 
    POWERDOWN    : in    std_ulogic;
2053 
    OADIV0       : in    std_ulogic;
2054 
    OADIV1       : in    std_ulogic;
2055 
    OADIV2       : in    std_ulogic;
2056 
    OADIV3       : in    std_ulogic;
2057 
    OADIV4       : in    std_ulogic;
2058 
    OAMUX0       : in    std_ulogic;
2059 
    OAMUX1       : in    std_ulogic;
2060 
    OAMUX2       : in    std_ulogic;
2061 
    DLYGLA0      : in    std_ulogic;
2062 
    DLYGLA1      : in    std_ulogic;
2063 
    DLYGLA2      : in    std_ulogic;
2064 
    DLYGLA3      : in    std_ulogic;
2065 
    DLYGLA4      : in    std_ulogic;
2066 
    OBDIV0       : in    std_ulogic;
2067 
    OBDIV1       : in    std_ulogic;
2068 
    OBDIV2       : in    std_ulogic;
2069 
    OBDIV3       : in    std_ulogic;
2070 
    OBDIV4       : in    std_ulogic;
2071 
    OBMUX0       : in    std_ulogic;
2072 
    OBMUX1       : in    std_ulogic;
2073 
    OBMUX2       : in    std_ulogic;
2074 
    DLYYB0       : in    std_ulogic;
2075 
    DLYYB1       : in    std_ulogic;
2076 
    DLYYB2       : in    std_ulogic;
2077 
    DLYYB3       : in    std_ulogic;
2078 
    DLYYB4       : in    std_ulogic;
2079 
    DLYGLB0      : in    std_ulogic;
2080 
    DLYGLB1      : in    std_ulogic;
2081 
    DLYGLB2      : in    std_ulogic;
2082 
    DLYGLB3      : in    std_ulogic;
2083 
    DLYGLB4      : in    std_ulogic;
2084 
    OCDIV0       : in    std_ulogic;
2085 
    OCDIV1       : in    std_ulogic;
2086 
    OCDIV2       : in    std_ulogic;
2087 
    OCDIV3       : in    std_ulogic;
2088 
    OCDIV4       : in    std_ulogic;
2089 
    OCMUX0       : in    std_ulogic;
2090 
    OCMUX1       : in    std_ulogic;
2091 
    OCMUX2       : in    std_ulogic;
2092 
    DLYYC0       : in    std_ulogic;
2093 
    DLYYC1       : in    std_ulogic;
2094 
    DLYYC2       : in    std_ulogic;
2095 
    DLYYC3       : in    std_ulogic;
2096 
    DLYYC4       : in    std_ulogic;
2097 
    DLYGLC0      : in    std_ulogic;
2098 
    DLYGLC1      : in    std_ulogic;
2099 
    DLYGLC2      : in    std_ulogic;
2100 
    DLYGLC3      : in    std_ulogic;
2101 
    DLYGLC4      : in    std_ulogic;
2102 
    FINDIV0      : in    std_ulogic;
2103 
    FINDIV1      : in    std_ulogic;
2104 
    FINDIV2      : in    std_ulogic;
2105 
    FINDIV3      : in    std_ulogic;
2106 
    FINDIV4      : in    std_ulogic;
2107 
    FINDIV5      : in    std_ulogic;
2108 
    FINDIV6      : in    std_ulogic;
2109 
    FBDIV0       : in    std_ulogic;
2110 
    FBDIV1       : in    std_ulogic;
2111 
    FBDIV2       : in    std_ulogic;
2112 
    FBDIV3       : in    std_ulogic;
2113 
    FBDIV4       : in    std_ulogic;
2114 
    FBDIV5       : in    std_ulogic;
2115 
    FBDIV6       : in    std_ulogic;
2116 
    FBDLY0       : in    std_ulogic;
2117 
    FBDlY1       : in    std_ulogic;
2118 
    FBDLY2       : in    std_ulogic;
2119 
    FBDLY3       : in    std_ulogic;
2120 
    FBDlY4       : in    std_ulogic;
2121 
    FBSEL0       : in    std_ulogic;
2122 
    FBSEL1       : in    std_ulogic;
2123 
    XDLYSEL      : in    std_ulogic;
2124 
    VCOSEL0      : in    std_ulogic;
2125 
    VCOSEL1      : in    std_ulogic;
2126 
    VCOSEL2      : in    std_ulogic;
2127 
    GLA          : out   std_ulogic;
2128 
    LOCK         : out   std_ulogic;
2129 
    GLB          : out   std_ulogic;
2130 
    YB           : out   std_ulogic;
2131 
    GLC          : out   std_ulogic;
2132 
    YC           : out   std_ulogic
2133 
   );
2134 
 
2135 
  attribute VITAL_LEVEL0 of PLL : entity is TRUE;
2136 
end PLL;
2137 
 
2138 
-- architecture body --
2139 
library IEEE;
2140 
use IEEE.VITAL_Primitives.all;
2141 
library proasic3;
2142 
use proasic3.components.all;
2143 
 
2144 
architecture VITAL_ACT of PLL is
2145 
attribute VITAL_LEVEL1 of VITAL_ACT : architecture is FALSE;
2146 
 
2147 
  signal CLKA_ipd               : std_ulogic;
2148 
  signal EXTFB_ipd              : std_ulogic;
2149 
  signal POWERDOWN_ipd          : std_ulogic;
2150 
  signal OADIV0_ipd             : std_ulogic;
2151 
  signal OADIV1_ipd             : std_ulogic;
2152 
  signal OADIV2_ipd             : std_ulogic;
2153 
  signal OADIV3_ipd             : std_ulogic;
2154 
  signal OADIV4_ipd             : std_ulogic;
2155 
  signal OAMUX0_ipd             : std_ulogic;
2156 
  signal OAMUX1_ipd             : std_ulogic;
2157 
  signal OAMUX2_ipd             : std_ulogic;
2158 
  signal DLYGLA0_ipd            : std_ulogic;
2159 
  signal DLYGLA1_ipd            : std_ulogic;
2160 
  signal DLYGLA2_ipd            : std_ulogic;
2161 
  signal DLYGLA3_ipd            : std_ulogic;
2162 
  signal DLYGLA4_ipd            : std_ulogic;
2163 
  signal OBDIV0_ipd             : std_ulogic;
2164 
  signal OBDIV1_ipd             : std_ulogic;
2165 
  signal OBDIV2_ipd             : std_ulogic;
2166 
  signal OBDIV3_ipd             : std_ulogic;
2167 
  signal OBDIV4_ipd             : std_ulogic;
2168 
  signal OBMUX0_ipd             : std_ulogic;
2169 
  signal OBMUX1_ipd             : std_ulogic;
2170 
  signal OBMUX2_ipd             : std_ulogic;
2171 
  signal DLYYB0_ipd             : std_ulogic;
2172 
  signal DLYYB1_ipd             : std_ulogic;
2173 
  signal DLYYB2_ipd             : std_ulogic;
2174 
  signal DLYYB3_ipd             : std_ulogic;
2175 
  signal DLYYB4_ipd             : std_ulogic;
2176 
  signal DLYGLB0_ipd            : std_ulogic;
2177 
  signal DLYGLB1_ipd            : std_ulogic;
2178 
  signal DLYGLB2_ipd            : std_ulogic;
2179 
  signal DLYGLB3_ipd            : std_ulogic;
2180 
  signal DLYGLB4_ipd            : std_ulogic;
2181 
  signal OCDIV0_ipd             : std_ulogic;
2182 
  signal OCDIV1_ipd             : std_ulogic;
2183 
  signal OCDIV2_ipd             : std_ulogic;
2184 
  signal OCDIV3_ipd             : std_ulogic;
2185 
  signal OCDIV4_ipd             : std_ulogic;
2186 
  signal OCMUX0_ipd             : std_ulogic;
2187 
  signal OCMUX1_ipd             : std_ulogic;
2188 
  signal OCMUX2_ipd             : std_ulogic;
2189 
  signal DLYYC0_ipd             : std_ulogic;
2190 
  signal DLYYC1_ipd             : std_ulogic;
2191 
  signal DLYYC2_ipd             : std_ulogic;
2192 
  signal DLYYC3_ipd             : std_ulogic;
2193 
  signal DLYYC4_ipd             : std_ulogic;
2194 
  signal DLYGLC0_ipd            : std_ulogic;
2195 
  signal DLYGLC1_ipd            : std_ulogic;
2196 
  signal DLYGLC2_ipd            : std_ulogic;
2197 
  signal DLYGLC3_ipd            : std_ulogic;
2198 
  signal DLYGLC4_ipd            : std_ulogic;
2199 
  signal FINDIV0_ipd            : std_ulogic;
2200 
  signal FINDIV1_ipd            : std_ulogic;
2201 
  signal FINDIV2_ipd            : std_ulogic;
2202 
  signal FINDIV3_ipd            : std_ulogic;
2203 
  signal FINDIV4_ipd            : std_ulogic;
2204 
  signal FINDIV5_ipd            : std_ulogic;
2205 
  signal FINDIV6_ipd            : std_ulogic;
2206 
  signal FBDIV0_ipd             : std_ulogic;
2207 
  signal FBDIV1_ipd             : std_ulogic;
2208 
  signal FBDIV2_ipd             : std_ulogic;
2209 
  signal FBDIV3_ipd             : std_ulogic;
2210 
  signal FBDIV4_ipd             : std_ulogic;
2211 
  signal FBDIV5_ipd             : std_ulogic;
2212 
  signal FBDIV6_ipd             : std_ulogic;
2213 
  signal FBDLY0_ipd             : std_ulogic;
2214 
  signal FBDlY1_ipd             : std_ulogic;
2215 
  signal FBDLY2_ipd             : std_ulogic;
2216 
  signal FBDLY3_ipd             : std_ulogic;
2217 
  signal FBDlY4_ipd             : std_ulogic;
2218 
  signal FBSEL0_ipd             : std_ulogic;
2219 
  signal FBSEL1_ipd             : std_ulogic;
2220 
  signal XDLYSEL_ipd            : std_ulogic;
2221 
  signal VCOSEL0_ipd            : std_ulogic;
2222 
  signal VCOSEL1_ipd            : std_ulogic;
2223 
  signal VCOSEL2_ipd            : std_ulogic;
2224 
 
2225 
  signal GND                    : std_logic := '0';
2226 
  signal UNUSED                 : std_logic := 'X';
2227 
 
2228 
  component PLLPRIM
2229 
    generic (
2230 
              VCOFREQUENCY :  Real;
2231 
              f_CLKA_LOCK  :  Integer
2232 
            );
2233 
    port (
2234 
           DYNSYNC      : in    std_ulogic;
2235 
           CLKA         : in    std_ulogic;
2236 
           EXTFB        : in    std_ulogic;
2237 
           POWERDOWN    : in    std_ulogic;
2238 
           CLKB         : in    std_ulogic;
2239 
           CLKC         : in    std_ulogic;
2240 
           OADIVRST     : in    std_ulogic;
2241 
           OADIVHALF    : in    std_ulogic;
2242 
           OADIV0       : in    std_ulogic;
2243 
           OADIV1       : in    std_ulogic;
2244 
           OADIV2       : in    std_ulogic;
2245 
           OADIV3       : in    std_ulogic;
2246 
           OADIV4       : in    std_ulogic;
2247 
           OAMUX0       : in    std_ulogic;
2248 
           OAMUX1       : in    std_ulogic;
2249 
           OAMUX2       : in    std_ulogic;
2250 
           DLYGLA0      : in    std_ulogic;
2251 
           DLYGLA1      : in    std_ulogic;
2252 
           DLYGLA2      : in    std_ulogic;
2253 
           DLYGLA3      : in    std_ulogic;
2254 
           DLYGLA4      : in    std_ulogic;
2255 
           OBDIVRST     : in    std_ulogic;
2256 
           OBDIVHALF    : in    std_ulogic;
2257 
           OBDIV0       : in    std_ulogic;
2258 
           OBDIV1       : in    std_ulogic;
2259 
           OBDIV2       : in    std_ulogic;
2260 
           OBDIV3       : in    std_ulogic;
2261 
           OBDIV4       : in    std_ulogic;
2262 
           OBMUX0       : in    std_ulogic;
2263 
           OBMUX1       : in    std_ulogic;
2264 
           OBMUX2       : in    std_ulogic;
2265 
           DLYYB0       : in    std_ulogic;
2266 
           DLYYB1       : in    std_ulogic;
2267 
           DLYYB2       : in    std_ulogic;
2268 
           DLYYB3       : in    std_ulogic;
2269 
           DLYYB4       : in    std_ulogic;
2270 
           DLYGLB0      : in    std_ulogic;
2271 
           DLYGLB1      : in    std_ulogic;
2272 
           DLYGLB2      : in    std_ulogic;
2273 
           DLYGLB3      : in    std_ulogic;
2274 
           DLYGLB4      : in    std_ulogic;
2275 
           OCDIVRST     : in    std_ulogic;
2276 
           OCDIVHALF    : in    std_ulogic;
2277 
           OCDIV0       : in    std_ulogic;
2278 
           OCDIV1       : in    std_ulogic;
2279 
           OCDIV2       : in    std_ulogic;
2280 
           OCDIV3       : in    std_ulogic;
2281 
           OCDIV4       : in    std_ulogic;
2282 
           OCMUX0       : in    std_ulogic;
2283 
           OCMUX1       : in    std_ulogic;
2284 
           OCMUX2       : in    std_ulogic;
2285 
           DLYYC0       : in    std_ulogic;
2286 
           DLYYC1       : in    std_ulogic;
2287 
           DLYYC2       : in    std_ulogic;
2288 
           DLYYC3       : in    std_ulogic;
2289 
           DLYYC4       : in    std_ulogic;
2290 
           DLYGLC0      : in    std_ulogic;
2291 
           DLYGLC1      : in    std_ulogic;
2292 
           DLYGLC2      : in    std_ulogic;
2293 
           DLYGLC3      : in    std_ulogic;
2294 
           DLYGLC4      : in    std_ulogic;
2295 
           FINDIV0      : in    std_ulogic;
2296 
           FINDIV1      : in    std_ulogic;
2297 
           FINDIV2      : in    std_ulogic;
2298 
           FINDIV3      : in    std_ulogic;
2299 
           FINDIV4      : in    std_ulogic;
2300 
           FINDIV5      : in    std_ulogic;
2301 
           FINDIV6      : in    std_ulogic;
2302 
           FBDIV0       : in    std_ulogic;
2303 
           FBDIV1       : in    std_ulogic;
2304 
           FBDIV2       : in    std_ulogic;
2305 
           FBDIV3       : in    std_ulogic;
2306 
           FBDIV4       : in    std_ulogic;
2307 
           FBDIV5       : in    std_ulogic;
2308 
           FBDIV6       : in    std_ulogic;
2309 
           FBDLY0       : in    std_ulogic;
2310 
           FBDlY1       : in    std_ulogic;
2311 
           FBDLY2       : in    std_ulogic;
2312 
           FBDLY3       : in    std_ulogic;
2313 
           FBDlY4       : in    std_ulogic;
2314 
           FBSEL0       : in    std_ulogic;
2315 
           FBSEL1       : in    std_ulogic;
2316 
           XDLYSEL      : in    std_ulogic;
2317 
           VCOSEL0      : in    std_ulogic;
2318 
           VCOSEL1      : in    std_ulogic;
2319 
           VCOSEL2      : in    std_ulogic;
2320 
           GLA          : out   std_ulogic;
2321 
           LOCK         : out   std_ulogic;
2322 
           GLB          : out   std_ulogic;
2323 
           YB           : out   std_ulogic;
2324 
           GLC          : out   std_ulogic;
2325 
           YC           : out   std_ulogic
2326 
         );
2327 
  end component;
2328 
 
2329 
  begin
2330 
 
2331 
    ---------------------
2332 
    --  INPUT PATH DELAYs
2333 
    ---------------------
2334 
    WireDelay : block
2335 
 
2336 
    begin
2337 
 
2338 
      VitalWireDelay ( CLKA_ipd,      CLKA,      tipd_CLKA );
2339 
      VitalWireDelay ( EXTFB_ipd,     EXTFB,     tipd_EXTFB );
2340 
      VitalWireDelay ( POWERDOWN_ipd, POWERDOWN, tipd_POWERDOWN );
2341 
      VitalWireDelay ( OADIV0_ipd,    OADIV0,    tipd_OADIV0 );
2342 
      VitalWireDelay ( OADIV1_ipd,    OADIV1,    tipd_OADIV1 );
2343 
      VitalWireDelay ( OADIV2_ipd,    OADIV2,    tipd_OADIV2 );
2344 
      VitalWireDelay ( OADIV3_ipd,    OADIV3,    tipd_OADIV3 );
2345 
      VitalWireDelay ( OADIV4_ipd,    OADIV4,    tipd_OADIV4 );
2346 
      VitalWireDelay ( OAMUX0_ipd,    OAMUX0,    tipd_OAMUX0 );
2347 
      VitalWireDelay ( OAMUX1_ipd,    OAMUX1,    tipd_OAMUX1 );
2348 
      VitalWireDelay ( OAMUX2_ipd,    OAMUX2,    tipd_OAMUX2 );
2349 
      VitalWireDelay ( DLYGLA0_ipd,   DLYGLA0,   tipd_DLYGLA0 );
2350 
      VitalWireDelay ( DLYGLA1_ipd,   DLYGLA1,   tipd_DLYGLA1 );
2351 
      VitalWireDelay ( DLYGLA2_ipd,   DLYGLA2,   tipd_DLYGLA2 );
2352 
      VitalWireDelay ( DLYGLA3_ipd,   DLYGLA3,   tipd_DLYGLA3 );
2353 
      VitalWireDelay ( DLYGLA4_ipd,   DLYGLA4,   tipd_DLYGLA4 );
2354 
      VitalWireDelay ( OBDIV0_ipd,    OBDIV0,    tipd_OBDIV0 );
2355 
      VitalWireDelay ( OBDIV1_ipd,    OBDIV1,    tipd_OBDIV1 );
2356 
      VitalWireDelay ( OBDIV2_ipd,    OBDIV2,    tipd_OBDIV2 );
2357 
      VitalWireDelay ( OBDIV3_ipd,    OBDIV3,    tipd_OBDIV3 );
2358 
      VitalWireDelay ( OBDIV4_ipd,    OBDIV4,    tipd_OBDIV4 );
2359 
      VitalWireDelay ( OBMUX0_ipd,    OBMUX0,    tipd_OBMUX0 );
2360 
      VitalWireDelay ( OBMUX1_ipd,    OBMUX1,    tipd_OBMUX1 );
2361 
      VitalWireDelay ( OBMUX2_ipd,    OBMUX2,    tipd_OBMUX2 );
2362 
      VitalWireDelay ( DLYYB0_ipd,    DLYYB0,    tipd_DLYYB0 );
2363 
      VitalWireDelay ( DLYYB1_ipd,    DLYYB1,    tipd_DLYYB1 );
2364 
      VitalWireDelay ( DLYYB2_ipd,    DLYYB2,    tipd_DLYYB2 );
2365 
      VitalWireDelay ( DLYYB3_ipd,    DLYYB3,    tipd_DLYYB3 );
2366 
      VitalWireDelay ( DLYYB4_ipd,    DLYYB4,    tipd_DLYYB4 );
2367 
      VitalWireDelay ( DLYGLB0_ipd,   DLYGLB0,   tipd_DLYGLB0 );
2368 
      VitalWireDelay ( DLYGLB1_ipd,   DLYGLB1,   tipd_DLYGLB1 );
2369 
      VitalWireDelay ( DLYGLB2_ipd,   DLYGLB2,   tipd_DLYGLB2 );
2370 
      VitalWireDelay ( DLYGLB3_ipd,   DLYGLB3,   tipd_DLYGLB3 );
2371 
      VitalWireDelay ( DLYGLB4_ipd,   DLYGLB4,   tipd_DLYGLB4 );
2372 
      VitalWireDelay ( OCDIV0_ipd,    OCDIV0,    tipd_OCDIV0 );
2373 
      VitalWireDelay ( OCDIV1_ipd,    OCDIV1,    tipd_OCDIV1 );
2374 
      VitalWireDelay ( OCDIV2_ipd,    OCDIV2,    tipd_OCDIV2 );
2375 
      VitalWireDelay ( OCDIV3_ipd,    OCDIV3,    tipd_OCDIV3 );
2376 
      VitalWireDelay ( OCDIV4_ipd,    OCDIV4,    tipd_OCDIV4 );
2377 
      VitalWireDelay ( OCMUX0_ipd,    OCMUX0,    tipd_OCMUX0 );
2378 
      VitalWireDelay ( OCMUX1_ipd,    OCMUX1,    tipd_OCMUX1 );
2379 
      VitalWireDelay ( OCMUX2_ipd,    OCMUX2,    tipd_OCMUX2 );
2380 
      VitalWireDelay ( DLYYC0_ipd,    DLYYC0,    tipd_DLYYC0 );
2381 
      VitalWireDelay ( DLYYC1_ipd,    DLYYC1,    tipd_DLYYC1 );
2382 
      VitalWireDelay ( DLYYC2_ipd,    DLYYC2,    tipd_DLYYC2 );
2383 
      VitalWireDelay ( DLYYC3_ipd,    DLYYC3,    tipd_DLYYC3 );
2384 
      VitalWireDelay ( DLYYC4_ipd,    DLYYC4,    tipd_DLYYC4 );
2385 
      VitalWireDelay ( DLYGLC0_ipd,   DLYGLC0,   tipd_DLYGLC0 );
2386 
      VitalWireDelay ( DLYGLC1_ipd,   DLYGLC1,   tipd_DLYGLC1 );
2387 
      VitalWireDelay ( DLYGLC2_ipd,   DLYGLC2,   tipd_DLYGLC2 );
2388 
      VitalWireDelay ( DLYGLC3_ipd,   DLYGLC3,   tipd_DLYGLC3 );
2389 
      VitalWireDelay ( DLYGLC4_ipd,   DLYGLC4,   tipd_DLYGLC4 );
2390 
      VitalWireDelay ( FINDIV0_ipd,   FINDIV0,   tipd_FINDIV0 );
2391 
      VitalWireDelay ( FINDIV1_ipd,   FINDIV1,   tipd_FINDIV1 );
2392 
      VitalWireDelay ( FINDIV2_ipd,   FINDIV2,   tipd_FINDIV2 );
2393 
      VitalWireDelay ( FINDIV3_ipd,   FINDIV3,   tipd_FINDIV3 );
2394 
      VitalWireDelay ( FINDIV4_ipd,   FINDIV4,   tipd_FINDIV4 );
2395 
      VitalWireDelay ( FINDIV5_ipd,   FINDIV5,   tipd_FINDIV5 );
2396 
      VitalWireDelay ( FINDIV6_ipd,   FINDIV6,   tipd_FINDIV6 );
2397 
      VitalWireDelay ( FBDIV0_ipd,    FBDIV0,    tipd_FBDIV0 );
2398 
      VitalWireDelay ( FBDIV1_ipd,    FBDIV1,    tipd_FBDIV1 );
2399 
      VitalWireDelay ( FBDIV2_ipd,    FBDIV2,    tipd_FBDIV2 );
2400 
      VitalWireDelay ( FBDIV3_ipd,    FBDIV3,    tipd_FBDIV3 );
2401 
      VitalWireDelay ( FBDIV4_ipd,    FBDIV4,    tipd_FBDIV4 );
2402 
      VitalWireDelay ( FBDIV5_ipd,    FBDIV5,    tipd_FBDIV5 );
2403 
      VitalWireDelay ( FBDIV6_ipd,    FBDIV6,    tipd_FBDIV6 );
2404 
      VitalWireDelay ( FBDLY0_ipd,    FBDLY0,    tipd_FBDLY0 );
2405 
      VitalWireDelay ( FBDLY1_ipd,    FBDLY1,    tipd_FBDLY1 );
2406 
      VitalWireDelay ( FBDLY2_ipd,    FBDLY2,    tipd_FBDLY2 );
2407 
      VitalWireDelay ( FBDLY3_ipd,    FBDLY3,    tipd_FBDLY3 );
2408 
      VitalWireDelay ( FBDLY4_ipd,    FBDLY4,    tipd_FBDLY4 );
2409 
      VitalWireDelay ( FBSEL0_ipd,    FBSEL0,    tipd_FBSEL0 );
2410 
      VitalWireDelay ( FBSEL1_ipd,    FBSEL1,    tipd_FBSEL1 );
2411 
      VitalWireDelay ( XDLYSEL_ipd,   XDLYSEL,   tipd_XDLYSEL );
2412 
      VitalWireDelay ( VCOSEL0_ipd,   VCOSEL0,   tipd_VCOSEL0 );
2413 
      VitalWireDelay ( VCOSEL1_ipd,   VCOSEL1,   tipd_VCOSEL1 );
2414 
      VitalWireDelay ( VCOSEL2_ipd,   VCOSEL2,   tipd_VCOSEL2 );
2415 
 
2416 
    end block WireDelay;
2417 
 
2418 
    P1: PLLPRIM
2419 
          generic map (
2420 
                        VCOFREQUENCY => VCOFREQUENCY,
2421 
                        f_CLKA_LOCK  => f_CLKA_LOCK
2422 
                      )
2423 
          port map    (
2424 
                        DYNSYNC      => GND,
2425 
                        CLKA         => CLKA_ipd,
2426 
                        EXTFB        => EXTFB_ipd,
2427 
                        POWERDOWN    => POWERDOWN_ipd,
2428 
                        CLKB         => UNUSED,
2429 
                        CLKC         => UNUSED,
2430 
                        OADIVRST     => GND,
2431 
                        OADIVHALF    => GND,
2432 
                        OADIV0       => OADIV0_ipd,
2433 
                        OADIV1       => OADIV1_ipd,
2434 
                        OADIV2       => OADIV2_ipd,
2435 
                        OADIV3       => OADIV3_ipd,
2436 
                        OADIV4       => OADIV4_ipd,
2437 
                        OAMUX0       => OAMUX0_ipd,
2438 
                        OAMUX1       => OAMUX1_ipd,
2439 
                        OAMUX2       => OAMUX2_ipd,
2440 
                        DLYGLA0      => DLYGLA0_ipd,
2441 
                        DLYGLA1      => DLYGLA1_ipd,
2442 
                        DLYGLA2      => DLYGLA2_ipd,
2443 
                        DLYGLA3      => DLYGLA3_ipd,
2444 
                        DLYGLA4      => DLYGLA4_ipd,
2445 
                        OBDIVRST     => GND,
2446 
                        OBDIVHALF    => GND,
2447 
                        OBDIV0       => OBDIV0_ipd,
2448 
                        OBDIV1       => OBDIV1_ipd,
2449 
                        OBDIV2       => OBDIV2_ipd,
2450 
                        OBDIV3       => OBDIV3_ipd,
2451 
                        OBDIV4       => OBDIV4_ipd,
2452 
                        OBMUX0       => OBMUX0_ipd,
2453 
                        OBMUX1       => OBMUX1_ipd,
2454 
                        OBMUX2       => OBMUX2_ipd,
2455 
                        DLYYB0       => DLYYB0_ipd,
2456 
                        DLYYB1       => DLYYB1_ipd,
2457 
                        DLYYB2       => DLYYB2_ipd,
2458 
                        DLYYB3       => DLYYB3_ipd,
2459 
                        DLYYB4       => DLYYB4_ipd,
2460 
                        DLYGLB0      => DLYGLB0_ipd,
2461 
                        DLYGLB1      => DLYGLB1_ipd,
2462 
                        DLYGLB2      => DLYGLB2_ipd,
2463 
                        DLYGLB3      => DLYGLB3_ipd,
2464 
                        DLYGLB4      => DLYGLB4_ipd,
2465 
                        OCDIVRST     => GND,
2466 
                        OCDIVHALF    => GND,
2467 
                        OCDIV0       => OCDIV0_ipd,
2468 
                        OCDIV1       => OCDIV1_ipd,
2469 
                        OCDIV2       => OCDIV2_ipd,
2470 
                        OCDIV3       => OCDIV3_ipd,
2471 
                        OCDIV4       => OCDIV4_ipd,
2472 
                        OCMUX0       => OCMUX0_ipd,
2473 
                        OCMUX1       => OCMUX1_ipd,
2474 
                        OCMUX2       => OCMUX2_ipd,
2475 
                        DLYYC0       => DLYYC0_ipd,
2476 
                        DLYYC1       => DLYYC1_ipd,
2477 
                        DLYYC2       => DLYYC2_ipd,
2478 
                        DLYYC3       => DLYYC3_ipd,
2479 
                        DLYYC4       => DLYYC4_ipd,
2480 
                        DLYGLC0      => DLYGLC0_ipd,
2481 
                        DLYGLC1      => DLYGLC1_ipd,
2482 
                        DLYGLC2      => DLYGLC2_ipd,
2483 
                        DLYGLC3      => DLYGLC3_ipd,
2484 
                        DLYGLC4      => DLYGLC4_ipd,
2485 
                        FINDIV0      => FINDIV0_ipd,
2486 
                        FINDIV1      => FINDIV1_ipd,
2487 
                        FINDIV2      => FINDIV2_ipd,
2488 
                        FINDIV3      => FINDIV3_ipd,
2489 
                        FINDIV4      => FINDIV4_ipd,
2490 
                        FINDIV5      => FINDIV5_ipd,
2491 
                        FINDIV6      => FINDIV6_ipd,
2492 
                        FBDIV0       => FBDIV0_ipd,
2493 
                        FBDIV1       => FBDIV1_ipd,
2494 
                        FBDIV2       => FBDIV2_ipd,
2495 
                        FBDIV3       => FBDIV3_ipd,
2496 
                        FBDIV4       => FBDIV4_ipd,
2497 
                        FBDIV5       => FBDIV5_ipd,
2498 
                        FBDIV6       => FBDIV6_ipd,
2499 
                        FBDLY0       => FBDLY0_ipd,
2500 
                        FBDlY1       => FBDlY1_ipd,
2501 
                        FBDLY2       => FBDLY2_ipd,
2502 
                        FBDLY3       => FBDLY3_ipd,
2503 
                        FBDlY4       => FBDlY4_ipd,
2504 
                        FBSEL0       => FBSEL0_ipd,
2505 
                        FBSEL1       => FBSEL1_ipd,
2506 
                        XDLYSEL      => XDLYSEL_ipd,
2507 
                        VCOSEL0      => VCOSEL0_ipd,
2508 
                        VCOSEL1      => VCOSEL1_ipd,
2509 
                        VCOSEL2      => VCOSEL2_ipd,
2510 
                        GLA          => GLA,
2511 
                        LOCK         => LOCK,
2512 
                        GLB          => GLB,
2513 
                        YB           => YB,
2514 
                        GLC          => GLC,
2515 
                        YC           => YC
2516 
                      );
2517 
  end VITAL_ACT;
2518 
 
2519 
 library IEEE;
2520 
 use IEEE.std_logic_1164.all;
2521 
 
2522 
 entity UJTAG is
2523 
   port(
2524 
      UTDO           :  in    STD_ULOGIC;
2525 
      TMS            :  in    STD_ULOGIC;
2526 
      TDI            :  in    STD_ULOGIC;
2527 
      TCK            :  in    STD_ULOGIC;
2528 
      TRSTB          :  in    STD_ULOGIC;
2529 
      UIREG0         :  out   STD_ULOGIC;
2530 
      UIREG1         :  out   STD_ULOGIC;
2531 
      UIREG2         :  out   STD_ULOGIC;
2532 
      UIREG3         :  out   STD_ULOGIC;
2533 
      UIREG4         :  out   STD_ULOGIC;
2534 
      UIREG5         :  out   STD_ULOGIC;
2535 
      UIREG6         :  out   STD_ULOGIC;
2536 
      UIREG7         :  out   STD_ULOGIC;
2537 
      UTDI           :  out   STD_ULOGIC;
2538 
      URSTB          :  out   STD_ULOGIC;
2539 
      UDRCK          :  out   STD_ULOGIC;
2540 
      UDRCAP         :  out   STD_ULOGIC;
2541 
      UDRSH          :  out   STD_ULOGIC;
2542 
      UDRUPD         :  out   STD_ULOGIC;
2543 
      TDO            :  out   STD_ULOGIC);
2544 
 end;
2545 
 
2546 
 library IEEE;
2547 
 use IEEE.std_logic_1164.all;
2548 
 
2549 
 architecture behav of UJTAG is
2550 
 begin
2551 
    UIREG0 <= '0';
2552 
    UIREG1 <= '0';
2553 
    UIREG2 <= '0';
2554 
    UIREG3 <= '0';
2555 
    UIREG4 <= '0';
2556 
    UIREG5 <= '0';
2557 
    UIREG6 <= '0';
2558 
    UIREG7 <= '0';
2559 
    UTDI   <= '0';
2560 
    URSTB  <= '0';
2561 
    UDRCK  <= '0';
2562 
    UDRCAP <= '0';
2563 
    UDRSH  <= '0';
2564 
    UDRUPD <= '0';
2565 
    TDO    <= '0';
2566 
 end;
2567 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.