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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: cycloneiii_ddr_phy
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-- File: cycloneiii_ddr_phy.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Description: DDR PHY for Altera FPGAs
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------------------------------------------------------------------------------
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LIBRARY cycloneiii;
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USE cycloneiii.all;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY altdqs_cyciii_adqs_n7i2 IS
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generic (width : integer := 2; period : string := "10000ps");
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PORT
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(
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dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
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dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
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dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
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dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
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dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
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dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
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inclk : IN STD_LOGIC := '0';
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oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
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outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
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outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
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);
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END altdqs_cyciii_adqs_n7i2;
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ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
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-- ATTRIBUTE synthesis_clearbox : boolean;
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-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
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SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
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SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
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SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
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SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
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SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
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SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
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SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
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SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
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SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
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SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
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SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
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SIGNAL dqs_update : STD_LOGIC;
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SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
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COMPONENT cycloneiii_dll
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GENERIC
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(
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DELAY_BUFFER_MODE : STRING := "low";
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DELAY_CHAIN_LENGTH : NATURAL := 12;
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DELAYCTRLOUT_MODE : STRING := "normal";
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INPUT_FREQUENCY : STRING;
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JITTER_REDUCTION : STRING := "false";
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OFFSETCTRLOUT_MODE : STRING := "static";
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SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
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SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
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SIM_VALID_LOCK : NATURAL := 5;
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SIM_VALID_LOCKCOUNT : NATURAL := 0;
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STATIC_DELAY_CTRL : NATURAL := 0;
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STATIC_OFFSET : STRING;
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USE_UPNDNIN : STRING := "false";
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USE_UPNDNINCLKENA : STRING := "false";
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lpm_type : STRING := "cycloneiii_dll"
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);
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PORT
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(
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addnsub : IN STD_LOGIC := '1';
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aload : IN STD_LOGIC := '0';
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clk : IN STD_LOGIC;
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delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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dqsupdate : OUT STD_LOGIC;
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offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
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offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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upndnin : IN STD_LOGIC := '0';
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upndninclkena : IN STD_LOGIC := '1';
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upndnout : OUT STD_LOGIC
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);
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END COMPONENT;
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COMPONENT cycloneiii_io
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GENERIC
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(
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BUS_HOLD : STRING := "false";
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DDIO_MODE : STRING := "none";
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DDIOINCLK_INPUT : STRING := "negated_inclk";
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DQS_CTRL_LATCHES_ENABLE : STRING := "false";
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DQS_DELAY_BUFFER_MODE : STRING := "none";
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DQS_EDGE_DETECT_ENABLE : STRING := "false";
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DQS_INPUT_FREQUENCY : STRING := "unused";
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DQS_OFFSETCTRL_ENABLE : STRING := "false";
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DQS_OUT_MODE : STRING := "none";
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DQS_PHASE_SHIFT : NATURAL := 0;
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EXTEND_OE_DISABLE : STRING := "false";
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GATED_DQS : STRING := "false";
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INCLK_INPUT : STRING := "normal";
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INPUT_ASYNC_RESET : STRING := "none";
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INPUT_POWER_UP : STRING := "low";
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INPUT_REGISTER_MODE : STRING := "none";
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INPUT_SYNC_RESET : STRING := "none";
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OE_ASYNC_RESET : STRING := "none";
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OE_POWER_UP : STRING := "low";
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OE_REGISTER_MODE : STRING := "none";
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OE_SYNC_RESET : STRING := "none";
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OPEN_DRAIN_OUTPUT : STRING := "false";
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OPERATION_MODE : STRING;
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OUTPUT_ASYNC_RESET : STRING := "none";
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OUTPUT_POWER_UP : STRING := "low";
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OUTPUT_REGISTER_MODE : STRING := "none";
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OUTPUT_SYNC_RESET : STRING := "none";
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SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
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SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
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SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
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TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
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TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
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lpm_type : STRING := "cycloneiii_io"
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);
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PORT
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(
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areset : IN STD_LOGIC := '0';
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combout : OUT STD_LOGIC;
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datain : IN STD_LOGIC := '0';
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ddiodatain : IN STD_LOGIC := '0';
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ddioinclk : IN STD_LOGIC := '0';
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ddioregout : OUT STD_LOGIC;
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delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
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dqsbusout : OUT STD_LOGIC;
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dqsupdateen : IN STD_LOGIC := '1';
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inclk : IN STD_LOGIC := '0';
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inclkena : IN STD_LOGIC := '1';
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linkin : IN STD_LOGIC := '0';
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linkout : OUT STD_LOGIC;
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oe : IN STD_LOGIC := '1';
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offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
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outclk : IN STD_LOGIC := '0';
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outclkena : IN STD_LOGIC := '1';
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padio : INOUT STD_LOGIC;
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regout : OUT STD_LOGIC;
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sreset : IN STD_LOGIC := '0';
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terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
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);
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END COMPONENT;
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BEGIN
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delay_ctrl <= wire_cyciii_dll1_delayctrlout;
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dll_delayctrlout <= delay_ctrl;
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dqinclk <= wire_cyciii_io2a_dqsbusout;
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dqs_update <= wire_cyciii_dll1_dqsupdate;
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dqsundelayedout <= wire_cyciii_io2a_combout;
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offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
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cyciii_dll1 : cycloneiii_dll
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GENERIC MAP (
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DELAY_BUFFER_MODE => "low",
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DELAY_CHAIN_LENGTH => 12,
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DELAYCTRLOUT_MODE => "normal",
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INPUT_FREQUENCY => period, --"10000ps",
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JITTER_REDUCTION => "false",
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OFFSETCTRLOUT_MODE => "static",
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SIM_LOOP_DELAY_INCREMENT => 132,
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SIM_LOOP_INTRINSIC_DELAY => 3840,
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SIM_VALID_LOCK => 1,
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SIM_VALID_LOCKCOUNT => 46,
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STATIC_OFFSET => "0",
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USE_UPNDNIN => "false",
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USE_UPNDNINCLKENA => "false"
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)
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PORT MAP (
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clk => inclk,
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delayctrlout => wire_cyciii_dll1_delayctrlout,
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dqsupdate => wire_cyciii_dll1_dqsupdate,
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offsetctrlout => wire_cyciii_dll1_offsetctrlout
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);
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wire_cyciii_io2a_datain <= dqs_datain_h;
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wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
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wire_cyciii_io2a_oe <= oe;
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wire_cyciii_io2a_outclk <= outclk;
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wire_cyciii_io2a_outclkena <= outclkena;
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loop0 : FOR i IN 0 TO width-1 GENERATE
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cyciii_io2a : cycloneiii_io
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GENERIC MAP (
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DDIO_MODE => "output",
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DQS_CTRL_LATCHES_ENABLE => "true",
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DQS_DELAY_BUFFER_MODE => "low",
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DQS_EDGE_DETECT_ENABLE => "false",
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DQS_INPUT_FREQUENCY => period, --"10000ps",
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DQS_OFFSETCTRL_ENABLE => "true",
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DQS_OUT_MODE => "delay_chain3",
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DQS_PHASE_SHIFT => 9000,
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EXTEND_OE_DISABLE => "false",
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GATED_DQS => "false",
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OE_ASYNC_RESET => "none",
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OE_POWER_UP => "low",
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OE_REGISTER_MODE => "register",
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OE_SYNC_RESET => "none",
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OPEN_DRAIN_OUTPUT => "false",
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OPERATION_MODE => "bidir",
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OUTPUT_ASYNC_RESET => "none",
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OUTPUT_POWER_UP => "low",
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OUTPUT_REGISTER_MODE => "register",
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OUTPUT_SYNC_RESET => "none",
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SIM_DQS_DELAY_INCREMENT => 22,
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SIM_DQS_INTRINSIC_DELAY => 960,
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SIM_DQS_OFFSET_INCREMENT => 11,
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TIE_OFF_OE_CLOCK_ENABLE => "false",
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TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
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)
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PORT MAP (
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combout => wire_cyciii_io2a_combout(i),
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datain => wire_cyciii_io2a_datain(i),
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ddiodatain => wire_cyciii_io2a_ddiodatain(i),
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delayctrlin => delay_ctrl,
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dqsbusout => wire_cyciii_io2a_dqsbusout(i),
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dqsupdateen => dqs_update,
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oe => wire_cyciii_io2a_oe(i),
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offsetctrlin => offset_ctrl,
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outclk => wire_cyciii_io2a_outclk(i),
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outclkena => wire_cyciii_io2a_outclkena(i),
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padio => dqs_padio(i)
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);
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END GENERATE loop0;
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238 |
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END RTL; --altdqs_cyciii_adqs_n7i2
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240 |
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241 |
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LIBRARY ieee;
|
242 |
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USE ieee.std_logic_1164.all;
|
243 |
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|
244 |
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ENTITY altdqs_cyciii IS
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245 |
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generic (width : integer := 2; period : string := "10000ps");
|
246 |
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PORT
|
247 |
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(
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248 |
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dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
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249 |
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dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
250 |
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inclk : IN STD_LOGIC ;
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251 |
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oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
252 |
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outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
253 |
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dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
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dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
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255 |
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dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
|
256 |
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dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
|
257 |
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);
|
258 |
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END;
|
259 |
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|
260 |
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|
261 |
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ARCHITECTURE RTL OF altdqs_cyciii IS
|
262 |
|
|
|
263 |
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-- ATTRIBUTE synthesis_clearbox: boolean;
|
264 |
|
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-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
|
265 |
|
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
|
266 |
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
|
267 |
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SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
|
268 |
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SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
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269 |
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SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
|
270 |
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|
271 |
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|
272 |
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|
273 |
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COMPONENT altdqs_cyciii_adqs_n7i2
|
274 |
|
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generic (width : integer := 2; period : string := "10000ps");
|
275 |
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PORT (
|
276 |
|
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outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
277 |
|
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dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
|
278 |
|
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outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
279 |
|
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oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
280 |
|
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dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
281 |
|
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inclk : IN STD_LOGIC ;
|
282 |
|
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dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
283 |
|
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dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
284 |
|
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dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
|
285 |
|
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dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
|
286 |
|
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);
|
287 |
|
|
END COMPONENT;
|
288 |
|
|
|
289 |
|
|
BEGIN
|
290 |
|
|
sub_wire3_bv(width-1 downto 0) <= (others => '1');
|
291 |
|
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sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
|
292 |
|
|
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
|
293 |
|
|
dqinclk <= not sub_wire1(width-1 downto 0);
|
294 |
|
|
dqsundelayedout <= sub_wire2(width-1 downto 0);
|
295 |
|
|
|
296 |
|
|
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
|
297 |
|
|
generic map (width, period)
|
298 |
|
|
PORT MAP (
|
299 |
|
|
outclk => outclk,
|
300 |
|
|
outclkena => sub_wire3,
|
301 |
|
|
oe => oe,
|
302 |
|
|
dqs_datain_h => dqs_datain_h,
|
303 |
|
|
inclk => inclk,
|
304 |
|
|
dqs_datain_l => dqs_datain_l,
|
305 |
|
|
dll_delayctrlout => sub_wire0,
|
306 |
|
|
dqinclk => sub_wire1,
|
307 |
|
|
dqsundelayedout => sub_wire2,
|
308 |
|
|
dqs_padio => dqs_padio
|
309 |
|
|
);
|
310 |
|
|
|
311 |
|
|
|
312 |
|
|
|
313 |
|
|
END RTL;
|
314 |
|
|
|
315 |
|
|
library ieee;
|
316 |
|
|
use ieee.std_logic_1164.all;
|
317 |
|
|
|
318 |
|
|
library grlib;
|
319 |
|
|
use grlib.stdlib.all;
|
320 |
|
|
library techmap;
|
321 |
|
|
use techmap.gencomp.all;
|
322 |
|
|
|
323 |
|
|
library altera_mf;
|
324 |
|
|
use altera_mf.altera_mf_components.all;
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
------------------------------------------------------------------
|
328 |
|
|
-- CYCLONEIII DDR PHY --------------------------------------------
|
329 |
|
|
------------------------------------------------------------------
|
330 |
|
|
|
331 |
|
|
entity cycloneiii_ddr_phy is
|
332 |
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
333 |
|
|
dbits : integer := 16; clk_mul : integer := 2 ;
|
334 |
|
|
clk_div : integer := 2);
|
335 |
|
|
|
336 |
|
|
port (
|
337 |
|
|
rst : in std_ulogic;
|
338 |
|
|
clk : in std_logic; -- input clock
|
339 |
|
|
clkout : out std_ulogic; -- system clock
|
340 |
|
|
lock : out std_ulogic; -- DCM locked
|
341 |
|
|
|
342 |
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
343 |
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
344 |
|
|
ddr_clk_fb_out : out std_logic;
|
345 |
|
|
ddr_clk_fb : in std_logic;
|
346 |
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
347 |
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
348 |
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
349 |
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
350 |
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
351 |
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
352 |
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
353 |
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
354 |
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
355 |
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
356 |
|
|
|
357 |
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
358 |
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
359 |
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
360 |
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
361 |
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
362 |
|
|
oen : in std_ulogic;
|
363 |
|
|
dqs : in std_ulogic;
|
364 |
|
|
dqsoen : in std_ulogic;
|
365 |
|
|
rasn : in std_ulogic;
|
366 |
|
|
casn : in std_ulogic;
|
367 |
|
|
wen : in std_ulogic;
|
368 |
|
|
csn : in std_logic_vector(1 downto 0);
|
369 |
|
|
cke : in std_logic_vector(1 downto 0)
|
370 |
|
|
);
|
371 |
|
|
|
372 |
|
|
end;
|
373 |
|
|
|
374 |
|
|
architecture rtl of cycloneiii_ddr_phy is
|
375 |
|
|
|
376 |
|
|
signal vcc, gnd, dqsn, oe, lockl : std_logic;
|
377 |
|
|
signal ddr_clk_fb_outr : std_ulogic;
|
378 |
|
|
signal ddr_clk_fbl, fbclk : std_ulogic;
|
379 |
|
|
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
|
380 |
|
|
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
|
381 |
|
|
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
|
382 |
|
|
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
|
383 |
|
|
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
|
384 |
|
|
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
|
385 |
|
|
signal locked, vlockl, ddrclkfbl : std_ulogic;
|
386 |
|
|
signal clk4, clk5 : std_logic;
|
387 |
|
|
|
388 |
|
|
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
|
389 |
|
|
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
|
390 |
|
|
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
|
391 |
|
|
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
|
392 |
|
|
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
|
393 |
|
|
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
|
394 |
|
|
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
395 |
|
|
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
396 |
|
|
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
397 |
|
|
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
398 |
|
|
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
|
399 |
|
|
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
|
400 |
|
|
signal dllrst : std_logic_vector(0 to 3);
|
401 |
|
|
signal dll0rst : std_logic_vector(0 to 3);
|
402 |
|
|
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
|
403 |
|
|
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
|
404 |
|
|
signal pclkout : std_logic_vector (5 downto 1);
|
405 |
|
|
signal ddr_clkin : std_logic_vector(0 to 2);
|
406 |
|
|
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
407 |
|
|
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
408 |
|
|
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
409 |
|
|
|
410 |
|
|
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
|
411 |
|
|
|
412 |
|
|
component altdqs_cyciii
|
413 |
|
|
generic (width : integer := 2; period : string := "10000ps");
|
414 |
|
|
PORT
|
415 |
|
|
(
|
416 |
|
|
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
417 |
|
|
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
418 |
|
|
inclk : IN STD_LOGIC ;
|
419 |
|
|
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
420 |
|
|
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
|
421 |
|
|
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
422 |
|
|
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
|
423 |
|
|
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
|
424 |
|
|
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
|
425 |
|
|
);
|
426 |
|
|
END component;
|
427 |
|
|
|
428 |
|
|
type phasevec is array (1 to 3) of string(1 to 4);
|
429 |
|
|
type phasevecarr is array (10 to 13) of phasevec;
|
430 |
|
|
|
431 |
|
|
constant phasearr : phasevecarr := (
|
432 |
|
|
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
|
433 |
|
|
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
|
434 |
|
|
|
435 |
|
|
type periodtype is array (10 to 13) of string(1 to 6);
|
436 |
|
|
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
|
437 |
|
|
begin
|
438 |
|
|
|
439 |
|
|
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
|
440 |
|
|
|
441 |
|
|
mclk <= clk;
|
442 |
|
|
-- clkout <= clk_270r;
|
443 |
|
|
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
|
444 |
|
|
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
|
445 |
|
|
clk0r <= clk_270r; clk90r <= clk_0r;
|
446 |
|
|
clk180r <= clk_90r; clk270r <= clk_180r;
|
447 |
|
|
|
448 |
|
|
dll : altpll
|
449 |
|
|
generic map (
|
450 |
|
|
intended_device_family => "CycloneIII",
|
451 |
|
|
operation_mode => "NORMAL",
|
452 |
|
|
inclk0_input_frequency => 1000000/MHz,
|
453 |
|
|
inclk1_input_frequency => 1000000/MHz,
|
454 |
|
|
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
|
455 |
|
|
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
|
456 |
|
|
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
|
457 |
|
|
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
|
458 |
|
|
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
|
459 |
|
|
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
|
460 |
|
|
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
|
461 |
|
|
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
|
462 |
|
|
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
|
463 |
|
|
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
|
464 |
|
|
)
|
465 |
|
|
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
|
466 |
|
|
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
|
467 |
|
|
clk(4) => clk4, clk(5) => clk5, locked => lockl);
|
468 |
|
|
|
469 |
|
|
rstdel : process (mclk, rst, lockl)
|
470 |
|
|
begin
|
471 |
|
|
if rst = '0' then dllrst <= (others => '1');
|
472 |
|
|
elsif rising_edge(mclk) then
|
473 |
|
|
dllrst <= dllrst(1 to 3) & '0';
|
474 |
|
|
end if;
|
475 |
|
|
end process;
|
476 |
|
|
|
477 |
|
|
rdel : if rstdelay /= 0 generate
|
478 |
|
|
rcnt : process (clk_0r)
|
479 |
|
|
variable cnt : std_logic_vector(15 downto 0);
|
480 |
|
|
variable vlock, co : std_ulogic;
|
481 |
|
|
begin
|
482 |
|
|
if rising_edge(clk_0r) then
|
483 |
|
|
co := cnt(15);
|
484 |
|
|
vlockl <= vlock;
|
485 |
|
|
if lockl = '0' then
|
486 |
|
|
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
|
487 |
|
|
else
|
488 |
|
|
if vlock = '0' then
|
489 |
|
|
cnt := cnt -1; vlock := cnt(15) and not co;
|
490 |
|
|
end if;
|
491 |
|
|
end if;
|
492 |
|
|
end if;
|
493 |
|
|
if lockl = '0' then
|
494 |
|
|
vlock := '0';
|
495 |
|
|
end if;
|
496 |
|
|
end process;
|
497 |
|
|
end generate;
|
498 |
|
|
|
499 |
|
|
locked <= lockl when rstdelay = 0 else vlockl;
|
500 |
|
|
lock <= locked;
|
501 |
|
|
|
502 |
|
|
-- Generate external DDR clock
|
503 |
|
|
|
504 |
|
|
-- fbclkpad : altddio_out generic map (width => 1)
|
505 |
|
|
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
|
506 |
|
|
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
|
507 |
|
|
|
508 |
|
|
ddrclocks : for i in 0 to 2 generate
|
509 |
|
|
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
510 |
|
|
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
|
511 |
|
|
outclock => clk90r, dataout(0) => ddr_clk(i));
|
512 |
|
|
|
513 |
|
|
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
514 |
|
|
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
|
515 |
|
|
outclock => clk90r, dataout(0) => ddr_clkb(i));
|
516 |
|
|
|
517 |
|
|
end generate;
|
518 |
|
|
|
519 |
|
|
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
520 |
|
|
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
|
521 |
|
|
outclock => clk0r, dataout => ddr_csb(1 downto 0));
|
522 |
|
|
|
523 |
|
|
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
524 |
|
|
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
|
525 |
|
|
outclock => clk0r, dataout => ddr_cke(1 downto 0));
|
526 |
|
|
|
527 |
|
|
ddrbanks : for i in 0 to 1 generate
|
528 |
|
|
ckel(i) <= cke(i) and locked;
|
529 |
|
|
end generate;
|
530 |
|
|
|
531 |
|
|
rasnpad : altddio_out generic map (width => 1,
|
532 |
|
|
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
533 |
|
|
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
|
534 |
|
|
outclock => clk0r, dataout(0) => ddr_rasb);
|
535 |
|
|
|
536 |
|
|
casnpad : altddio_out generic map (width => 1,
|
537 |
|
|
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
538 |
|
|
port map ( datain_h(0) => casn, datain_l(0) => casn,
|
539 |
|
|
outclock => clk0r, dataout(0) => ddr_casb);
|
540 |
|
|
|
541 |
|
|
wenpad : altddio_out generic map (width => 1,
|
542 |
|
|
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
543 |
|
|
port map ( datain_h(0) => wen, datain_l(0) => wen,
|
544 |
|
|
outclock => clk0r, dataout(0) => ddr_web);
|
545 |
|
|
|
546 |
|
|
dmpads : altddio_out generic map (width => dbits/8,
|
547 |
|
|
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
548 |
|
|
port map (
|
549 |
|
|
datain_h => dm(dbits/8*2-1 downto dbits/8),
|
550 |
|
|
datain_l => dm(dbits/8-1 downto 0),
|
551 |
|
|
outclock => clk0r, dataout => ddr_dm
|
552 |
|
|
);
|
553 |
|
|
|
554 |
|
|
bapads : altddio_out generic map (width => 2)
|
555 |
|
|
port map (
|
556 |
|
|
datain_h => ba, datain_l => ba,
|
557 |
|
|
outclock => clk0r, dataout => ddr_ba
|
558 |
|
|
);
|
559 |
|
|
|
560 |
|
|
addrpads : altddio_out generic map (width => 14)
|
561 |
|
|
port map (
|
562 |
|
|
datain_h => addr, datain_l => addr,
|
563 |
|
|
outclock => clk0r, dataout => ddr_ad
|
564 |
|
|
);
|
565 |
|
|
|
566 |
|
|
-- DQS generation
|
567 |
|
|
|
568 |
|
|
dqsnv <= (others => dqsn);
|
569 |
|
|
dqsoclk <= (others => clk90r);
|
570 |
|
|
|
571 |
|
|
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
|
572 |
|
|
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
|
573 |
|
|
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
|
574 |
|
|
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
|
575 |
|
|
dqsundelayedout => open );
|
576 |
|
|
|
577 |
|
|
-- Data bus
|
578 |
|
|
|
579 |
|
|
dqgen : for i in 0 to dbits/8-1 generate
|
580 |
|
|
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
|
581 |
|
|
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
|
582 |
|
|
port map (
|
583 |
|
|
datain_l => dqout(i*8+7 downto i*8),
|
584 |
|
|
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
|
585 |
|
|
inclock => dqinclk(i), --clk270r,
|
586 |
|
|
outclock => clk0r, oe => oe,
|
587 |
|
|
dataout_h => dqin(i*8+7 downto i*8),
|
588 |
|
|
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
|
589 |
|
|
padio => ddr_dq(i*8+7 downto i*8));
|
590 |
|
|
end generate;
|
591 |
|
|
|
592 |
|
|
dqsreg : process(clk180r)
|
593 |
|
|
begin
|
594 |
|
|
if rising_edge(clk180r) then
|
595 |
|
|
dqsn <= oe;
|
596 |
|
|
end if;
|
597 |
|
|
end process;
|
598 |
|
|
oereg : process(clk0r)
|
599 |
|
|
begin
|
600 |
|
|
if rising_edge(clk0r) then
|
601 |
|
|
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
|
602 |
|
|
end if;
|
603 |
|
|
end process;
|
604 |
|
|
|
605 |
|
|
end;
|