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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [allclkgen.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity:      libclk
-- File:        libclk.vhd
-- Author:      Jiri Gaisler - Gaisler Research
-- Description: Clock generator interface package
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
 
package allclkgen is
 
component clkgen_virtex
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    sdramen  : integer := 0;
    noclkfb  : integer := 0;
    pcien    : integer := 0;
    pcidll   : integer := 0;
    pcisysclk: integer := 0);
  port (
    clkin   : in  std_logic;
    pciclkin: in  std_logic;
    clk     : out std_logic;                    -- main clock
    clkn    : out std_logic;                    -- inverted main clock
    clk2x   : out std_logic;                    -- double clock
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type);
end component;
 
component clkgen_virtex2
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    sdramen  : integer := 0;
    noclkfb  : integer := 0;
    pcien    : integer := 0;
    pcidll   : integer := 0;
    pcisysclk: integer := 0;
    freq     : integer := 25000;
    clk2xen  : integer := 0;
    clksel   : integer := 0);             -- enable clock select         
  port (
    clkin   : in  std_logic;
    pciclkin: in  std_logic;
    clk     : out std_logic;                    -- main clock
    clkn    : out std_logic;                    -- inverted main clock
    clk2x   : out std_logic;                    -- double clock
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type;
    clk1xu  : out std_ulogic;                   -- unscaled clock
    clk2xu  : out std_ulogic);
end component;
 
component clkgen_spartan3
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    sdramen  : integer := 0;
    noclkfb  : integer := 0;
    pcien    : integer := 0;
    pcidll   : integer := 0;
    pcisysclk: integer := 0;
    freq     : integer := 25000;
    clk2xen  : integer := 0;
    clksel   : integer := 0);             -- enable clock select         
  port (
    clkin   : in  std_logic;
    pciclkin: in  std_logic;
    clk     : out std_logic;                    -- main clock
    clkn    : out std_logic;                    -- inverted main clock
    clk2x   : out std_logic;                    -- double clock
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type;
    clk1xu  : out std_ulogic;                   -- unscaled clock
    clk2xu  : out std_ulogic);
end component;
 
component clkgen_virtex5
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    sdramen  : integer := 0;
    noclkfb  : integer := 0;
    pcien    : integer := 0;
    pcidll   : integer := 0;
    pcisysclk: integer := 0;
    freq     : integer := 25000;
    clk2xen  : integer := 0;
    clksel   : integer := 0);             -- enable clock select         
  port (
    clkin   : in  std_logic;
    pciclkin: in  std_logic;
    clk     : out std_logic;                    -- main clock
    clkn    : out std_logic;                    -- inverted main clock
    clk2x   : out std_logic;                    -- double clock
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type;
    clk1xu  : out std_ulogic;                   -- unscaled clock
    clk2xu  : out std_ulogic);
end component;
 
component clkgen_axcelerator
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    sdramen  : integer := 0;
    sdinvclk : integer := 0;
    pcien    : integer := 0;
    pcidll   : integer := 0;
    pcisysclk: integer := 0);
  port (
    clkin   : in  std_logic;
    pciclkin: in  std_logic;
    clk     : out std_logic;                    -- main clock
    clkn    : out std_logic;                    -- inverted main clock
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type);
end component;
 
component clkgen_altera_mf
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    sdramen  : integer := 0;
    sdinvclk : integer := 0;
    pcien    : integer := 0;
    pcidll   : integer := 0;
    pcisysclk: integer := 0;
    freq     : integer := 25000;
    clk2xen  : integer := 0);
  port (
    clkin   : in  std_logic;
    pciclkin: in  std_logic;
    clk     : out std_logic;                    -- main clock
    clkn    : out std_logic;                    -- inverted main clock
    clk2x   : out std_logic;                    -- double clock    
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type);
end component;
 
component clkgen_cycloneiii
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    sdramen  : integer := 0;
    sdinvclk : integer := 0;
    pcien    : integer := 0;
    pcidll   : integer := 0;
    pcisysclk: integer := 0;
    freq     : integer := 25000;
    clk2xen  : integer := 0);
  port (
    clkin   : in  std_logic;
    pciclkin: in  std_logic;
    clk     : out std_logic;                    -- main clock
    clkn    : out std_logic;                    -- inverted main clock
    clk2x   : out std_logic;                    -- double clock    
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type);
end component;
 
component clkgen_stratixiii
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    sdramen  : integer := 0;
    sdinvclk : integer := 0;
    pcien    : integer := 0;
    pcidll   : integer := 0;
    pcisysclk: integer := 0;
    freq     : integer := 25000;
    clk2xen  : integer := 0);
  port (
    clkin   : in  std_logic;
    pciclkin: in  std_logic;
    clk     : out std_logic;                    -- main clock
    clkn    : out std_logic;                    -- inverted main clock
    clk2x   : out std_logic;                    -- double clock    
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type);
end component;
 
component clkgen_rh_lib18t
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1);
  port (
    rst     : in  std_logic;
    clkin   : in  std_logic;
    clk     : out std_logic;
    sdclk   : out std_logic;                    -- SDRAM clock
    clk2x   : out std_logic;
    clk4x   : out std_logic
    );
end component;
 
component clkmul_virtex2
  generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
  port (
    resetin : in  std_logic;
    clkin   : in  std_logic;
    clk     : out std_logic;
    resetout: out std_logic
  );
end component;
 
component clkand_unisim
  port(
    i      :  in  std_ulogic;
    en     :  in  std_ulogic;
    o      :  out std_ulogic
  );
end component;
 
component clkand_ut025crh
  port(
    i      :  in  std_ulogic;
    en     :  in  std_ulogic;
    o      :  out std_ulogic
  );
end component;
 
component clkmux_unisim
  port(
    i0, i1  :  in  std_ulogic;
    sel     :  in  std_ulogic;
    o       :  out std_ulogic
  );
end component;
 
  component altera_pll
    generic (
      clk_mul  : integer := 1;
      clk_div  : integer := 1;
      clk_freq : integer := 25000;
      clk2xen  : integer := 0;
      sdramen  : integer := 0
    );
    port (
      inclk0 : in  std_ulogic;
      c0     : out std_ulogic;
      c0_2x   : out std_ulogic;
      e0     : out std_ulogic;
      locked : out std_ulogic);
  end component;
 
  component clkgen_proasic3
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    clk_odiv : integer := 1;            -- output divider
    pcien    : integer := 0;
    pcisysclk: integer := 0;
    freq     : integer := 25000);       -- clock frequency in KHz
  port (
    clkin   : in  std_ulogic;
    pciclkin: in  std_ulogic;
    clk     : out std_ulogic;                   -- main clock
    sdclk   : out std_ulogic;                   -- SDRAM clock
    pciclk  : out std_ulogic;
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type);
  end component;
 
  component cyclone3_pll is
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    clk_freq : integer := 25000;
    clk2xen  : integer := 0;
    sdramen  : integer := 0
  );
  port (
    inclk0  : in  std_ulogic;
    c0      : out std_ulogic;
    c0_2x   : out std_ulogic;
    e0      : out std_ulogic;
    locked  : out std_ulogic);
  end component;
 
  component stratix3_pll
  generic (
    clk_mul  : integer := 1;
    clk_div  : integer := 1;
    clk_freq : integer := 25000;
    clk2xen  : integer := 0;
    sdramen  : integer := 0
  );
  port (
    inclk0  : in  std_ulogic;
    c0      : out std_ulogic;
    c0_2x   : out std_ulogic;
    e0      : out std_ulogic;
    locked  : out std_ulogic);
  end component;
 
  component clkgen_dare
  port (
    clkin   : in  std_logic;
    clk     : out std_logic;                    -- main clock
    clk2x   : out std_logic;                    -- 2x clock
    sdclk   : out std_logic;                    -- SDRAM clock
    pciclk  : out std_logic;                    -- PCI clock
    cgi     : in clkgen_in_type;
    cgo     : out clkgen_out_type;
    clk4x   : out std_logic;                    -- 4x clock
    clk1xu  : out std_logic;                    -- unscaled 1X clock
    clk2xu  : out std_logic);                   -- unscaled 2X clock
  end component;
end;

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [allclkgen.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Entity: libclk`
20			`-- File: libclk.vhd`
21			`-- Author: Jiri Gaisler - Gaisler Research`
22			`-- Description: Clock generator interface package`
23			`------------------------------------------------------------------------------`
24
25			`library ieee;`
26			`use ieee.std_logic_1164.all;`
27			`library techmap;`
28			`use techmap.gencomp.all;`
29
30			`package allclkgen is`
31
32			`component clkgen_virtex`
33			`generic (`
34			`clk_mul : integer := 1;`
35			`clk_div : integer := 1;`
36			`sdramen : integer := 0;`
37			`noclkfb : integer := 0;`
38			`pcien : integer := 0;`
39			`pcidll : integer := 0;`
40			`pcisysclk: integer := 0);`
41			`port (`
42			`clkin : in std_logic;`
43			`pciclkin: in std_logic;`
44			`clk : out std_logic; -- main clock`
45			`clkn : out std_logic; -- inverted main clock`
46			`clk2x : out std_logic; -- double clock`
47			`sdclk : out std_logic; -- SDRAM clock`
48			`pciclk : out std_logic; -- PCI clock`
49			`cgi : in clkgen_in_type;`
50			`cgo : out clkgen_out_type);`
51			`end component;`
52
53			`component clkgen_virtex2`
54			`generic (`
55			`clk_mul : integer := 1;`
56			`clk_div : integer := 1;`
57			`sdramen : integer := 0;`
58			`noclkfb : integer := 0;`
59			`pcien : integer := 0;`
60			`pcidll : integer := 0;`
61			`pcisysclk: integer := 0;`
62			`freq : integer := 25000;`
63			`clk2xen : integer := 0;`
64			`clksel : integer := 0); -- enable clock select`
65			`port (`
66			`clkin : in std_logic;`
67			`pciclkin: in std_logic;`
68			`clk : out std_logic; -- main clock`
69			`clkn : out std_logic; -- inverted main clock`
70			`clk2x : out std_logic; -- double clock`
71			`sdclk : out std_logic; -- SDRAM clock`
72			`pciclk : out std_logic; -- PCI clock`
73			`cgi : in clkgen_in_type;`
74			`cgo : out clkgen_out_type;`
75			`clk1xu : out std_ulogic; -- unscaled clock`
76			`clk2xu : out std_ulogic);`
77			`end component;`
78
79			`component clkgen_spartan3`
80			`generic (`
81			`clk_mul : integer := 1;`
82			`clk_div : integer := 1;`
83			`sdramen : integer := 0;`
84			`noclkfb : integer := 0;`
85			`pcien : integer := 0;`
86			`pcidll : integer := 0;`
87			`pcisysclk: integer := 0;`
88			`freq : integer := 25000;`
89			`clk2xen : integer := 0;`
90			`clksel : integer := 0); -- enable clock select`
91			`port (`
92			`clkin : in std_logic;`
93			`pciclkin: in std_logic;`
94			`clk : out std_logic; -- main clock`
95			`clkn : out std_logic; -- inverted main clock`
96			`clk2x : out std_logic; -- double clock`
97			`sdclk : out std_logic; -- SDRAM clock`
98			`pciclk : out std_logic; -- PCI clock`
99			`cgi : in clkgen_in_type;`
100			`cgo : out clkgen_out_type;`
101			`clk1xu : out std_ulogic; -- unscaled clock`
102			`clk2xu : out std_ulogic);`
103			`end component;`
104
105			`component clkgen_virtex5`
106			`generic (`
107			`clk_mul : integer := 1;`
108			`clk_div : integer := 1;`
109			`sdramen : integer := 0;`
110			`noclkfb : integer := 0;`
111			`pcien : integer := 0;`
112			`pcidll : integer := 0;`
113			`pcisysclk: integer := 0;`
114			`freq : integer := 25000;`
115			`clk2xen : integer := 0;`
116			`clksel : integer := 0); -- enable clock select`
117			`port (`
118			`clkin : in std_logic;`
119			`pciclkin: in std_logic;`
120			`clk : out std_logic; -- main clock`
121			`clkn : out std_logic; -- inverted main clock`
122			`clk2x : out std_logic; -- double clock`
123			`sdclk : out std_logic; -- SDRAM clock`
124			`pciclk : out std_logic; -- PCI clock`
125			`cgi : in clkgen_in_type;`
126			`cgo : out clkgen_out_type;`
127			`clk1xu : out std_ulogic; -- unscaled clock`
128			`clk2xu : out std_ulogic);`
129			`end component;`
130
131			`component clkgen_axcelerator`
132			`generic (`
133			`clk_mul : integer := 1;`
134			`clk_div : integer := 1;`
135			`sdramen : integer := 0;`
136			`sdinvclk : integer := 0;`
137			`pcien : integer := 0;`
138			`pcidll : integer := 0;`
139			`pcisysclk: integer := 0);`
140			`port (`
141			`clkin : in std_logic;`
142			`pciclkin: in std_logic;`
143			`clk : out std_logic; -- main clock`
144			`clkn : out std_logic; -- inverted main clock`
145			`sdclk : out std_logic; -- SDRAM clock`
146			`pciclk : out std_logic; -- PCI clock`
147			`cgi : in clkgen_in_type;`
148			`cgo : out clkgen_out_type);`
149			`end component;`
150
151			`component clkgen_altera_mf`
152			`generic (`
153			`clk_mul : integer := 1;`
154			`clk_div : integer := 1;`
155			`sdramen : integer := 0;`
156			`sdinvclk : integer := 0;`
157			`pcien : integer := 0;`
158			`pcidll : integer := 0;`
159			`pcisysclk: integer := 0;`
160			`freq : integer := 25000;`
161			`clk2xen : integer := 0);`
162			`port (`
163			`clkin : in std_logic;`
164			`pciclkin: in std_logic;`
165			`clk : out std_logic; -- main clock`
166			`clkn : out std_logic; -- inverted main clock`
167			`clk2x : out std_logic; -- double clock`
168			`sdclk : out std_logic; -- SDRAM clock`
169			`pciclk : out std_logic; -- PCI clock`
170			`cgi : in clkgen_in_type;`
171			`cgo : out clkgen_out_type);`
172			`end component;`
173
174			`component clkgen_cycloneiii`
175			`generic (`
176			`clk_mul : integer := 1;`
177			`clk_div : integer := 1;`
178			`sdramen : integer := 0;`
179			`sdinvclk : integer := 0;`
180			`pcien : integer := 0;`
181			`pcidll : integer := 0;`
182			`pcisysclk: integer := 0;`
183			`freq : integer := 25000;`
184			`clk2xen : integer := 0);`
185			`port (`
186			`clkin : in std_logic;`
187			`pciclkin: in std_logic;`
188			`clk : out std_logic; -- main clock`
189			`clkn : out std_logic; -- inverted main clock`
190			`clk2x : out std_logic; -- double clock`
191			`sdclk : out std_logic; -- SDRAM clock`
192			`pciclk : out std_logic; -- PCI clock`
193			`cgi : in clkgen_in_type;`
194			`cgo : out clkgen_out_type);`
195			`end component;`
196
197			`component clkgen_stratixiii`
198			`generic (`
199			`clk_mul : integer := 1;`
200			`clk_div : integer := 1;`
201			`sdramen : integer := 0;`
202			`sdinvclk : integer := 0;`
203			`pcien : integer := 0;`
204			`pcidll : integer := 0;`
205			`pcisysclk: integer := 0;`
206			`freq : integer := 25000;`
207			`clk2xen : integer := 0);`
208			`port (`
209			`clkin : in std_logic;`
210			`pciclkin: in std_logic;`
211			`clk : out std_logic; -- main clock`
212			`clkn : out std_logic; -- inverted main clock`
213			`clk2x : out std_logic; -- double clock`
214			`sdclk : out std_logic; -- SDRAM clock`
215			`pciclk : out std_logic; -- PCI clock`
216			`cgi : in clkgen_in_type;`
217			`cgo : out clkgen_out_type);`
218			`end component;`
219
220			`component clkgen_rh_lib18t`
221			`generic (`
222			`clk_mul : integer := 1;`
223			`clk_div : integer := 1);`
224			`port (`
225			`rst : in std_logic;`
226			`clkin : in std_logic;`
227			`clk : out std_logic;`
228			`sdclk : out std_logic; -- SDRAM clock`
229			`clk2x : out std_logic;`
230			`clk4x : out std_logic`
231			`);`
232			`end component;`
233
234			`component clkmul_virtex2`
235			`generic ( clk_mul : integer := 2 ; clk_div : integer := 2);`
236			`port (`
237			`resetin : in std_logic;`
238			`clkin : in std_logic;`
239			`clk : out std_logic;`
240			`resetout: out std_logic`
241			`);`
242			`end component;`
243
244			`component clkand_unisim`
245			`port(`
246			`i : in std_ulogic;`
247			`en : in std_ulogic;`
248			`o : out std_ulogic`
249			`);`
250			`end component;`
251
252			`component clkand_ut025crh`
253			`port(`
254			`i : in std_ulogic;`
255			`en : in std_ulogic;`
256			`o : out std_ulogic`
257			`);`
258			`end component;`
259
260			`component clkmux_unisim`
261			`port(`
262			`i0, i1 : in std_ulogic;`
263			`sel : in std_ulogic;`
264			`o : out std_ulogic`
265			`);`
266			`end component;`
267
268			`component altera_pll`
269			`generic (`
270			`clk_mul : integer := 1;`
271			`clk_div : integer := 1;`
272			`clk_freq : integer := 25000;`
273			`clk2xen : integer := 0;`
274			`sdramen : integer := 0`
275			`);`
276			`port (`
277			`inclk0 : in std_ulogic;`
278			`c0 : out std_ulogic;`
279			`c0_2x : out std_ulogic;`
280			`e0 : out std_ulogic;`
281			`locked : out std_ulogic);`
282			`end component;`
283
284			`component clkgen_proasic3`
285			`generic (`
286			`clk_mul : integer := 1;`
287			`clk_div : integer := 1;`
288			`clk_odiv : integer := 1; -- output divider`
289			`pcien : integer := 0;`
290			`pcisysclk: integer := 0;`
291			`freq : integer := 25000); -- clock frequency in KHz`
292			`port (`
293			`clkin : in std_ulogic;`
294			`pciclkin: in std_ulogic;`
295			`clk : out std_ulogic; -- main clock`
296			`sdclk : out std_ulogic; -- SDRAM clock`
297			`pciclk : out std_ulogic;`
298			`cgi : in clkgen_in_type;`
299			`cgo : out clkgen_out_type);`
300			`end component;`
301
302			`component cyclone3_pll is`
303			`generic (`
304			`clk_mul : integer := 1;`
305			`clk_div : integer := 1;`
306			`clk_freq : integer := 25000;`
307			`clk2xen : integer := 0;`
308			`sdramen : integer := 0`
309			`);`
310			`port (`
311			`inclk0 : in std_ulogic;`
312			`c0 : out std_ulogic;`
313			`c0_2x : out std_ulogic;`
314			`e0 : out std_ulogic;`
315			`locked : out std_ulogic);`
316			`end component;`
317
318			`component stratix3_pll`
319			`generic (`
320			`clk_mul : integer := 1;`
321			`clk_div : integer := 1;`
322			`clk_freq : integer := 25000;`
323			`clk2xen : integer := 0;`
324			`sdramen : integer := 0`
325			`);`
326			`port (`
327			`inclk0 : in std_ulogic;`
328			`c0 : out std_ulogic;`
329			`c0_2x : out std_ulogic;`
330			`e0 : out std_ulogic;`
331			`locked : out std_ulogic);`
332			`end component;`
333
334			`component clkgen_dare`
335			`port (`
336			`clkin : in std_logic;`
337			`clk : out std_logic; -- main clock`
338			`clk2x : out std_logic; -- 2x clock`
339			`sdclk : out std_logic; -- SDRAM clock`
340			`pciclk : out std_logic; -- PCI clock`
341			`cgi : in clkgen_in_type;`
342			`cgo : out clkgen_out_type;`
343			`clk4x : out std_logic; -- 4x clock`
344			`clk1xu : out std_logic; -- unscaled 1X clock`
345			`clk2xu : out std_logic); -- unscaled 2X clock`
346			`end component;`
347			`end;`