OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [allmem.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali 
------------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
3 
--  Copyright (C) 2003, Gaisler Research
4 
--
5 
--  This program is free software; you can redistribute it and/or modify
6 
--  it under the terms of the GNU General Public License as published by
7 
--  the Free Software Foundation; either version 2 of the License, or
8 
--  (at your option) any later version.
9 
--
10 
--  This program is distributed in the hope that it will be useful,
11 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
--  GNU General Public License for more details.
14 
--
15 
--  You should have received a copy of the GNU General Public License
16 
--  along with this program; if not, write to the Free Software
17 
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18 
-----------------------------------------------------------------------------
19 
-- Package:     allmem
20 
-- File:        allmem.vhd
21 
-- Author:      Jiri Gaisler Gaisler Research
22 
-- Description: All tech specific memories
23 
------------------------------------------------------------------------------
24 
 
25 
library ieee;
26 
use ieee.std_logic_1164.all;
27 
 
28 
package allmem is
29 
 
30 
-- AX & RTAX family
31 
 
32 
  component axcel_syncram
33 
  generic ( abits : integer := 10; dbits : integer := 8 );
34 
  port (
35 
    clk      : in std_ulogic;
36 
    address  : in std_logic_vector((abits -1) downto 0);
37 
    datain   : in std_logic_vector((dbits -1) downto 0);
38 
    dataout  : out std_logic_vector((dbits -1) downto 0);
39 
    enable   : in std_ulogic;
40 
    write    : in std_ulogic);
41 
  end component;
42 
 
43 
  component axcel_syncram_2p
44 
  generic ( abits : integer := 8; dbits : integer := 32);
45 
  port (
46 
    rclk  : in std_ulogic;
47 
    rena  : in std_ulogic;
48 
    raddr : in std_logic_vector (abits -1 downto 0);
49 
    dout  : out std_logic_vector (dbits -1 downto 0);
50 
    wclk  : in std_ulogic;
51 
    waddr : in std_logic_vector (abits -1 downto 0);
52 
    din   : in std_logic_vector (dbits -1 downto 0);
53 
    write : in std_ulogic);
54 
  end component;
55 
 
56 
-- Proasic + Proasicplus family
57 
 
58 
  component proasic_syncram
59 
  generic ( abits : integer := 10; dbits : integer := 8 );
60 
  port (
61 
    clk      : in std_ulogic;
62 
    address  : in std_logic_vector((abits -1) downto 0);
63 
    datain   : in std_logic_vector((dbits -1) downto 0);
64 
    dataout  : out std_logic_vector((dbits -1) downto 0);
65 
    enable   : in std_ulogic;
66 
    write    : in std_ulogic);
67 
  end component;
68 
 
69 
  component proasic_syncram_2p
70 
  generic ( abits : integer := 8; dbits : integer := 32);
71 
  port (
72 
    rclk  : in std_ulogic;
73 
    rena  : in std_ulogic;
74 
    raddr : in std_logic_vector (abits -1 downto 0);
75 
    dout  : out std_logic_vector (dbits -1 downto 0);
76 
    wclk  : in std_ulogic;
77 
    waddr : in std_logic_vector (abits -1 downto 0);
78 
    din   : in std_logic_vector (dbits -1 downto 0);
79 
    write : in std_ulogic);
80 
  end component;
81 
 
82 
-- Proasic3 family
83 
 
84 
  component proasic3_syncram
85 
  generic ( abits : integer := 10; dbits : integer := 8 );
86 
  port (
87 
    clk      : in std_ulogic;
88 
    address  : in std_logic_vector((abits -1) downto 0);
89 
    datain   : in std_logic_vector((dbits -1) downto 0);
90 
    dataout  : out std_logic_vector((dbits -1) downto 0);
91 
    enable   : in std_ulogic;
92 
    write    : in std_ulogic);
93 
  end component;
94 
 
95 
  component proasic3_syncram_2p
96 
  generic ( abits : integer := 8; dbits : integer := 32);
97 
  port (
98 
    rclk  : in std_ulogic;
99 
    rena  : in std_ulogic;
100 
    raddr : in std_logic_vector (abits -1 downto 0);
101 
    dout  : out std_logic_vector (dbits -1 downto 0);
102 
    wclk  : in std_ulogic;
103 
    waddr : in std_logic_vector (abits -1 downto 0);
104 
    din   : in std_logic_vector (dbits -1 downto 0);
105 
    write : in std_ulogic);
106 
  end component;
107 
 
108 
  component proasic3_syncram_dp is
109 
  generic ( abits : integer := 6; dbits : integer := 8 );
110 
  port (
111 
    clk1     : in std_ulogic;
112 
    address1 : in std_logic_vector((abits -1) downto 0);
113 
    datain1  : in std_logic_vector((dbits -1) downto 0);
114 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
115 
    enable1  : in std_ulogic;
116 
    write1   : in std_ulogic;
117 
    clk2     : in std_ulogic;
118 
    address2 : in std_logic_vector((abits -1) downto 0);
119 
    datain2  : in std_logic_vector((dbits -1) downto 0);
120 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
121 
    enable2  : in std_ulogic;
122 
    write2   : in std_ulogic
123 
   );
124 
  end component;
125 
 
126 
component altera_syncram
127 
  generic ( abits : integer := 10; dbits : integer := 8 );
128 
  port (
129 
    clk      : in std_ulogic;
130 
    address  : in std_logic_vector((abits -1) downto 0);
131 
    datain   : in std_logic_vector((dbits -1) downto 0);
132 
    dataout  : out std_logic_vector((dbits -1) downto 0);
133 
    enable   : in std_ulogic;
134 
    write    : in std_ulogic
135 
   );
136 
end component;
137 
 
138 
component altera_syncram_dp
139 
  generic ( abits : integer := 10; dbits : integer := 8 );
140 
  port (
141 
    clk1     : in std_ulogic;
142 
    address1 : in std_logic_vector((abits -1) downto 0);
143 
    datain1  : in std_logic_vector((dbits -1) downto 0);
144 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
145 
    enable1  : in std_ulogic;
146 
    write1   : in std_ulogic;
147 
    clk2     : in std_ulogic;
148 
    address2 : in std_logic_vector((abits -1) downto 0);
149 
    datain2  : in std_logic_vector((dbits -1) downto 0);
150 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
151 
    enable2  : in std_ulogic;
152 
    write2   : in std_ulogic
153 
   );
154 
end component;
155 
 
156 
component generic_syncram
157 
  generic (abits : integer := 10; dbits : integer := 8 );
158 
  port (
159 
    clk      : in std_ulogic;
160 
    address  : in std_logic_vector((abits -1) downto 0);
161 
    datain   : in std_logic_vector((dbits -1) downto 0);
162 
    dataout  : out std_logic_vector((dbits -1) downto 0);
163 
    write    : in std_ulogic
164 
   );
165 
end component;
166 
 
167 
component generic_syncram_2p
168 
  generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
169 
  port (
170 
    rclk : in std_ulogic;
171 
    wclk : in std_ulogic;
172 
    rdaddress: in std_logic_vector (abits -1 downto 0);
173 
    wraddress: in std_logic_vector (abits -1 downto 0);
174 
    data: in std_logic_vector (dbits -1 downto 0);
175 
    wren : in std_ulogic;
176 
    q: out std_logic_vector (dbits -1 downto 0)
177 
  );
178 
end component;
179 
 
180 
-- synchronous 3-port regfile (2 read, 1 write port)
181 
 
182 
  component generic_regfile_3p
183 
  generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
184 
           wrfst : integer := 0; numregs : integer := 40);
185 
  port (
186 
    wclk   : in  std_ulogic;
187 
    waddr  : in  std_logic_vector((abits -1) downto 0);
188 
    wdata  : in  std_logic_vector((dbits -1) downto 0);
189 
    we     : in  std_ulogic;
190 
    rclk   : in  std_ulogic;
191 
    raddr1 : in  std_logic_vector((abits -1) downto 0);
192 
    re1    : in  std_ulogic;
193 
    rdata1 : out std_logic_vector((dbits -1) downto 0);
194 
    raddr2 : in  std_logic_vector((abits -1) downto 0);
195 
    re2    : in  std_ulogic;
196 
    rdata2 : out std_logic_vector((dbits -1) downto 0)
197 
  );
198 
  end component;
199 
 
200 
  component ihp25_syncram
201 
    generic ( abits : integer := 10; dbits : integer := 8 );
202 
    port (
203 
      clk      : in std_logic;
204 
      address  : in std_logic_vector(abits -1 downto 0);
205 
      datain   : in std_logic_vector(dbits -1 downto 0);
206 
      dataout  : out std_logic_vector(dbits -1 downto 0);
207 
      enable   : in std_logic;
208 
      write    : in std_logic
209 
    );
210 
  end component;
211 
 
212 
  component ec_syncram
213 
  generic ( abits : integer := 10; dbits : integer := 8 );
214 
  port (
215 
    clk      : in std_ulogic;
216 
    address  : in std_logic_vector((abits -1) downto 0);
217 
    datain   : in std_logic_vector((dbits -1) downto 0);
218 
    dataout  : out std_logic_vector((dbits -1) downto 0);
219 
    enable   : in std_ulogic;
220 
    write    : in std_ulogic
221 
   );
222 
  end component;
223 
 
224 
  component ec_syncram_dp
225 
  generic ( abits : integer := 10; dbits : integer := 8 );
226 
  port (
227 
    clk1     : in std_ulogic;
228 
    address1 : in std_logic_vector((abits -1) downto 0);
229 
    datain1  : in std_logic_vector((dbits -1) downto 0);
230 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
231 
    enable1  : in std_ulogic;
232 
    write1   : in std_ulogic;
233 
    clk2     : in std_ulogic;
234 
    address2 : in std_logic_vector((abits -1) downto 0);
235 
    datain2  : in std_logic_vector((dbits -1) downto 0);
236 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
237 
    enable2  : in std_ulogic;
238 
    write2   : in std_ulogic
239 
   );
240 
  end component;
241 
 
242 
  component rh_lib18t_syncram_2p
243 
  generic (abits : integer := 6; dbits : integer := 8);
244 
  port (
245 
    rclk     : in std_ulogic;
246 
    renable  : in std_ulogic;
247 
    raddress : in std_logic_vector((abits -1) downto 0);
248 
    dataout  : out std_logic_vector((dbits -1) downto 0);
249 
    write    : in std_ulogic;
250 
    waddress : in std_logic_vector((abits -1) downto 0);
251 
    datain   : in std_logic_vector((dbits -1) downto 0);
252 
    diagin   : in std_logic_vector(3 downto 0));
253 
  end component;
254 
 
255 
  component rh_lib18t_syncram is
256 
  generic (abits : integer := 6; dbits : integer := 8 );
257 
  port (
258 
    clk      : in std_ulogic;
259 
    address  : in std_logic_vector((abits -1) downto 0);
260 
    datain   : in std_logic_vector((dbits -1) downto 0);
261 
    dataout  : out std_logic_vector((dbits -1) downto 0);
262 
    enable   : in std_ulogic;
263 
    write    : in std_ulogic;
264 
    diagin   : in std_logic_vector(1 downto 0) := "00");
265 
  end component;
266 
 
267 
  component umc_syncram
268 
  generic ( abits : integer := 10; dbits : integer := 8 );
269 
  port (
270 
    clk      : in std_ulogic;
271 
    address  : in std_logic_vector(abits -1 downto 0);
272 
    datain   : in std_logic_vector(dbits -1 downto 0);
273 
    dataout  : out std_logic_vector(dbits -1 downto 0);
274 
    enable   : in std_ulogic;
275 
    write    : in std_ulogic);
276 
  end component;
277 
 
278 
  component rhumc_syncram
279 
  generic ( abits : integer := 10; dbits : integer := 8 );
280 
  port (
281 
    clk      : in std_ulogic;
282 
    address  : in std_logic_vector(abits -1 downto 0);
283 
    datain   : in std_logic_vector(dbits -1 downto 0);
284 
    dataout  : out std_logic_vector(dbits -1 downto 0);
285 
    enable   : in std_ulogic;
286 
    write    : in std_ulogic);
287 
  end component;
288 
 
289 
  component virage_syncram
290 
  generic ( abits : integer := 10; dbits : integer := 8 );
291 
  port (
292 
    clk      : in std_ulogic;
293 
    address  : in std_logic_vector(abits -1 downto 0);
294 
    datain   : in std_logic_vector(dbits -1 downto 0);
295 
    dataout  : out std_logic_vector(dbits -1 downto 0);
296 
    enable   : in std_ulogic;
297 
    write    : in std_ulogic);
298 
  end component;
299 
 
300 
  component virage_syncram_dp
301 
  generic ( abits : integer := 10; dbits : integer := 8 );
302 
  port (
303 
    clk1     : in std_ulogic;
304 
    address1 : in std_logic_vector((abits -1) downto 0);
305 
    datain1  : in std_logic_vector((dbits -1) downto 0);
306 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
307 
    enable1  : in std_ulogic;
308 
    write1   : in std_ulogic;
309 
    clk2     : in std_ulogic;
310 
    address2 : in std_logic_vector((abits -1) downto 0);
311 
    datain2  : in std_logic_vector((dbits -1) downto 0);
312 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
313 
    enable2  : in std_ulogic;
314 
    write2   : in std_ulogic);
315 
  end component;
316 
 
317 
  component virage90_syncram
318 
  generic ( abits : integer := 10; dbits : integer := 8 );
319 
  port (
320 
    clk      : in std_ulogic;
321 
    address  : in std_logic_vector(abits -1 downto 0);
322 
    datain   : in std_logic_vector(dbits -1 downto 0);
323 
    dataout  : out std_logic_vector(dbits -1 downto 0);
324 
    enable   : in std_ulogic;
325 
    write    : in std_ulogic);
326 
  end component;
327 
 
328 
  component virtex_syncram
329 
  generic ( abits : integer := 6; dbits : integer := 8 );
330 
  port (
331 
    clk      : in std_ulogic;
332 
    address  : in std_logic_vector((abits -1) downto 0);
333 
    datain   : in std_logic_vector((dbits -1) downto 0);
334 
    dataout  : out std_logic_vector((dbits -1) downto 0);
335 
    enable   : in std_ulogic;
336 
    write    : in std_ulogic
337 
   );
338 
  end component;
339 
 
340 
  component virtex_syncram_dp
341 
  generic ( abits : integer := 6; dbits : integer := 8 );
342 
  port (
343 
    clk1     : in std_ulogic;
344 
    address1 : in std_logic_vector((abits -1) downto 0);
345 
    datain1  : in std_logic_vector((dbits -1) downto 0);
346 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
347 
    enable1  : in std_ulogic;
348 
    write1   : in std_ulogic;
349 
    clk2     : in std_ulogic;
350 
    address2 : in std_logic_vector((abits -1) downto 0);
351 
    datain2  : in std_logic_vector((dbits -1) downto 0);
352 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
353 
    enable2  : in std_ulogic;
354 
    write2   : in std_ulogic
355 
   );
356 
  end component;
357 
 
358 
  component virtex2_syncram
359 
  generic ( abits : integer := 10; dbits : integer := 8 );
360 
  port (
361 
    clk      : in std_ulogic;
362 
    address  : in std_logic_vector((abits -1) downto 0);
363 
    datain   : in std_logic_vector((dbits -1) downto 0);
364 
    dataout  : out std_logic_vector((dbits -1) downto 0);
365 
    enable   : in std_ulogic;
366 
    write    : in std_ulogic
367 
   );
368 
  end component;
369 
 
370 
  component virtex2_syncram_dp
371 
  generic ( abits : integer := 10; dbits : integer := 8 );
372 
  port (
373 
    clk1     : in std_ulogic;
374 
    address1 : in std_logic_vector((abits -1) downto 0);
375 
    datain1  : in std_logic_vector((dbits -1) downto 0);
376 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
377 
    enable1  : in std_ulogic;
378 
    write1   : in std_ulogic;
379 
    clk2     : in std_ulogic;
380 
    address2 : in std_logic_vector((abits -1) downto 0);
381 
    datain2  : in std_logic_vector((dbits -1) downto 0);
382 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
383 
    enable2  : in std_ulogic;
384 
    write2   : in std_ulogic
385 
   );
386 
  end component;
387 
 
388 
  component virage90_syncram_dp
389 
  generic ( abits : integer := 10; dbits : integer := 8 );
390 
  port (
391 
    clk1     : in std_ulogic;
392 
    address1 : in std_logic_vector((abits -1) downto 0);
393 
    datain1  : in std_logic_vector((dbits -1) downto 0);
394 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
395 
    enable1  : in std_ulogic;
396 
    write1   : in std_ulogic;
397 
    clk2     : in std_ulogic;
398 
    address2 : in std_logic_vector((abits -1) downto 0);
399 
    datain2  : in std_logic_vector((dbits -1) downto 0);
400 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
401 
    enable2  : in std_ulogic;
402 
    write2   : in std_ulogic
403 
   );
404 
  end component;
405 
 
406 
  component virtex2_syncram64
407 
  generic ( abits : integer := 9);
408 
  port (
409 
    clk     : in  std_ulogic;
410 
    address : in  std_logic_vector (abits -1 downto 0);
411 
    datain  : in  std_logic_vector (63 downto 0);
412 
    dataout : out std_logic_vector (63 downto 0);
413 
    enable  : in  std_logic_vector (1 downto 0);
414 
    write   : in  std_logic_vector (1 downto 0)
415 
  );
416 
  end component;
417 
 
418 
  component ut025crh_syncram
419 
  generic ( abits : integer := 10; dbits : integer := 8 );
420 
  port (
421 
    clk      : in std_ulogic;
422 
    address  : in std_logic_vector((abits -1) downto 0);
423 
    datain   : in std_logic_vector((dbits -1) downto 0);
424 
    dataout  : out std_logic_vector((dbits -1) downto 0);
425 
    enable   : in std_ulogic;
426 
    write    : in std_ulogic
427 
   );
428 
  end component;
429 
 
430 
  component ut025crh_syncram_2p
431 
  generic ( abits : integer := 8; dbits : integer := 32);
432 
  port (
433 
    rclk  : in std_ulogic;
434 
    rena  : in std_ulogic;
435 
    raddr : in std_logic_vector (abits -1 downto 0);
436 
    dout  : out std_logic_vector (dbits -1 downto 0);
437 
    wclk  : in std_ulogic;
438 
    waddr : in std_logic_vector (abits -1 downto 0);
439 
    din   : in std_logic_vector (dbits -1 downto 0);
440 
    write : in std_ulogic);
441 
  end component;
442 
 
443 
  component peregrine_regfile_3p
444 
  generic (abits : integer := 6; dbits : integer := 32);
445 
  port (
446 
    wclk   : in  std_ulogic;
447 
    waddr  : in  std_logic_vector((abits -1) downto 0);
448 
    wdata  : in  std_logic_vector((dbits -1) downto 0);
449 
    we     : in  std_ulogic;
450 
    raddr1 : in  std_logic_vector((abits -1) downto 0);
451 
    re1    : in  std_ulogic;
452 
    rdata1 : out std_logic_vector((dbits -1) downto 0);
453 
    raddr2 : in  std_logic_vector((abits -1) downto 0);
454 
    re2    : in  std_ulogic;
455 
    rdata2 : out std_logic_vector((dbits -1) downto 0));
456 
  end component;
457 
 
458 
  component eclipse_syncram_2p is
459 
  generic ( abits : integer := 8; dbits : integer := 32);
460 
  port (
461 
    rclk  : in std_ulogic;
462 
    rena  : in std_ulogic;
463 
    raddr : in std_logic_vector (abits -1 downto 0);
464 
    dout  : out std_logic_vector (dbits -1 downto 0);
465 
    wclk  : in std_ulogic;
466 
    waddr : in std_logic_vector (abits -1 downto 0);
467 
    din   : in std_logic_vector (dbits -1 downto 0);
468 
    write : in std_ulogic);
469 
  end component;
470 
 
471 
  component nextreme_syncram_2p is
472 
  generic (abits : integer := 6; dbits : integer := 8);
473 
  port (
474 
    rclk     : in std_ulogic;
475 
    renable  : in std_ulogic;
476 
    raddress : in std_logic_vector((abits -1) downto 0);
477 
    dataout  : out std_logic_vector((dbits -1) downto 0);
478 
    wclk     : in std_ulogic;
479 
    write    : in std_ulogic;
480 
    waddress : in std_logic_vector((abits -1) downto 0);
481 
    datain   : in std_logic_vector((dbits -1) downto 0));
482 
  end component;
483 
 
484 
  component custom1_syncram_2p is
485 
  generic ( abits : integer := 8; dbits : integer := 32);
486 
  port (
487 
    rclk     : in std_ulogic;
488 
    renable  : in std_ulogic;
489 
    raddress : in std_logic_vector((abits -1) downto 0);
490 
    dataout  : out std_logic_vector((dbits -1) downto 0);
491 
    wclk     : in std_ulogic;
492 
    write    : in std_ulogic;
493 
    waddress : in std_logic_vector((abits -1) downto 0);
494 
    datain   : in std_logic_vector((dbits -1) downto 0));
495 
  end component;
496 
 
497 
  component artisan_syncram_2p is
498 
  generic ( abits : integer := 8; dbits : integer := 32);
499 
  port (
500 
    rclk     : in std_ulogic;
501 
    renable  : in std_ulogic;
502 
    raddress : in std_logic_vector((abits -1) downto 0);
503 
    dataout  : out std_logic_vector((dbits -1) downto 0);
504 
    wclk     : in std_ulogic;
505 
    write    : in std_ulogic;
506 
    waddress : in std_logic_vector((abits -1) downto 0);
507 
    datain   : in std_logic_vector((dbits -1) downto 0));
508 
  end component;
509 
 
510 
  component ihp25rh_syncram
511 
    generic ( abits : integer := 10; dbits : integer := 8 );
512 
    port (
513 
      clk      : in std_logic;
514 
      address  : in std_logic_vector(abits -1 downto 0);
515 
      datain   : in std_logic_vector(dbits -1 downto 0);
516 
      dataout  : out std_logic_vector(dbits -1 downto 0);
517 
      enable   : in std_logic;
518 
      write    : in std_logic);
519 
  end component;
520 
 
521 
  component peregrine_syncram
522 
  generic ( abits : integer := 10; dbits : integer := 8 );
523 
  port (
524 
    clk      : in std_ulogic;
525 
    address  : in std_logic_vector((abits -1) downto 0);
526 
    datain   : in std_logic_vector((dbits -1) downto 0);
527 
    dataout  : out std_logic_vector((dbits -1) downto 0);
528 
    enable   : in std_ulogic;
529 
    write    : in std_ulogic
530 
   );
531 
  end component;
532 
 
533 
  component artisan_syncram
534 
  generic ( abits : integer := 10; dbits : integer := 32 );
535 
  port (
536 
    clk      : in std_ulogic;
537 
    address  : in std_logic_vector((abits -1) downto 0);
538 
    datain   : in std_logic_vector((dbits -1) downto 0);
539 
    dataout  : out std_logic_vector((dbits -1) downto 0);
540 
    enable   : in std_ulogic;
541 
    write    : in std_ulogic
542 
   );
543 
  end component;
544 
 
545 
  component custom1_syncram
546 
  generic ( abits : integer := 10; dbits : integer := 32 );
547 
  port (
548 
    clk      : in std_ulogic;
549 
    address  : in std_logic_vector((abits -1) downto 0);
550 
    datain   : in std_logic_vector((dbits -1) downto 0);
551 
    dataout  : out std_logic_vector((dbits -1) downto 0);
552 
    enable   : in std_ulogic;
553 
    write    : in std_ulogic
554 
   );
555 
  end component;
556 
 
557 
  component nextreme_syncram
558 
  generic (abits : integer := 6; dbits : integer := 8 );
559 
  port (
560 
    clk      : in std_ulogic;
561 
    address  : in std_logic_vector((abits -1) downto 0);
562 
    datain   : in std_logic_vector((dbits -1) downto 0);
563 
    dataout  : out std_logic_vector((dbits -1) downto 0);
564 
    enable   : in std_ulogic;
565 
    write    : in std_ulogic);
566 
  end component;
567 
 
568 
  component virtex2_syncram_2p is
569 
  generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
570 
        wrfst : integer := 0);
571 
  port (
572 
    rclk     : in std_ulogic;
573 
    renable  : in std_ulogic;
574 
    raddress : in std_logic_vector((abits -1) downto 0);
575 
    dataout  : out std_logic_vector((dbits -1) downto 0);
576 
    wclk     : in std_ulogic;
577 
    write    : in std_ulogic;
578 
    waddress : in std_logic_vector((abits -1) downto 0);
579 
    datain   : in std_logic_vector((dbits -1) downto 0));
580 
  end component;
581 
 
582 
  component virage_syncram_2p
583 
  generic (abits : integer := 6; dbits : integer := 8;
584 
        sepclk : integer := 0; wrfst : integer := 0);
585 
  port (
586 
    rclk     : in std_ulogic;
587 
    renable  : in std_ulogic;
588 
    raddress : in std_logic_vector((abits -1) downto 0);
589 
    dataout  : out std_logic_vector((dbits -1) downto 0);
590 
    wclk     : in std_ulogic;
591 
    write    : in std_ulogic;
592 
    waddress : in std_logic_vector((abits -1) downto 0);
593 
    datain   : in std_logic_vector((dbits -1) downto 0));
594 
  end component;
595 
 
596 
  component atc18rha_syncram
597 
  generic ( abits : integer := 10; dbits : integer := 8 );
598 
  port (
599 
    clk      : in std_ulogic;
600 
    address  : in std_logic_vector(abits -1 downto 0);
601 
    datain   : in std_logic_vector(dbits -1 downto 0);
602 
    dataout  : out std_logic_vector(dbits -1 downto 0);
603 
    enable   : in std_ulogic;
604 
    write    : in std_ulogic;
605 
    testin   : in std_logic_vector(3 downto 0));
606 
  end component;
607 
 
608 
  component atc18rha_syncram_dp
609 
  generic ( abits : integer := 10; dbits : integer := 8);
610 
  port (
611 
    clk1     : in std_ulogic;
612 
    address1 : in std_logic_vector((abits -1) downto 0);
613 
    datain1  : in std_logic_vector((dbits -1) downto 0);
614 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
615 
    enable1  : in std_ulogic;
616 
    write1   : in std_ulogic;
617 
    clk2     : in std_ulogic;
618 
    address2 : in std_logic_vector((abits -1) downto 0);
619 
    datain2  : in std_logic_vector((dbits -1) downto 0);
620 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
621 
    enable2  : in std_ulogic;
622 
    write2   : in std_ulogic;
623 
    testin   : in std_logic_vector(3 downto 0));
624 
  end component;
625 
 
626 
  component atc18rha_syncram_2p
627 
  generic ( abits : integer := 6; dbits : integer := 8;
628 
        sepclk : integer := 0; wrfst : integer := 0);
629 
  port (
630 
    rclk     : in std_ulogic;
631 
    renable  : in std_ulogic;
632 
    raddress : in std_logic_vector((abits -1) downto 0);
633 
    dataout  : out std_logic_vector((dbits -1) downto 0);
634 
    wclk     : in std_ulogic;
635 
    write    : in std_ulogic;
636 
    waddress : in std_logic_vector((abits -1) downto 0);
637 
    datain   : in std_logic_vector((dbits -1) downto 0);
638 
    testin   : in std_logic_vector(3 downto 0));
639 
  end component;
640 
 
641 
  component artisan_syncram_dp
642 
  generic ( abits : integer := 10; dbits : integer := 32 );
643 
  port (
644 
    clk1     : in std_ulogic;
645 
    address1 : in std_logic_vector((abits -1) downto 0);
646 
    datain1  : in std_logic_vector((dbits -1) downto 0);
647 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
648 
    enable1  : in std_ulogic;
649 
    write1   : in std_ulogic;
650 
    clk2     : in std_ulogic;
651 
    address2 : in std_logic_vector((abits -1) downto 0);
652 
    datain2  : in std_logic_vector((dbits -1) downto 0);
653 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
654 
    enable2  : in std_ulogic;
655 
    write2   : in std_ulogic
656 
   );
657 
  end component;
658 
 
659 
end;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.