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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [grspwc_net.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity:      grspwc
-- File:        grspwc.vhd
-- Author:      Marko Isomaki - Gaisler Research 
-- Description: Provides a link interface to a SpaceWire network
--              with an AHB host interface and RMAP support.  
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
 
entity grspwc_net is
  generic(
    tech         : integer := 0;
    sysfreq      : integer := 40000;
    usegen       : integer range 0 to 1  := 1;
    nsync        : integer range 1 to 2  := 1;
    rmap         : integer range 0 to 1  := 0;
    rmapcrc      : integer range 0 to 1  := 0;
    fifosize1    : integer range 4 to 32 := 32;
    fifosize2    : integer range 16 to 64 := 64;
    rxunaligned  : integer range 0 to 1 := 0;
    rmapbufs     : integer range 2 to 8 := 4;
    scantest     : integer range 0 to 1 := 0
  );
  port(
    rst          : in  std_ulogic;
    clk          : in  std_ulogic;
    txclk        : in  std_ulogic;
    --ahb mst in
    hgrant       : in  std_ulogic;
    hready       : in  std_ulogic;
    hresp        : in  std_logic_vector(1 downto 0);
    hrdata       : in  std_logic_vector(31 downto 0);
    --ahb mst out
    hbusreq      : out  std_ulogic;
    hlock        : out  std_ulogic;
    htrans       : out  std_logic_vector(1 downto 0);
    haddr        : out  std_logic_vector(31 downto 0);
    hwrite       : out  std_ulogic;
    hsize        : out  std_logic_vector(2 downto 0);
    hburst       : out  std_logic_vector(2 downto 0);
    hprot        : out  std_logic_vector(3 downto 0);
    hwdata       : out  std_logic_vector(31 downto 0);
    --apb slv in 
    psel         : in   std_ulogic;
    penable      : in   std_ulogic;
    paddr        : in   std_logic_vector(31 downto 0);
    pwrite       : in   std_ulogic;
    pwdata       : in   std_logic_vector(31 downto 0);
    --apb slv out
    prdata       : out  std_logic_vector(31 downto 0);
    --spw in
    di           : in std_logic_vector(1 downto 0);
    si           : in std_logic_vector(1 downto 0);
    --spw out
    do           : out std_logic_vector(1 downto 0);
    so           : out std_logic_vector(1 downto 0);
    --time iface
    tickin       : in   std_ulogic;
    tickout      : out  std_ulogic;
    --irq
    irq          : out  std_logic;
    --misc     
    clkdiv10     : in   std_logic_vector(7 downto 0);
    dcrstval     : in   std_logic_vector(9 downto 0);
    timerrstval  : in   std_logic_vector(11 downto 0);
    --rmapen
    rmapen       : in   std_ulogic;
    --clk bufs
    rxclki       : in std_logic_vector(1 downto 0);
    nrxclki      : in std_logic_vector(1 downto 0);
    rxclko       : out std_logic_vector(1 downto 0);
    --rx ahb fifo
    rxrenable    : out  std_ulogic;
    rxraddress   : out  std_logic_vector(4 downto 0);
    rxwrite      : out  std_ulogic;
    rxwdata      : out  std_logic_vector(31 downto 0);
    rxwaddress   : out  std_logic_vector(4 downto 0);
    rxrdata      : in   std_logic_vector(31 downto 0);
    --tx ahb fifo
    txrenable    : out  std_ulogic;
    txraddress   : out  std_logic_vector(4 downto 0);
    txwrite      : out  std_ulogic;
    txwdata      : out  std_logic_vector(31 downto 0);
    txwaddress   : out  std_logic_vector(4 downto 0);
    txrdata      : in   std_logic_vector(31 downto 0);
    --nchar fifo
    ncrenable    : out  std_ulogic;
    ncraddress   : out  std_logic_vector(5 downto 0);
    ncwrite      : out  std_ulogic;
    ncwdata      : out  std_logic_vector(8 downto 0);
    ncwaddress   : out  std_logic_vector(5 downto 0);
    ncrdata      : in   std_logic_vector(8 downto 0);
    --rmap buf
    rmrenable    : out  std_ulogic;
    rmraddress   : out  std_logic_vector(7 downto 0);
    rmwrite      : out  std_ulogic;
    rmwdata      : out  std_logic_vector(7 downto 0);
    rmwaddress   : out  std_logic_vector(7 downto 0);
    rmrdata      : in   std_logic_vector(7 downto 0);
    linkdis      : out  std_ulogic;
    testclk      : in   std_ulogic := '0';
    testrst      : in   std_ulogic := '0';
    testen       : in   std_ulogic := '0'
  );
end entity;
 
architecture rtl of grspwc_net is
 
component grspwc_unisim
  generic(
    sysfreq      : integer := 40000;
    usegen       : integer range 0 to 1  := 1;
    nsync        : integer range 1 to 2  := 1;
    rmap         : integer range 0 to 1  := 0;
    rmapcrc      : integer range 0 to 1  := 0;
    fifosize1    : integer range 4 to 32 := 32;
    fifosize2    : integer range 16 to 64 := 64;
    rxunaligned  : integer range 0 to 1 := 0;
    rmapbufs     : integer range 2 to 8 := 4;
    scantest     : integer range 0 to 1 := 0
  );
  port(
    rst          : in  std_ulogic;
    clk          : in  std_ulogic;
    txclk        : in  std_ulogic;
    --ahb mst in
    hgrant       : in  std_ulogic;
    hready       : in  std_ulogic;
    hresp        : in  std_logic_vector(1 downto 0);
    hrdata       : in  std_logic_vector(31 downto 0);
    --ahb mst out
    hbusreq      : out  std_ulogic;
    hlock        : out  std_ulogic;
    htrans       : out  std_logic_vector(1 downto 0);
    haddr        : out  std_logic_vector(31 downto 0);
    hwrite       : out  std_ulogic;
    hsize        : out  std_logic_vector(2 downto 0);
    hburst       : out  std_logic_vector(2 downto 0);
    hprot        : out  std_logic_vector(3 downto 0);
    hwdata       : out  std_logic_vector(31 downto 0);
    --apb slv in 
    psel         : in   std_ulogic;
    penable      : in   std_ulogic;
    paddr        : in   std_logic_vector(31 downto 0);
    pwrite       : in   std_ulogic;
    pwdata       : in   std_logic_vector(31 downto 0);
    --apb slv out
    prdata       : out  std_logic_vector(31 downto 0);
    --spw in
    di           : in std_logic_vector(1 downto 0);
    si           : in std_logic_vector(1 downto 0);
    --spw out
    do           : out std_logic_vector(1 downto 0);
    so           : out std_logic_vector(1 downto 0);
    --time iface
    tickin       : in   std_ulogic;
    tickout      : out  std_ulogic;
    --irq
    irq          : out  std_logic;
    --misc     
    clkdiv10     : in   std_logic_vector(7 downto 0);
    dcrstval     : in   std_logic_vector(9 downto 0);
    timerrstval  : in   std_logic_vector(11 downto 0);
    --rmapen
    rmapen       : in   std_ulogic;
    --clk bufs
    rxclki       : in std_logic_vector(1 downto 0);
    nrxclki      : in std_logic_vector(1 downto 0);
    rxclko       : out std_logic_vector(1 downto 0);
    --rx ahb fifo
    rxrenable    : out  std_ulogic;
    rxraddress   : out  std_logic_vector(4 downto 0);
    rxwrite      : out  std_ulogic;
    rxwdata      : out  std_logic_vector(31 downto 0);
    rxwaddress   : out  std_logic_vector(4 downto 0);
    rxrdata      : in   std_logic_vector(31 downto 0);
    --tx ahb fifo
    txrenable    : out  std_ulogic;
    txraddress   : out  std_logic_vector(4 downto 0);
    txwrite      : out  std_ulogic;
    txwdata      : out  std_logic_vector(31 downto 0);
    txwaddress   : out  std_logic_vector(4 downto 0);
    txrdata      : in   std_logic_vector(31 downto 0);
    --nchar fifo
    ncrenable    : out  std_ulogic;
    ncraddress   : out  std_logic_vector(5 downto 0);
    ncwrite      : out  std_ulogic;
    ncwdata      : out  std_logic_vector(8 downto 0);
    ncwaddress   : out  std_logic_vector(5 downto 0);
    ncrdata      : in   std_logic_vector(8 downto 0);
    --rmap buf
    rmrenable    : out  std_ulogic;
    rmraddress   : out  std_logic_vector(7 downto 0);
    rmwrite      : out  std_ulogic;
    rmwdata      : out  std_logic_vector(7 downto 0);
    rmwaddress   : out  std_logic_vector(7 downto 0);
    rmrdata      : in   std_logic_vector(7 downto 0);
    linkdis      : out  std_ulogic;
    testclk      : in   std_ulogic := '0';
    testrst      : in   std_ulogic := '0';
    testen       : in   std_ulogic := '0'
  );
end component;
 
component grspwc_axcelerator
  generic(
    sysfreq      : integer := 40000;
    usegen       : integer range 0 to 1  := 1;
    nsync        : integer range 1 to 2  := 1;
    rmap         : integer range 0 to 1  := 0;
    rmapcrc      : integer range 0 to 1  := 0;
    fifosize1    : integer range 4 to 32 := 32;
    fifosize2    : integer range 16 to 64 := 64;
    rxunaligned  : integer range 0 to 1 := 0;
    rmapbufs     : integer range 2 to 8 := 4;
    scantest     : integer range 0 to 1 := 0
  );
  port(
    rst          : in  std_ulogic;
    clk          : in  std_ulogic;
    txclk        : in  std_ulogic;
    --ahb mst in
    hgrant       : in  std_ulogic;
    hready       : in  std_ulogic;
    hresp        : in  std_logic_vector(1 downto 0);
    hrdata       : in  std_logic_vector(31 downto 0);
    --ahb mst out
    hbusreq      : out  std_ulogic;
    hlock        : out  std_ulogic;
    htrans       : out  std_logic_vector(1 downto 0);
    haddr        : out  std_logic_vector(31 downto 0);
    hwrite       : out  std_ulogic;
    hsize        : out  std_logic_vector(2 downto 0);
    hburst       : out  std_logic_vector(2 downto 0);
    hprot        : out  std_logic_vector(3 downto 0);
    hwdata       : out  std_logic_vector(31 downto 0);
    --apb slv in 
    psel         : in   std_ulogic;
    penable      : in   std_ulogic;
    paddr        : in   std_logic_vector(31 downto 0);
    pwrite       : in   std_ulogic;
    pwdata       : in   std_logic_vector(31 downto 0);
    --apb slv out
    prdata       : out  std_logic_vector(31 downto 0);
    --spw in
    di : in std_logic_vector(1 downto 0);
    si : in std_logic_vector(1 downto 0);
    --spw out
    do : out std_logic_vector(1 downto 0);
    so : out std_logic_vector(1 downto 0);
    --time iface
    tickin       : in   std_ulogic;
    tickout      : out  std_ulogic;
    --irq
    irq          : out  std_logic;
    --misc     
    clkdiv10     : in   std_logic_vector(7 downto 0);
    dcrstval     : in   std_logic_vector(9 downto 0);
    timerrstval  : in   std_logic_vector(11 downto 0);
    --rmapen
    rmapen       : in   std_ulogic;
    --clk bufs
    rxclki : in std_logic_vector(1 downto 0);
    nrxclki : in std_logic_vector(1 downto 0);
    rxclko : out std_logic_vector(1 downto 0);
    --rx ahb fifo
    rxrenable    : out  std_ulogic;
    rxraddress   : out  std_logic_vector(4 downto 0);
    rxwrite      : out  std_ulogic;
    rxwdata      : out  std_logic_vector(31 downto 0);
    rxwaddress   : out  std_logic_vector(4 downto 0);
    rxrdata      : in   std_logic_vector(31 downto 0);
    --tx ahb fifo
    txrenable    : out  std_ulogic;
    txraddress   : out  std_logic_vector(4 downto 0);
    txwrite      : out  std_ulogic;
    txwdata      : out  std_logic_vector(31 downto 0);
    txwaddress   : out  std_logic_vector(4 downto 0);
    txrdata      : in   std_logic_vector(31 downto 0);
    --nchar fifo
    ncrenable    : out  std_ulogic;
    ncraddress   : out  std_logic_vector(5 downto 0);
    ncwrite      : out  std_ulogic;
    ncwdata      : out  std_logic_vector(8 downto 0);
    ncwaddress   : out  std_logic_vector(5 downto 0);
    ncrdata      : in   std_logic_vector(8 downto 0);
    --rmap buf
    rmrenable    : out  std_ulogic;
    rmraddress   : out  std_logic_vector(7 downto 0);
    rmwrite      : out  std_ulogic;
    rmwdata      : out  std_logic_vector(7 downto 0);
    rmwaddress   : out  std_logic_vector(7 downto 0);
    rmrdata      : in   std_logic_vector(7 downto 0);
    linkdis      : out  std_ulogic;
    testclk      : in   std_ulogic := '0';
    testrst      : in   std_ulogic := '0';
    testen       : in   std_ulogic := '0'
  );
end component;
 
begin
 
  ax : if tech = axcel generate
    grspwc0 : grspwc_axcelerator
    generic map (sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
                 rxunaligned, rmapbufs, scantest)
    port map(
      rst          => rst,
      clk          => clk,
      txclk        => txclk,
      --ahb mst in
      hgrant       => hgrant,
      hready       => hready,
      hresp        => hresp,
      hrdata       => hrdata,
      --ahb mst out
      hbusreq      => hbusreq,
      hlock        => hlock,
      htrans       => htrans,
      haddr        => haddr,
      hwrite       => hwrite,
      hsize        => hsize,
      hburst       => hburst,
      hprot        => hprot,
      hwdata       => hwdata,
      --apb slv in 
      psel         => psel,
      penable      => penable,
      paddr        => paddr,
      pwrite       => pwrite,
      pwdata       => pwdata,
      --apb slv out
      prdata       => prdata,
      --spw in
      di           => di,
      si           => si,
      --spw out
      do           => do,
      so           => so,
      --time iface
      tickin       => tickin,
      tickout      => tickout,
      --clk bufs
      rxclki       => rxclki,
      nrxclki      => nrxclki,
      rxclko       => rxclko,
      --irq
      irq          => irq,
      --misc     
      clkdiv10     => clkdiv10,
      dcrstval     => dcrstval,
      timerrstval  => timerrstval,
      --rmapen    
      rmapen       => rmapen,
      --rx ahb fifo
      rxrenable    => rxrenable,
      rxraddress   => rxraddress,
      rxwrite      => rxwrite,
      rxwdata      => rxwdata,
      rxwaddress   => rxwaddress,
      rxrdata      => rxrdata,
      --tx ahb fifo
      txrenable    => txrenable,
      txraddress   => txraddress,
      txwrite      => txwrite,
      txwdata      => txwdata,
      txwaddress   => txwaddress,
      txrdata      => txrdata,
      --nchar fifo
      ncrenable    => ncrenable,
      ncraddress   => ncraddress,
      ncwrite      => ncwrite,
      ncwdata      => ncwdata,
      ncwaddress   => ncwaddress,
      ncrdata      => ncrdata,
      --rmap buf
      rmrenable    => rmrenable,
      rmraddress   => rmraddress,
      rmwrite      => rmwrite,
      rmwdata      => rmwdata,
      rmwaddress   => rmwaddress,
      rmrdata      => rmrdata,
      linkdis      => linkdis,
      testclk      => testclk,
      testrst      => testrst,
      testen       => testen
      );
  end generate;
 
  xil : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
        (tech = spartan3) or (tech = spartan3e) generate
    grspwc0 : grspwc_unisim
    generic map (sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
                 rxunaligned, rmapbufs, scantest)
    port map(
      rst          => rst,
      clk          => clk,
      txclk        => txclk,
      --ahb mst in
      hgrant       => hgrant,
      hready       => hready,
      hresp        => hresp,
      hrdata       => hrdata,
      --ahb mst out
      hbusreq      => hbusreq,
      hlock        => hlock,
      htrans       => htrans,
      haddr        => haddr,
      hwrite       => hwrite,
      hsize        => hsize,
      hburst       => hburst,
      hprot        => hprot,
      hwdata       => hwdata,
      --apb slv in 
      psel         => psel,
      penable      => penable,
      paddr        => paddr,
      pwrite       => pwrite,
      pwdata       => pwdata,
      --apb slv out
      prdata       => prdata,
      --spw in
      di           => di,
      si           => si,
      --spw out
      do           => do,
      so           => so,
      --time iface
      tickin       => tickin,
      tickout      => tickout,
      --clk bufs
      rxclki       => rxclki,
      nrxclki      => nrxclki,
      rxclko       => rxclko,
      --irq
      irq          => irq,
      --misc     
      clkdiv10     => clkdiv10,
      dcrstval     => dcrstval,
      timerrstval  => timerrstval,
      --rmapen    
      rmapen       => rmapen,
      --rx ahb fifo
      rxrenable    => rxrenable,
      rxraddress   => rxraddress,
      rxwrite      => rxwrite,
      rxwdata      => rxwdata,
      rxwaddress   => rxwaddress,
      rxrdata      => rxrdata,
      --tx ahb fifo
      txrenable    => txrenable,
      txraddress   => txraddress,
      txwrite      => txwrite,
      txwdata      => txwdata,
      txwaddress   => txwaddress,
      txrdata      => txrdata,
      --nchar fifo
      ncrenable    => ncrenable,
      ncraddress   => ncraddress,
      ncwrite      => ncwrite,
      ncwdata      => ncwdata,
      ncwaddress   => ncwaddress,
      ncrdata      => ncrdata,
      --rmap buf
      rmrenable    => rmrenable,
      rmraddress   => rmraddress,
      rmwrite      => rmwrite,
      rmwdata      => rmwdata,
      rmwaddress   => rmwaddress,
      rmrdata      => rmrdata,
      linkdis      => linkdis,
      testclk      => testclk,
      testrst      => testrst,
      testen       => testen
      );
  end generate;
 
-- pragma translate_off
  nonet : if not ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
        (tech = spartan3) or (tech = spartan3e) or (tech = axcel))
  generate
    err : process
    begin
      assert false report "ERROR : No GRSPWC netlist available for this process!"
      severity failure;
      wait;
    end process;
  end generate;
 
-- pragma translate_on
 
end architecture;

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [maps/] [grspwc_net.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Entity: grspwc`
20			`-- File: grspwc.vhd`
21			`-- Author: Marko Isomaki - Gaisler Research`
22			`-- Description: Provides a link interface to a SpaceWire network`
23			`-- with an AHB host interface and RMAP support.`
24			`------------------------------------------------------------------------------`
25			`library ieee;`
26			`use ieee.std_logic_1164.all;`
27			`library techmap;`
28			`use techmap.gencomp.all;`
29
30			`entity grspwc_net is`
31			`generic(`
32			`tech : integer := 0;`
33			`sysfreq : integer := 40000;`
34			`usegen : integer range 0 to 1 := 1;`
35			`nsync : integer range 1 to 2 := 1;`
36			`rmap : integer range 0 to 1 := 0;`
37			`rmapcrc : integer range 0 to 1 := 0;`
38			`fifosize1 : integer range 4 to 32 := 32;`
39			`fifosize2 : integer range 16 to 64 := 64;`
40			`rxunaligned : integer range 0 to 1 := 0;`
41			`rmapbufs : integer range 2 to 8 := 4;`
42			`scantest : integer range 0 to 1 := 0`
43			`);`
44			`port(`
45			`rst : in std_ulogic;`
46			`clk : in std_ulogic;`
47			`txclk : in std_ulogic;`
48			`--ahb mst in`
49			`hgrant : in std_ulogic;`
50			`hready : in std_ulogic;`
51			`hresp : in std_logic_vector(1 downto 0);`
52			`hrdata : in std_logic_vector(31 downto 0);`
53			`--ahb mst out`
54			`hbusreq : out std_ulogic;`
55			`hlock : out std_ulogic;`
56			`htrans : out std_logic_vector(1 downto 0);`
57			`haddr : out std_logic_vector(31 downto 0);`
58			`hwrite : out std_ulogic;`
59			`hsize : out std_logic_vector(2 downto 0);`
60			`hburst : out std_logic_vector(2 downto 0);`
61			`hprot : out std_logic_vector(3 downto 0);`
62			`hwdata : out std_logic_vector(31 downto 0);`
63			`--apb slv in`
64			`psel : in std_ulogic;`
65			`penable : in std_ulogic;`
66			`paddr : in std_logic_vector(31 downto 0);`
67			`pwrite : in std_ulogic;`
68			`pwdata : in std_logic_vector(31 downto 0);`
69			`--apb slv out`
70			`prdata : out std_logic_vector(31 downto 0);`
71			`--spw in`
72			`di : in std_logic_vector(1 downto 0);`
73			`si : in std_logic_vector(1 downto 0);`
74			`--spw out`
75			`do : out std_logic_vector(1 downto 0);`
76			`so : out std_logic_vector(1 downto 0);`
77			`--time iface`
78			`tickin : in std_ulogic;`
79			`tickout : out std_ulogic;`
80			`--irq`
81			`irq : out std_logic;`
82			`--misc`
83			`clkdiv10 : in std_logic_vector(7 downto 0);`
84			`dcrstval : in std_logic_vector(9 downto 0);`
85			`timerrstval : in std_logic_vector(11 downto 0);`
86			`--rmapen`
87			`rmapen : in std_ulogic;`
88			`--clk bufs`
89			`rxclki : in std_logic_vector(1 downto 0);`
90			`nrxclki : in std_logic_vector(1 downto 0);`
91			`rxclko : out std_logic_vector(1 downto 0);`
92			`--rx ahb fifo`
93			`rxrenable : out std_ulogic;`
94			`rxraddress : out std_logic_vector(4 downto 0);`
95			`rxwrite : out std_ulogic;`
96			`rxwdata : out std_logic_vector(31 downto 0);`
97			`rxwaddress : out std_logic_vector(4 downto 0);`
98			`rxrdata : in std_logic_vector(31 downto 0);`
99			`--tx ahb fifo`
100			`txrenable : out std_ulogic;`
101			`txraddress : out std_logic_vector(4 downto 0);`
102			`txwrite : out std_ulogic;`
103			`txwdata : out std_logic_vector(31 downto 0);`
104			`txwaddress : out std_logic_vector(4 downto 0);`
105			`txrdata : in std_logic_vector(31 downto 0);`
106			`--nchar fifo`
107			`ncrenable : out std_ulogic;`
108			`ncraddress : out std_logic_vector(5 downto 0);`
109			`ncwrite : out std_ulogic;`
110			`ncwdata : out std_logic_vector(8 downto 0);`
111			`ncwaddress : out std_logic_vector(5 downto 0);`
112			`ncrdata : in std_logic_vector(8 downto 0);`
113			`--rmap buf`
114			`rmrenable : out std_ulogic;`
115			`rmraddress : out std_logic_vector(7 downto 0);`
116			`rmwrite : out std_ulogic;`
117			`rmwdata : out std_logic_vector(7 downto 0);`
118			`rmwaddress : out std_logic_vector(7 downto 0);`
119			`rmrdata : in std_logic_vector(7 downto 0);`
120			`linkdis : out std_ulogic;`
121			`testclk : in std_ulogic := '0';`
122			`testrst : in std_ulogic := '0';`
123			`testen : in std_ulogic := '0'`
124			`);`
125			`end entity;`
126
127			`architecture rtl of grspwc_net is`
128
129			`component grspwc_unisim`
130			`generic(`
131			`sysfreq : integer := 40000;`
132			`usegen : integer range 0 to 1 := 1;`
133			`nsync : integer range 1 to 2 := 1;`
134			`rmap : integer range 0 to 1 := 0;`
135			`rmapcrc : integer range 0 to 1 := 0;`
136			`fifosize1 : integer range 4 to 32 := 32;`
137			`fifosize2 : integer range 16 to 64 := 64;`
138			`rxunaligned : integer range 0 to 1 := 0;`
139			`rmapbufs : integer range 2 to 8 := 4;`
140			`scantest : integer range 0 to 1 := 0`
141			`);`
142			`port(`
143			`rst : in std_ulogic;`
144			`clk : in std_ulogic;`
145			`txclk : in std_ulogic;`
146			`--ahb mst in`
147			`hgrant : in std_ulogic;`
148			`hready : in std_ulogic;`
149			`hresp : in std_logic_vector(1 downto 0);`
150			`hrdata : in std_logic_vector(31 downto 0);`
151			`--ahb mst out`
152			`hbusreq : out std_ulogic;`
153			`hlock : out std_ulogic;`
154			`htrans : out std_logic_vector(1 downto 0);`
155			`haddr : out std_logic_vector(31 downto 0);`
156			`hwrite : out std_ulogic;`
157			`hsize : out std_logic_vector(2 downto 0);`
158			`hburst : out std_logic_vector(2 downto 0);`
159			`hprot : out std_logic_vector(3 downto 0);`
160			`hwdata : out std_logic_vector(31 downto 0);`
161			`--apb slv in`
162			`psel : in std_ulogic;`
163			`penable : in std_ulogic;`
164			`paddr : in std_logic_vector(31 downto 0);`
165			`pwrite : in std_ulogic;`
166			`pwdata : in std_logic_vector(31 downto 0);`
167			`--apb slv out`
168			`prdata : out std_logic_vector(31 downto 0);`
169			`--spw in`
170			`di : in std_logic_vector(1 downto 0);`
171			`si : in std_logic_vector(1 downto 0);`
172			`--spw out`
173			`do : out std_logic_vector(1 downto 0);`
174			`so : out std_logic_vector(1 downto 0);`
175			`--time iface`
176			`tickin : in std_ulogic;`
177			`tickout : out std_ulogic;`
178			`--irq`
179			`irq : out std_logic;`
180			`--misc`
181			`clkdiv10 : in std_logic_vector(7 downto 0);`
182			`dcrstval : in std_logic_vector(9 downto 0);`
183			`timerrstval : in std_logic_vector(11 downto 0);`
184			`--rmapen`
185			`rmapen : in std_ulogic;`
186			`--clk bufs`
187			`rxclki : in std_logic_vector(1 downto 0);`
188			`nrxclki : in std_logic_vector(1 downto 0);`
189			`rxclko : out std_logic_vector(1 downto 0);`
190			`--rx ahb fifo`
191			`rxrenable : out std_ulogic;`
192			`rxraddress : out std_logic_vector(4 downto 0);`
193			`rxwrite : out std_ulogic;`
194			`rxwdata : out std_logic_vector(31 downto 0);`
195			`rxwaddress : out std_logic_vector(4 downto 0);`
196			`rxrdata : in std_logic_vector(31 downto 0);`
197			`--tx ahb fifo`
198			`txrenable : out std_ulogic;`
199			`txraddress : out std_logic_vector(4 downto 0);`
200			`txwrite : out std_ulogic;`
201			`txwdata : out std_logic_vector(31 downto 0);`
202			`txwaddress : out std_logic_vector(4 downto 0);`
203			`txrdata : in std_logic_vector(31 downto 0);`
204			`--nchar fifo`
205			`ncrenable : out std_ulogic;`
206			`ncraddress : out std_logic_vector(5 downto 0);`
207			`ncwrite : out std_ulogic;`
208			`ncwdata : out std_logic_vector(8 downto 0);`
209			`ncwaddress : out std_logic_vector(5 downto 0);`
210			`ncrdata : in std_logic_vector(8 downto 0);`
211			`--rmap buf`
212			`rmrenable : out std_ulogic;`
213			`rmraddress : out std_logic_vector(7 downto 0);`
214			`rmwrite : out std_ulogic;`
215			`rmwdata : out std_logic_vector(7 downto 0);`
216			`rmwaddress : out std_logic_vector(7 downto 0);`
217			`rmrdata : in std_logic_vector(7 downto 0);`
218			`linkdis : out std_ulogic;`
219			`testclk : in std_ulogic := '0';`
220			`testrst : in std_ulogic := '0';`
221			`testen : in std_ulogic := '0'`
222			`);`
223			`end component;`
224
225			`component grspwc_axcelerator`
226			`generic(`
227			`sysfreq : integer := 40000;`
228			`usegen : integer range 0 to 1 := 1;`
229			`nsync : integer range 1 to 2 := 1;`
230			`rmap : integer range 0 to 1 := 0;`
231			`rmapcrc : integer range 0 to 1 := 0;`
232			`fifosize1 : integer range 4 to 32 := 32;`
233			`fifosize2 : integer range 16 to 64 := 64;`
234			`rxunaligned : integer range 0 to 1 := 0;`
235			`rmapbufs : integer range 2 to 8 := 4;`
236			`scantest : integer range 0 to 1 := 0`
237			`);`
238			`port(`
239			`rst : in std_ulogic;`
240			`clk : in std_ulogic;`
241			`txclk : in std_ulogic;`
242			`--ahb mst in`
243			`hgrant : in std_ulogic;`
244			`hready : in std_ulogic;`
245			`hresp : in std_logic_vector(1 downto 0);`
246			`hrdata : in std_logic_vector(31 downto 0);`
247			`--ahb mst out`
248			`hbusreq : out std_ulogic;`
249			`hlock : out std_ulogic;`
250			`htrans : out std_logic_vector(1 downto 0);`
251			`haddr : out std_logic_vector(31 downto 0);`
252			`hwrite : out std_ulogic;`
253			`hsize : out std_logic_vector(2 downto 0);`
254			`hburst : out std_logic_vector(2 downto 0);`
255			`hprot : out std_logic_vector(3 downto 0);`
256			`hwdata : out std_logic_vector(31 downto 0);`
257			`--apb slv in`
258			`psel : in std_ulogic;`
259			`penable : in std_ulogic;`
260			`paddr : in std_logic_vector(31 downto 0);`
261			`pwrite : in std_ulogic;`
262			`pwdata : in std_logic_vector(31 downto 0);`
263			`--apb slv out`
264			`prdata : out std_logic_vector(31 downto 0);`
265			`--spw in`
266			`di : in std_logic_vector(1 downto 0);`
267			`si : in std_logic_vector(1 downto 0);`
268			`--spw out`
269			`do : out std_logic_vector(1 downto 0);`
270			`so : out std_logic_vector(1 downto 0);`
271			`--time iface`
272			`tickin : in std_ulogic;`
273			`tickout : out std_ulogic;`
274			`--irq`
275			`irq : out std_logic;`
276			`--misc`
277			`clkdiv10 : in std_logic_vector(7 downto 0);`
278			`dcrstval : in std_logic_vector(9 downto 0);`
279			`timerrstval : in std_logic_vector(11 downto 0);`
280			`--rmapen`
281			`rmapen : in std_ulogic;`
282			`--clk bufs`
283			`rxclki : in std_logic_vector(1 downto 0);`
284			`nrxclki : in std_logic_vector(1 downto 0);`
285			`rxclko : out std_logic_vector(1 downto 0);`
286			`--rx ahb fifo`
287			`rxrenable : out std_ulogic;`
288			`rxraddress : out std_logic_vector(4 downto 0);`
289			`rxwrite : out std_ulogic;`
290			`rxwdata : out std_logic_vector(31 downto 0);`
291			`rxwaddress : out std_logic_vector(4 downto 0);`
292			`rxrdata : in std_logic_vector(31 downto 0);`
293			`--tx ahb fifo`
294			`txrenable : out std_ulogic;`
295			`txraddress : out std_logic_vector(4 downto 0);`
296			`txwrite : out std_ulogic;`
297			`txwdata : out std_logic_vector(31 downto 0);`
298			`txwaddress : out std_logic_vector(4 downto 0);`
299			`txrdata : in std_logic_vector(31 downto 0);`
300			`--nchar fifo`
301			`ncrenable : out std_ulogic;`
302			`ncraddress : out std_logic_vector(5 downto 0);`
303			`ncwrite : out std_ulogic;`
304			`ncwdata : out std_logic_vector(8 downto 0);`
305			`ncwaddress : out std_logic_vector(5 downto 0);`
306			`ncrdata : in std_logic_vector(8 downto 0);`
307			`--rmap buf`
308			`rmrenable : out std_ulogic;`
309			`rmraddress : out std_logic_vector(7 downto 0);`
310			`rmwrite : out std_ulogic;`
311			`rmwdata : out std_logic_vector(7 downto 0);`
312			`rmwaddress : out std_logic_vector(7 downto 0);`
313			`rmrdata : in std_logic_vector(7 downto 0);`
314			`linkdis : out std_ulogic;`
315			`testclk : in std_ulogic := '0';`
316			`testrst : in std_ulogic := '0';`
317			`testen : in std_ulogic := '0'`
318			`);`
319			`end component;`
320
321			`begin`
322
323			`ax : if tech = axcel generate`
324			`grspwc0 : grspwc_axcelerator`
325			`generic map (sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,`
326			`rxunaligned, rmapbufs, scantest)`
327			`port map(`
328			`rst => rst,`
329			`clk => clk,`
330			`txclk => txclk,`
331			`--ahb mst in`
332			`hgrant => hgrant,`
333			`hready => hready,`
334			`hresp => hresp,`
335			`hrdata => hrdata,`
336			`--ahb mst out`
337			`hbusreq => hbusreq,`
338			`hlock => hlock,`
339			`htrans => htrans,`
340			`haddr => haddr,`
341			`hwrite => hwrite,`
342			`hsize => hsize,`
343			`hburst => hburst,`
344			`hprot => hprot,`
345			`hwdata => hwdata,`
346			`--apb slv in`
347			`psel => psel,`
348			`penable => penable,`
349			`paddr => paddr,`
350			`pwrite => pwrite,`
351			`pwdata => pwdata,`
352			`--apb slv out`
353			`prdata => prdata,`
354			`--spw in`
355			`di => di,`
356			`si => si,`
357			`--spw out`
358			`do => do,`
359			`so => so,`
360			`--time iface`
361			`tickin => tickin,`
362			`tickout => tickout,`
363			`--clk bufs`
364			`rxclki => rxclki,`
365			`nrxclki => nrxclki,`
366			`rxclko => rxclko,`
367			`--irq`
368			`irq => irq,`
369			`--misc`
370			`clkdiv10 => clkdiv10,`
371			`dcrstval => dcrstval,`
372			`timerrstval => timerrstval,`
373			`--rmapen`
374			`rmapen => rmapen,`
375			`--rx ahb fifo`
376			`rxrenable => rxrenable,`
377			`rxraddress => rxraddress,`
378			`rxwrite => rxwrite,`
379			`rxwdata => rxwdata,`
380			`rxwaddress => rxwaddress,`
381			`rxrdata => rxrdata,`
382			`--tx ahb fifo`
383			`txrenable => txrenable,`
384			`txraddress => txraddress,`
385			`txwrite => txwrite,`
386			`txwdata => txwdata,`
387			`txwaddress => txwaddress,`
388			`txrdata => txrdata,`
389			`--nchar fifo`
390			`ncrenable => ncrenable,`
391			`ncraddress => ncraddress,`
392			`ncwrite => ncwrite,`
393			`ncwdata => ncwdata,`
394			`ncwaddress => ncwaddress,`
395			`ncrdata => ncrdata,`
396			`--rmap buf`
397			`rmrenable => rmrenable,`
398			`rmraddress => rmraddress,`
399			`rmwrite => rmwrite,`
400			`rmwdata => rmwdata,`
401			`rmwaddress => rmwaddress,`
402			`rmrdata => rmrdata,`
403			`linkdis => linkdis,`
404			`testclk => testclk,`
405			`testrst => testrst,`
406			`testen => testen`
407			`);`
408			`end generate;`
409
410			`xil : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or`
411			`(tech = spartan3) or (tech = spartan3e) generate`
412			`grspwc0 : grspwc_unisim`
413			`generic map (sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,`
414			`rxunaligned, rmapbufs, scantest)`
415			`port map(`
416			`rst => rst,`
417			`clk => clk,`
418			`txclk => txclk,`
419			`--ahb mst in`
420			`hgrant => hgrant,`
421			`hready => hready,`
422			`hresp => hresp,`
423			`hrdata => hrdata,`
424			`--ahb mst out`
425			`hbusreq => hbusreq,`
426			`hlock => hlock,`
427			`htrans => htrans,`
428			`haddr => haddr,`
429			`hwrite => hwrite,`
430			`hsize => hsize,`
431			`hburst => hburst,`
432			`hprot => hprot,`
433			`hwdata => hwdata,`
434			`--apb slv in`
435			`psel => psel,`
436			`penable => penable,`
437			`paddr => paddr,`
438			`pwrite => pwrite,`
439			`pwdata => pwdata,`
440			`--apb slv out`
441			`prdata => prdata,`
442			`--spw in`
443			`di => di,`
444			`si => si,`
445			`--spw out`
446			`do => do,`
447			`so => so,`
448			`--time iface`
449			`tickin => tickin,`
450			`tickout => tickout,`
451			`--clk bufs`
452			`rxclki => rxclki,`
453			`nrxclki => nrxclki,`
454			`rxclko => rxclko,`
455			`--irq`
456			`irq => irq,`
457			`--misc`
458			`clkdiv10 => clkdiv10,`
459			`dcrstval => dcrstval,`
460			`timerrstval => timerrstval,`
461			`--rmapen`
462			`rmapen => rmapen,`
463			`--rx ahb fifo`
464			`rxrenable => rxrenable,`
465			`rxraddress => rxraddress,`
466			`rxwrite => rxwrite,`
467			`rxwdata => rxwdata,`
468			`rxwaddress => rxwaddress,`
469			`rxrdata => rxrdata,`
470			`--tx ahb fifo`
471			`txrenable => txrenable,`
472			`txraddress => txraddress,`
473			`txwrite => txwrite,`
474			`txwdata => txwdata,`
475			`txwaddress => txwaddress,`
476			`txrdata => txrdata,`
477			`--nchar fifo`
478			`ncrenable => ncrenable,`
479			`ncraddress => ncraddress,`
480			`ncwrite => ncwrite,`
481			`ncwdata => ncwdata,`
482			`ncwaddress => ncwaddress,`
483			`ncrdata => ncrdata,`
484			`--rmap buf`
485			`rmrenable => rmrenable,`
486			`rmraddress => rmraddress,`
487			`rmwrite => rmwrite,`
488			`rmwdata => rmwdata,`
489			`rmwaddress => rmwaddress,`
490			`rmrdata => rmrdata,`
491			`linkdis => linkdis,`
492			`testclk => testclk,`
493			`testrst => testrst,`
494			`testen => testen`
495			`);`
496			`end generate;`
497
498			`-- pragma translate_off`
499			`nonet : if not ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or`
500			`(tech = spartan3) or (tech = spartan3e) or (tech = axcel))`
501			`generate`
502			`err : process`
503			`begin`
504			`assert false report "ERROR : No GRSPWC netlist available for this process!"`
505			`severity failure;`
506			`wait;`
507			`end process;`
508			`end generate;`
509
510			`-- pragma translate_on`
511
512			`end architecture;`