URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [umc18/] [memory_umc18.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log


------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity:      various
-- File:        mem_umc_gen.vhd
-- Author:      Jiri Gaisler Gaisler Research
-- Description: Memory generators for UMC rams
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library umc18;
use umc18.SRAM_2048wx32b;
use umc18.SRAM_1024wx32b;
use umc18.SRAM_512wx32b;
use umc18.SRAM_256wx32b;
use umc18.SRAM_128wx32b;
use umc18.SRAM_64wx32b;
use umc18.SRAM_32wx32b;
use umc18.SRAM_2048wx40b;
use umc18.SRAM_1024wx40b;
use umc18.SRAM_512wx40b;
use umc18.SRAM_256wx40b;
use umc18.SRAM_128wx40b;
use umc18.SRAM_64wx40b;
use umc18.SRAM_32wx40b;
-- pragma translate_on
 
entity umc_syncram is
  generic ( abits : integer := 10; dbits : integer := 8 );
  port (
    clk      : in std_ulogic;
    address  : in std_logic_vector(abits -1 downto 0);
    datain   : in std_logic_vector(dbits -1 downto 0);
    dataout  : out std_logic_vector(dbits -1 downto 0);
    enable   : in std_ulogic;
    write    : in std_ulogic
  );
end;
 
architecture rtl of umc_syncram is
  component SRAM_2048wx32b is
  port (
        a    : in  std_logic_vector(10 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_1024wx32b is
  port (
        a    : in  std_logic_vector(9 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_512wx32b is
  port (
        a    : in  std_logic_vector(8 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_256wx32b is
  port (
        a    : in  std_logic_vector(7 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_128wx32b is
  port (
        a    : in  std_logic_vector(6 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_64wx32b is
  port (
        a    : in  std_logic_vector(5 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_32wx32b is
  port (
        a    : in  std_logic_vector(4 downto 0);
        data : in  std_logic_vector(31 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(31 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_2048wx40b is
  port (
        a    : in  std_logic_vector(10 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_1024wx40b is
  port (
        a    : in  std_logic_vector(9 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_512wx40b is
  port (
        a    : in  std_logic_vector(8 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_256wx40b is
  port (
        a    : in  std_logic_vector(7 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_128wx40b is
  port (
        a    : in  std_logic_vector(6 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_64wx40b is
  port (
        a    : in  std_logic_vector(5 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  component SRAM_32wx40b is
  port (
        a    : in  std_logic_vector(4 downto 0);
        data : in  std_logic_vector(39 downto 0);
        csn  : in  std_logic;
        wen  : in  std_logic;
        oen  : in  std_logic;
        q    : out std_logic_vector(39 downto 0);
        clk  : in  std_logic
       );
  end component;
 
  signal d, q, gnd : std_logic_vector(41 downto 0);
  signal a : std_logic_vector(17 downto 0);
  signal vcc, csn, wen : std_ulogic;
  constant synopsys_bug : std_logic_vector(41 downto 0) := (others => '0');
begin
 
  csn <= not enable; wen <= not write;
  gnd <= (others => '0'); vcc <= '1';
  a(abits -1 downto 0) <= address;
  d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
  a(17 downto abits) <= synopsys_bug(17 downto abits);
  d(41 downto dbits) <= synopsys_bug(41 downto dbits);
  dataout <= q(dbits -1 downto 0);
--  q(41 downto dbits) <= synopsys_bug(41 downto dbits);
 
  d32 : if (dbits <= 32) generate
    a5d32 : if (abits <= 5) generate
      id0 : SRAM_32wx32b port map (a(4 downto 0), d(31 downto 0), csn,
                                   wen, gnd(0), q(31 downto 0), clk);
    end generate;
    a6d32 : if (abits = 6) generate
      id0 : SRAM_64wx32b port map (a(5 downto 0), d(31 downto 0), csn,
                                   wen, gnd(0), q(31 downto 0), clk);
    end generate;
    a7d32 : if (abits = 7) generate
      id0 : SRAM_128wx32b port map (a(6 downto 0), d(31 downto 0), csn,
                                   wen, gnd(0), q(31 downto 0), clk);
    end generate;
    a8d32 : if (abits = 8) generate
      id0 : SRAM_256wx32b port map (a(7 downto 0), d(31 downto 0), csn,
                                   wen, gnd(0), q(31 downto 0), clk);
    end generate;
    a9d32 : if (abits = 9) generate
      id0 : SRAM_512wx32b port map (a(8 downto 0), d(31 downto 0), csn,
                                   wen, gnd(0), q(31 downto 0), clk);
    end generate;
    a10d32 : if (abits = 10) generate
      id0 : SRAM_1024wx32b port map (a(9 downto 0), d(31 downto 0), csn,
                                   wen, gnd(0), q(31 downto 0), clk);
    end generate;
    a11d32 : if (abits = 11) generate
      id0 : SRAM_2048wx32b port map (a(10 downto 0), d(31 downto 0), csn,
                                   wen, gnd(0), q(31 downto 0), clk);
    end generate;
  end generate;
 
  d40 : if (dbits > 32) and  (dbits <= 40) generate
    a5d40 : if (abits <= 5) generate
      id0 : SRAM_32wx40b port map (a(4 downto 0), d(39 downto 0), csn,
                                   wen, gnd(0), q(39 downto 0), clk);
    end generate;
    a6d40 : if (abits = 6) generate
      id0 : SRAM_64wx40b port map (a(5 downto 0), d(39 downto 0), csn,
                                   wen, gnd(0), q(39 downto 0), clk);
    end generate;
    a7d40 : if (abits = 7) generate
      id0 : SRAM_128wx40b port map (a(6 downto 0), d(39 downto 0), csn,
                                   wen, gnd(0), q(39 downto 0), clk);
    end generate;
    a8d40 : if (abits = 8) generate
      id0 : SRAM_256wx40b port map (a(7 downto 0), d(39 downto 0), csn,
                                   wen, gnd(0), q(39 downto 0), clk);
    end generate;
    a9d40 : if (abits = 9) generate
      id0 : SRAM_512wx40b port map (a(8 downto 0), d(39 downto 0), csn,
                                   wen, gnd(0), q(39 downto 0), clk);
    end generate;
    a10d40 : if (abits = 10) generate
      id0 : SRAM_1024wx40b port map (a(9 downto 0), d(39 downto 0), csn,
                                   wen, gnd(0), q(39 downto 0), clk);
    end generate;
    a11d40 : if (abits = 11) generate
      id0 : SRAM_2048wx40b port map (a(10 downto 0), d(39 downto 0), csn,
                                   wen, gnd(0), q(39 downto 0), clk);
    end generate;
  end generate;
 
-- pragma translate_off
  a_to_high : if (abits > 12) or (dbits > 40) generate
    x : process
    begin
      assert false
      report  "Unsupported memory size (umc18)"
      severity failure;
      wait;
    end process;
  end generate;
-- pragma translate_on
 
end;

Browse

Tools

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [techmap/] [umc18/] [memory_umc18.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Entity: various`
20			`-- File: mem_umc_gen.vhd`
21			`-- Author: Jiri Gaisler Gaisler Research`
22			`-- Description: Memory generators for UMC rams`
23			`------------------------------------------------------------------------------`
24
25			`library ieee;`
26			`use ieee.std_logic_1164.all;`
27			`-- pragma translate_off`
28			`library umc18;`
29			`use umc18.SRAM_2048wx32b;`
30			`use umc18.SRAM_1024wx32b;`
31			`use umc18.SRAM_512wx32b;`
32			`use umc18.SRAM_256wx32b;`
33			`use umc18.SRAM_128wx32b;`
34			`use umc18.SRAM_64wx32b;`
35			`use umc18.SRAM_32wx32b;`
36			`use umc18.SRAM_2048wx40b;`
37			`use umc18.SRAM_1024wx40b;`
38			`use umc18.SRAM_512wx40b;`
39			`use umc18.SRAM_256wx40b;`
40			`use umc18.SRAM_128wx40b;`
41			`use umc18.SRAM_64wx40b;`
42			`use umc18.SRAM_32wx40b;`
43			`-- pragma translate_on`
44
45			`entity umc_syncram is`
46			`generic ( abits : integer := 10; dbits : integer := 8 );`
47			`port (`
48			`clk : in std_ulogic;`
49			`address : in std_logic_vector(abits -1 downto 0);`
50			`datain : in std_logic_vector(dbits -1 downto 0);`
51			`dataout : out std_logic_vector(dbits -1 downto 0);`
52			`enable : in std_ulogic;`
53			`write : in std_ulogic`
54			`);`
55			`end;`
56
57			`architecture rtl of umc_syncram is`
58			`component SRAM_2048wx32b is`
59			`port (`
60			`a : in std_logic_vector(10 downto 0);`
61			`data : in std_logic_vector(31 downto 0);`
62			`csn : in std_logic;`
63			`wen : in std_logic;`
64			`oen : in std_logic;`
65			`q : out std_logic_vector(31 downto 0);`
66			`clk : in std_logic`
67			`);`
68			`end component;`
69
70			`component SRAM_1024wx32b is`
71			`port (`
72			`a : in std_logic_vector(9 downto 0);`
73			`data : in std_logic_vector(31 downto 0);`
74			`csn : in std_logic;`
75			`wen : in std_logic;`
76			`oen : in std_logic;`
77			`q : out std_logic_vector(31 downto 0);`
78			`clk : in std_logic`
79			`);`
80			`end component;`
81
82			`component SRAM_512wx32b is`
83			`port (`
84			`a : in std_logic_vector(8 downto 0);`
85			`data : in std_logic_vector(31 downto 0);`
86			`csn : in std_logic;`
87			`wen : in std_logic;`
88			`oen : in std_logic;`
89			`q : out std_logic_vector(31 downto 0);`
90			`clk : in std_logic`
91			`);`
92			`end component;`
93
94			`component SRAM_256wx32b is`
95			`port (`
96			`a : in std_logic_vector(7 downto 0);`
97			`data : in std_logic_vector(31 downto 0);`
98			`csn : in std_logic;`
99			`wen : in std_logic;`
100			`oen : in std_logic;`
101			`q : out std_logic_vector(31 downto 0);`
102			`clk : in std_logic`
103			`);`
104			`end component;`
105
106			`component SRAM_128wx32b is`
107			`port (`
108			`a : in std_logic_vector(6 downto 0);`
109			`data : in std_logic_vector(31 downto 0);`
110			`csn : in std_logic;`
111			`wen : in std_logic;`
112			`oen : in std_logic;`
113			`q : out std_logic_vector(31 downto 0);`
114			`clk : in std_logic`
115			`);`
116			`end component;`
117
118			`component SRAM_64wx32b is`
119			`port (`
120			`a : in std_logic_vector(5 downto 0);`
121			`data : in std_logic_vector(31 downto 0);`
122			`csn : in std_logic;`
123			`wen : in std_logic;`
124			`oen : in std_logic;`
125			`q : out std_logic_vector(31 downto 0);`
126			`clk : in std_logic`
127			`);`
128			`end component;`
129
130			`component SRAM_32wx32b is`
131			`port (`
132			`a : in std_logic_vector(4 downto 0);`
133			`data : in std_logic_vector(31 downto 0);`
134			`csn : in std_logic;`
135			`wen : in std_logic;`
136			`oen : in std_logic;`
137			`q : out std_logic_vector(31 downto 0);`
138			`clk : in std_logic`
139			`);`
140			`end component;`
141
142			`component SRAM_2048wx40b is`
143			`port (`
144			`a : in std_logic_vector(10 downto 0);`
145			`data : in std_logic_vector(39 downto 0);`
146			`csn : in std_logic;`
147			`wen : in std_logic;`
148			`oen : in std_logic;`
149			`q : out std_logic_vector(39 downto 0);`
150			`clk : in std_logic`
151			`);`
152			`end component;`
153
154			`component SRAM_1024wx40b is`
155			`port (`
156			`a : in std_logic_vector(9 downto 0);`
157			`data : in std_logic_vector(39 downto 0);`
158			`csn : in std_logic;`
159			`wen : in std_logic;`
160			`oen : in std_logic;`
161			`q : out std_logic_vector(39 downto 0);`
162			`clk : in std_logic`
163			`);`
164			`end component;`
165
166			`component SRAM_512wx40b is`
167			`port (`
168			`a : in std_logic_vector(8 downto 0);`
169			`data : in std_logic_vector(39 downto 0);`
170			`csn : in std_logic;`
171			`wen : in std_logic;`
172			`oen : in std_logic;`
173			`q : out std_logic_vector(39 downto 0);`
174			`clk : in std_logic`
175			`);`
176			`end component;`
177
178			`component SRAM_256wx40b is`
179			`port (`
180			`a : in std_logic_vector(7 downto 0);`
181			`data : in std_logic_vector(39 downto 0);`
182			`csn : in std_logic;`
183			`wen : in std_logic;`
184			`oen : in std_logic;`
185			`q : out std_logic_vector(39 downto 0);`
186			`clk : in std_logic`
187			`);`
188			`end component;`
189
190			`component SRAM_128wx40b is`
191			`port (`
192			`a : in std_logic_vector(6 downto 0);`
193			`data : in std_logic_vector(39 downto 0);`
194			`csn : in std_logic;`
195			`wen : in std_logic;`
196			`oen : in std_logic;`
197			`q : out std_logic_vector(39 downto 0);`
198			`clk : in std_logic`
199			`);`
200			`end component;`
201
202			`component SRAM_64wx40b is`
203			`port (`
204			`a : in std_logic_vector(5 downto 0);`
205			`data : in std_logic_vector(39 downto 0);`
206			`csn : in std_logic;`
207			`wen : in std_logic;`
208			`oen : in std_logic;`
209			`q : out std_logic_vector(39 downto 0);`
210			`clk : in std_logic`
211			`);`
212			`end component;`
213
214			`component SRAM_32wx40b is`
215			`port (`
216			`a : in std_logic_vector(4 downto 0);`
217			`data : in std_logic_vector(39 downto 0);`
218			`csn : in std_logic;`
219			`wen : in std_logic;`
220			`oen : in std_logic;`
221			`q : out std_logic_vector(39 downto 0);`
222			`clk : in std_logic`
223			`);`
224			`end component;`
225
226			`signal d, q, gnd : std_logic_vector(41 downto 0);`
227			`signal a : std_logic_vector(17 downto 0);`
228			`signal vcc, csn, wen : std_ulogic;`
229			`constant synopsys_bug : std_logic_vector(41 downto 0) := (others => '0');`
230			`begin`
231
232			`csn <= not enable; wen <= not write;`
233			`gnd <= (others => '0'); vcc <= '1';`
234			`a(abits -1 downto 0) <= address;`
235			`d(dbits -1 downto 0) <= datain(dbits -1 downto 0);`
236			`a(17 downto abits) <= synopsys_bug(17 downto abits);`
237			`d(41 downto dbits) <= synopsys_bug(41 downto dbits);`
238			`dataout <= q(dbits -1 downto 0);`
239			`-- q(41 downto dbits) <= synopsys_bug(41 downto dbits);`
240
241			`d32 : if (dbits <= 32) generate`
242			`a5d32 : if (abits <= 5) generate`
243			`id0 : SRAM_32wx32b port map (a(4 downto 0), d(31 downto 0), csn,`
244			`wen, gnd(0), q(31 downto 0), clk);`
245			`end generate;`
246			`a6d32 : if (abits = 6) generate`
247			`id0 : SRAM_64wx32b port map (a(5 downto 0), d(31 downto 0), csn,`
248			`wen, gnd(0), q(31 downto 0), clk);`
249			`end generate;`
250			`a7d32 : if (abits = 7) generate`
251			`id0 : SRAM_128wx32b port map (a(6 downto 0), d(31 downto 0), csn,`
252			`wen, gnd(0), q(31 downto 0), clk);`
253			`end generate;`
254			`a8d32 : if (abits = 8) generate`
255			`id0 : SRAM_256wx32b port map (a(7 downto 0), d(31 downto 0), csn,`
256			`wen, gnd(0), q(31 downto 0), clk);`
257			`end generate;`
258			`a9d32 : if (abits = 9) generate`
259			`id0 : SRAM_512wx32b port map (a(8 downto 0), d(31 downto 0), csn,`
260			`wen, gnd(0), q(31 downto 0), clk);`
261			`end generate;`
262			`a10d32 : if (abits = 10) generate`
263			`id0 : SRAM_1024wx32b port map (a(9 downto 0), d(31 downto 0), csn,`
264			`wen, gnd(0), q(31 downto 0), clk);`
265			`end generate;`
266			`a11d32 : if (abits = 11) generate`
267			`id0 : SRAM_2048wx32b port map (a(10 downto 0), d(31 downto 0), csn,`
268			`wen, gnd(0), q(31 downto 0), clk);`
269			`end generate;`
270			`end generate;`
271
272			`d40 : if (dbits > 32) and (dbits <= 40) generate`
273			`a5d40 : if (abits <= 5) generate`
274			`id0 : SRAM_32wx40b port map (a(4 downto 0), d(39 downto 0), csn,`
275			`wen, gnd(0), q(39 downto 0), clk);`
276			`end generate;`
277			`a6d40 : if (abits = 6) generate`
278			`id0 : SRAM_64wx40b port map (a(5 downto 0), d(39 downto 0), csn,`
279			`wen, gnd(0), q(39 downto 0), clk);`
280			`end generate;`
281			`a7d40 : if (abits = 7) generate`
282			`id0 : SRAM_128wx40b port map (a(6 downto 0), d(39 downto 0), csn,`
283			`wen, gnd(0), q(39 downto 0), clk);`
284			`end generate;`
285			`a8d40 : if (abits = 8) generate`
286			`id0 : SRAM_256wx40b port map (a(7 downto 0), d(39 downto 0), csn,`
287			`wen, gnd(0), q(39 downto 0), clk);`
288			`end generate;`
289			`a9d40 : if (abits = 9) generate`
290			`id0 : SRAM_512wx40b port map (a(8 downto 0), d(39 downto 0), csn,`
291			`wen, gnd(0), q(39 downto 0), clk);`
292			`end generate;`
293			`a10d40 : if (abits = 10) generate`
294			`id0 : SRAM_1024wx40b port map (a(9 downto 0), d(39 downto 0), csn,`
295			`wen, gnd(0), q(39 downto 0), clk);`
296			`end generate;`
297			`a11d40 : if (abits = 11) generate`
298			`id0 : SRAM_2048wx40b port map (a(10 downto 0), d(39 downto 0), csn,`
299			`wen, gnd(0), q(39 downto 0), clk);`
300			`end generate;`
301			`end generate;`
302
303			`-- pragma translate_off`
304			`a_to_high : if (abits > 12) or (dbits > 40) generate`
305			`x : process`
306			`begin`
307			`assert false`
308			`report "Unsupported memory size (umc18)"`
309			`severity failure;`
310			`wait;`
311			`end process;`
312			`end generate;`
313			`-- pragma translate_on`
314
315			`end;`