OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [software/] [leon3/] [dsu3.c] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
 
2
#include "dsu3.h"
3
 
4
dsu3_tb_check(int dsuaddr)
5
{
6
    int i, tmp, atmp, k, j, histlen;
7
    unsigned int ahblen;
8
    int pat5 = 0x55555555;
9
    int patA = 0xAAAAAAAA;
10
    int err = 0;
11
    volatile int xtmp = 2;
12
    volatile int vtmp = 0;
13
 
14
    report_device(0x01004000);
15
 
16
    // check that AHB breakpoints work 
17
    /*
18
    *((volatile int *) (dsuaddr + DSU3_AHBCTRL)) = 0;
19
    *((volatile int *) (dsuaddr + DSU3_TIMETAG)) = 0;
20
    *((volatile int *) (dsuaddr + DSU3_AHBINDEX)) = 0;
21
    *((volatile int *) (dsuaddr + DSU3_AHBBPT1)) = (int) &xtmp;
22
    *((volatile int *) (dsuaddr + DSU3_AHBMSK1)) = -1;
23
    *((volatile int *) (dsuaddr + DSU3_AHBCTRL)) = 1;
24
    xtmp += 1;;
25
    if (*((volatile int *) (dsuaddr + DSU3_AHBCTRL))) fail (1);
26
    if ((*((volatile int *) (dsuaddr + DSU3_AHBBUF))) /= (int) &xtmp)
27
        fail (2);
28
    */
29
 
30
    *((volatile int *) (dsuaddr + DSU3_AHBCTRL)) = 0xffff0000;
31
    ahblen = *((volatile int *) (dsuaddr + DSU3_AHBCTRL));
32
    ahblen = (ahblen >> 14);
33
    if (ahblen) {
34
        check_tbuf(dsuaddr + DSU3_AHBBUF, ahblen+1);
35
    }
36
 
37
    *((volatile int *) (dsuaddr + DSU3_TBCTRL)) = 0x0000ffff;
38
    ahblen = *((volatile int *) (dsuaddr + DSU3_TBCTRL));
39
    if (ahblen) {
40
        check_tbuf(dsuaddr + DSU3_TBUF, ahblen+1);
41
    }
42
}
43
 
44
check_tbuf(int addr, int ahblen)
45
{
46
    long long patchk = 0x5555555555555555LL;
47
    long long patichk = 0xaaaaaaaaaaaaaaaaLL;
48
    int j, tmp, atmp;
49
 
50
        report_subtest(1);      // checker board test
51
        atmp = addr;
52
        j = 0;
53
        while (j < ahblen) {
54
            *((volatile long long *)(atmp)) = patchk;
55
            *((volatile long long *)(atmp+8)) = patchk;
56
            *((volatile long long *)(atmp+16)) = patichk;
57
            *((volatile long long *)(atmp+24)) = patichk;
58
            j += 32;
59
        }
60
        atmp = addr;
61
        j = 0;
62
        while (j < ahblen) {
63
            if (*((volatile long long *)(atmp)) != patchk) fail(j);
64
            if (*((volatile long long *)(atmp+8)) != patchk) fail(j);
65
            if (*((volatile long long *)(atmp+16)) != patichk) fail(j);
66
            if (*((volatile long long *)(atmp+24)) != patichk) fail(j);
67
            j += 32;
68
        }
69
        report_subtest(2);      // inverted checker board test
70
        atmp = addr;
71
        j = 0;
72
        while (j < ahblen) {
73
            *((volatile long long *)(atmp)) = patichk;
74
            *((volatile long long *)(atmp+8)) = patichk;
75
            *((volatile long long *)(atmp+16)) = patchk;
76
            *((volatile long long *)(atmp+24)) = patchk;
77
            j += 32;
78
        }
79
        atmp = addr;
80
        j = 0;
81
        while (j < ahblen) {
82
            if (*((volatile long long *)(atmp)) != patichk) fail(j);
83
            if (*((volatile long long *)(atmp+8)) != patichk) fail(j);
84
            if (*((volatile long long *)(atmp+16)) != patchk) fail(j);
85
            if (*((volatile long long *)(atmp+24)) != patchk) fail(j);
86
            j += 32;
87
        }
88
        report_subtest(3);      // check address decoder
89
        for (j=0; j<ahblen; j++) {
90
            atmp = addr + j*4;
91
            *((volatile int *)(atmp)) = atmp;
92
        }
93
        for (j=0; j<ahblen; j++) {
94
            atmp = addr + j*4;
95
            tmp = *((volatile int *) (atmp));
96
            if (tmp != atmp) fail(j);
97
        }
98
}
99
 
100
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.