OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [software/] [leon3/] [l2timers.c] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
#include "testmod.h"
2
 
3
struct timerreg {
4
    volatile unsigned int counter;              /* 0x0 */
5
    volatile unsigned int reload;               /* 0x4 */
6
    volatile unsigned int control;              /* 0x8 */
7
    volatile unsigned int wdog;                 /* 0xC */
8
};
9
 
10
struct l2timers {
11
    struct timerreg timer[2];
12
    volatile unsigned int scalercnt;            /* 0x00 */
13
    volatile unsigned int scalerload;           /* 0x04 */
14
};
15
 
16
#define IRQPEND 0x10
17
 
18
l2timers_test(int addr)
19
{
20
        struct l2timers *lr = (struct l2timers *) addr;
21
        extern volatile int irqtbl[];
22
        int i, j, pil, ntimers;
23
 
24
        report_device(0x04006000);
25
        ntimers = 2;
26
        lr->scalerload = -1;
27
        if (lr->scalercnt == lr->scalercnt) fail(1);
28
 
29
/* timer 1 test */
30
 
31
        lr->scalerload = 31;
32
        lr->scalercnt = 31;
33
        for (i=0; i<ntimers; i++) lr->timer[i].control = 0; // halt all timers
34
 
35
        /* test basic functions */
36
        for (i=0; i<ntimers; i++) {
37
            report_subtest(i);
38
            lr->timer[i].counter = 0;
39
            lr->timer[i].reload = 15;
40
            lr->timer[i].control = 0x6;
41
            if (lr->timer[i].counter != 15) fail(3); // check loading
42
            lr->timer[i].control = 0xf;
43
            for (j=14; j >= 0; j--) { while (lr->timer[i].counter != j) {}}
44
            while (lr->timer[i].counter != 15) {}
45
            lr->timer[i].control = 0;
46
        }
47
 
48
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.