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[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [pcores/] [myipif/] [hdl/] [vhdl/] [jpeg_dezigzag.vhd] - Blame information for rev 8

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------------------------------------------------------------------------------
-- Two shift registers are used, when nr1 is full and nr2  is empty
-- they are nr1 is mapped on nr2 in a reverse-zigzag order. Additionally
-- the "matrix" is transposed to compensate transponation of successional
-- the idct-core.
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg_dezigzag is
        port(
                Clk             : in std_logic;
                context_i: in std_logic_vector(3 downto 0);
                data_i  : in std_logic_vector(11 downto 0);
                reset_i : in std_logic;
 
                context_o: out std_logic_vector(3 downto 0);
                data_o  : out std_logic_vector(11 downto 0);
 
                -- flow control
                datavalid_i     : in std_logic;
                datavalid_o     : out std_logic;
                ready_i                 : in  std_logic;
                ready_o                 : out std_logic
        );
end entity jpeg_dezigzag;
 
 
 
 
 
architecture IMP of jpeg_dezigzag is
 
        type sr is array (0 to 63) of std_logic_vector(11 downto 0);
        signal sr_in, sr_out : sr := (others=>X"000");
        signal ce_in, ce_out : std_logic :='0';
        signal counter_in  : std_logic_vector(5 downto 0) :=(others=>'0');
        signal counter_out : std_logic_vector(5 downto 0) :=(others=>'0');
        signal do_copy, do_copy_D : std_logic :='0';
        signal stop_in,  stop_in_D  : std_logic :='0';
        signal stop_out, stop_out_D : std_logic :='1';
        signal stop_eoi_out, stop_eoi_out_D : std_logic := '1';
        signal context, context_D : std_logic_vector(3 downto 0) :=(others=>'0');
        signal eoi, eoi_D : std_logic :='0';
        signal eoi_hold, eoi_hold_D : std_logic :='0';
        signal ready, ready_D : std_logic :='1';
 
 
 
 
 
 
 
begin
 
 
 
ready_o         <= ready;
datavalid_o     <= (ce_out and not do_copy);
data_o          <= sr_out(0);
context_o       <= context;
 
process(ready, counter_in, do_copy)
begin
        ready_D <= ready;
        if (counter_in=63) then
                ready_D <='0';
        elsif(do_copy='1') then
                ready_D<='1';
        end if;
end process;
process(Clk)
begin
        if rising_edge(Clk) then
                if(reset_i='1') then
                        ready <='1';
                elsif ce_in='1' then
                        ready <= ready_D;
                end if;
        end if;
end process;
 
 
process(stop_eoi_out, counter_in, do_copy)
begin
        stop_eoi_out_D <= stop_eoi_out;
        if (counter_in=1) then
                stop_eoi_out_D <='1';
        elsif(do_copy='1') then
                stop_eoi_out_D<='0';
        end if;
end process;
process(Clk)
begin
        if rising_edge(Clk) then
                if(reset_i='1') then
                        stop_eoi_out <='1';
                elsif ce_in='1' then
                        stop_eoi_out <= stop_eoi_out_D;
                end if;
        end if;
end process;
 
 
 
-- handle the context
process(eoi, eoi_hold, context_i, counter_out, do_copy, stop_eoi_out)
begin
        eoi_D <= eoi;
        eoi_hold_D <= eoi_hold;
        if (context_i(3)='1' and do_copy='0' and stop_eoi_out='1') then
                eoi_hold_D <= '1';
        elsif(context_i(3)='1' and (do_copy='1' and stop_eoi_out='1')) then
                eoi_D <= '1';
                eoi_hold_D <= '0';
        elsif(context_i(3)='1' and stop_eoi_out='0') then
                eoi_D <= '1';
                eoi_hold_D <= '0';
        elsif(eoi_hold='1' and do_copy='1') then
                eoi_D <= '1';
                eoi_hold_D <= '0';
        end if;
        if (counter_out=63 and eoi='1') then
                eoi_D <= '0';
                eoi_hold_D <= '0';
        end if;
end process;
 
process(Clk)
begin
        if rising_edge(Clk) then
                eoi             <= eoi_D;
                eoi_hold <= eoi_hold_D;
                context <= '0' & '0' & context(1 downto 0);
                if counter_in=60 then
                        context_D <= context_i;
                end if;
                if do_copy='1' then
                        context <= context_D;
                end if;
 
                if reset_i='1' then
                        context <= (others=>'0');
                        eoi <='0';
                        eoi_hold <='0';
                elsif counter_out=63 and ce_out='1' then
                        context(3)      <= eoi;
                end if;
 
        end if;
end process;
 
 
 
 
 
-- SHIFT_IN
process(Clk)
begin
        if rising_edge(Clk) then
        if reset_i='1' then
                sr_in <= (others=>X"000");
                counter_in <= (others=>'0');
        elsif ce_in='1' and do_copy='0' then
                sr_in <= sr_in(1 to 63) & data_i;
                counter_in <= counter_in+1;
        end if;
        end if;
end process;
 
process(datavalid_i, stop_in, do_copy)
begin
        if datavalid_i='1' and stop_in='0' then
                ce_in <='1';
        elsif(do_copy='1') then
                ce_in <= '1';
        else
                ce_in <='0';
        end if;
end process;
 
process(counter_in, do_copy, ce_in)
begin
        stop_in_D <= stop_in;
        if(do_copy='1') then
                stop_in_D <= '0';
        elsif counter_in="111111" and ce_in='1' then
                stop_in_D <= '1';
        end if;
end process;
 
process(Clk)
begin
        if rising_edge(Clk) then
        if reset_i='1' then
                stop_in <= '0';
        else
                stop_in <= stop_in_D;
        end if;
        end if;
end process;
 
 
 
 
 
-- DO_COPY
process(stop_in, stop_out)
begin
        if stop_in ='1' and stop_out='1' then
                do_copy_D <= '1';
        else
                do_copy_D <= '0';
        end if;
end process;
process(Clk)
begin
        if rising_edge(Clk) then
                if(reset_i='1') then
                        do_copy <='0';
                else
                do_copy <= do_copy_D;
                end if;
        end if;
end process;
 
 
 
 
-- SHIFT_OUT
process(Clk)
begin
        if rising_edge(Clk) then
 
                if reset_i='1' then
                        sr_out <= (others=>X"000");
                        counter_out <= (others=>'0');
                elsif do_copy='1' then
 
--              -- do the Zig-Zag Mapping
--                      sr_out(00) <= sr_in(00);        
--                      sr_out(01) <= sr_in(01);        
--                      sr_out(02) <= sr_in(05);        
--                      sr_out(03) <= sr_in(06);        
--                      sr_out(04) <= sr_in(14);        
--                      sr_out(05) <= sr_in(15);        
--                      sr_out(06) <= sr_in(27);        
--                      sr_out(07) <= sr_in(28);        
--                      sr_out(08) <= sr_in(02);        
--                      sr_out(09) <= sr_in(04);        
--                      sr_out(10) <= sr_in(07);        
--                      sr_out(11) <= sr_in(13);        
--                      sr_out(12) <= sr_in(16);        
--                      sr_out(13) <= sr_in(26);        
--                      sr_out(14) <= sr_in(29);        
--                      sr_out(15) <= sr_in(42);        
--                      sr_out(16) <= sr_in(03);        
--                      sr_out(17) <= sr_in(08);        
--                      sr_out(18) <= sr_in(12);        
--                      sr_out(19) <= sr_in(17);        
--                      sr_out(20) <= sr_in(25);        
--                      sr_out(21) <= sr_in(30);        
--                      sr_out(22) <= sr_in(41);        
--                      sr_out(23) <= sr_in(43);        
--                      sr_out(24) <= sr_in(09);        
--                      sr_out(25) <= sr_in(11);        
--                      sr_out(26) <= sr_in(18);        
--                      sr_out(27) <= sr_in(24);        
--                      sr_out(28) <= sr_in(31);        
--                      sr_out(29) <= sr_in(40);        
--                      sr_out(30) <= sr_in(44);        
--                      sr_out(31) <= sr_in(53);        
--                      sr_out(32) <= sr_in(10);        
--                      sr_out(33) <= sr_in(19);        
--                      sr_out(34) <= sr_in(23);        
--                      sr_out(35) <= sr_in(32);        
--                      sr_out(36) <= sr_in(39);        
--                      sr_out(37) <= sr_in(45);        
--                      sr_out(38) <= sr_in(52);        
--                      sr_out(39) <= sr_in(54);        
--                      sr_out(40) <= sr_in(20);        
--                      sr_out(41) <= sr_in(22);        
--                      sr_out(42) <= sr_in(33);        
--                      sr_out(43) <= sr_in(38);        
--                      sr_out(44) <= sr_in(46);        
--                      sr_out(45) <= sr_in(51);        
--                      sr_out(46) <= sr_in(55);        
--                      sr_out(47) <= sr_in(60);        
--                      sr_out(48) <= sr_in(21);        
--                      sr_out(49) <= sr_in(34);        
--                      sr_out(50) <= sr_in(37);        
--                      sr_out(51) <= sr_in(47);        
--                      sr_out(52) <= sr_in(50);        
--                      sr_out(53) <= sr_in(56);        
--                      sr_out(54) <= sr_in(59);        
--                      sr_out(55) <= sr_in(61);        
--                      sr_out(56) <= sr_in(35);        
--                      sr_out(57) <= sr_in(36);        
--                      sr_out(58) <= sr_in(48);        
--                      sr_out(59) <= sr_in(49);        
--                      sr_out(60) <= sr_in(57);        
--                      sr_out(61) <= sr_in(58);        
--                      sr_out(62) <= sr_in(62);        
--                      sr_out(63) <= sr_in(63);        
                -- additionally transpose the inputx matrix
                -- to compensate the column-wise output of the successional idct-entity
                        sr_out(00) <= sr_in(00);
                        sr_out(08) <= sr_in(01);
                        sr_out(16) <= sr_in(05);
                        sr_out(24) <= sr_in(06);
                        sr_out(32) <= sr_in(14);
                        sr_out(40) <= sr_in(15);
                        sr_out(48) <= sr_in(27);
                        sr_out(56) <= sr_in(28);
                        sr_out(01) <= sr_in(02);
                        sr_out(09) <= sr_in(04);
                        sr_out(17) <= sr_in(07);
                        sr_out(25) <= sr_in(13);
                        sr_out(33) <= sr_in(16);
                        sr_out(41) <= sr_in(26);
                        sr_out(49) <= sr_in(29);
                        sr_out(57) <= sr_in(42);
                        sr_out(02) <= sr_in(03);
                        sr_out(10) <= sr_in(08);
                        sr_out(18) <= sr_in(12);
                        sr_out(26) <= sr_in(17);
                        sr_out(34) <= sr_in(25);
                        sr_out(42) <= sr_in(30);
                        sr_out(50) <= sr_in(41);
                        sr_out(58) <= sr_in(43);
                        sr_out(03) <= sr_in(09);
                        sr_out(11) <= sr_in(11);
                        sr_out(19) <= sr_in(18);
                        sr_out(27) <= sr_in(24);
                        sr_out(35) <= sr_in(31);
                        sr_out(43) <= sr_in(40);
                        sr_out(51) <= sr_in(44);
                        sr_out(59) <= sr_in(53);
                        sr_out(04) <= sr_in(10);
                        sr_out(12) <= sr_in(19);
                        sr_out(20) <= sr_in(23);
                        sr_out(28) <= sr_in(32);
                        sr_out(36) <= sr_in(39);
                        sr_out(44) <= sr_in(45);
                        sr_out(51) <= sr_in(52);
                        sr_out(60) <= sr_in(54);
                        sr_out(05) <= sr_in(20);
                        sr_out(13) <= sr_in(22);
                        sr_out(21) <= sr_in(33);
                        sr_out(29) <= sr_in(38);
                        sr_out(37) <= sr_in(46);
                        sr_out(45) <= sr_in(51);
                        sr_out(53) <= sr_in(55);
                        sr_out(61) <= sr_in(60);
                        sr_out(06) <= sr_in(21);
                        sr_out(14) <= sr_in(34);
                        sr_out(22) <= sr_in(37);
                        sr_out(30) <= sr_in(47);
                        sr_out(38) <= sr_in(50);
                        sr_out(46) <= sr_in(56);
                        sr_out(54) <= sr_in(59);
                        sr_out(62) <= sr_in(61);
                        sr_out(07) <= sr_in(35);
                        sr_out(15) <= sr_in(36);
                        sr_out(23) <= sr_in(48);
                        sr_out(31) <= sr_in(49);
                        sr_out(39) <= sr_in(57);
                        sr_out(47) <= sr_in(58);
                        sr_out(55) <= sr_in(62);
                        sr_out(63) <= sr_in(63);
                elsif ce_out='1' and do_copy='0' then
                        sr_out <= sr_out(1 to 63) & X"000";
                        counter_out <= counter_out+1;
                end if;
 
        end if;
end process;
 
 
process(ready_i, stop_out, do_copy)
begin
        if ready_i='1' and stop_out='0' then
                ce_out <='1';
        elsif(do_copy='1') then
                ce_out <= '1';
        else
                ce_out <='0';
        end if;
end process;
 
 
process(counter_out, do_copy, ce_out)
begin
        stop_out_D <= stop_out;
        if(do_copy='1') then
                stop_out_D <= '0';
        elsif counter_out="111111" and ce_out='1' then
                stop_out_D <= '1';
        end if;
end process;
 
 
process(Clk)
begin
        if rising_edge(Clk) then
        if reset_i='1' then
                stop_out <= '1';
        else
                stop_out <= stop_out_D;
        end if;
        end if;
end process;
 
 
end IMP;

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Subversion Repositories mjpeg-decoder

[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [pcores/] [myipif/] [hdl/] [vhdl/] [jpeg_dezigzag.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	2	smanz	`------------------------------------------------------------------------------`
2			`-- Two shift registers are used, when nr1 is full and nr2 is empty`
3			`-- they are nr1 is mapped on nr2 in a reverse-zigzag order. Additionally`
4			`-- the "matrix" is transposed to compensate transponation of successional`
5			`-- the idct-core.`
6			`------------------------------------------------------------------------------`
7
8			`library ieee;`
9			`use ieee.std_logic_1164.all;`
10			`use ieee.std_logic_arith.all;`
11			`use ieee.std_logic_unsigned.all;`
12
13
14			`entity jpeg_dezigzag is`
15			`port(`
16			`Clk : in std_logic;`
17			`context_i: in std_logic_vector(3 downto 0);`
18			`data_i : in std_logic_vector(11 downto 0);`
19			`reset_i : in std_logic;`
20
21			`context_o: out std_logic_vector(3 downto 0);`
22			`data_o : out std_logic_vector(11 downto 0);`
23
24			`-- flow control`
25			`datavalid_i : in std_logic;`
26			`datavalid_o : out std_logic;`
27			`ready_i : in std_logic;`
28			`ready_o : out std_logic`
29			`);`
30			`end entity jpeg_dezigzag;`
31
32
33
34
35
36			`architecture IMP of jpeg_dezigzag is`
37
38			`type sr is array (0 to 63) of std_logic_vector(11 downto 0);`
39			`signal sr_in, sr_out : sr := (others=>X"000");`
40			`signal ce_in, ce_out : std_logic :='0';`
41			`signal counter_in : std_logic_vector(5 downto 0) :=(others=>'0');`
42			`signal counter_out : std_logic_vector(5 downto 0) :=(others=>'0');`
43			`signal do_copy, do_copy_D : std_logic :='0';`
44			`signal stop_in, stop_in_D : std_logic :='0';`
45			`signal stop_out, stop_out_D : std_logic :='1';`
46			`signal stop_eoi_out, stop_eoi_out_D : std_logic := '1';`
47			`signal context, context_D : std_logic_vector(3 downto 0) :=(others=>'0');`
48			`signal eoi, eoi_D : std_logic :='0';`
49			`signal eoi_hold, eoi_hold_D : std_logic :='0';`
50			`signal ready, ready_D : std_logic :='1';`
51
52
53
54
55
56
57
58			`begin`
59
60
61
62			`ready_o <= ready;`
63			`datavalid_o <= (ce_out and not do_copy);`
64			`data_o <= sr_out(0);`
65			`context_o <= context;`
66
67			`process(ready, counter_in, do_copy)`
68			`begin`
69			`ready_D <= ready;`
70			`if (counter_in=63) then`
71			`ready_D <='0';`
72			`elsif(do_copy='1') then`
73			`ready_D<='1';`
74			`end if;`
75			`end process;`
76			`process(Clk)`
77			`begin`
78			`if rising_edge(Clk) then`
79			`if(reset_i='1') then`
80			`ready <='1';`
81			`elsif ce_in='1' then`
82			`ready <= ready_D;`
83			`end if;`
84			`end if;`
85			`end process;`
86
87
88			`process(stop_eoi_out, counter_in, do_copy)`
89			`begin`
90			`stop_eoi_out_D <= stop_eoi_out;`
91			`if (counter_in=1) then`
92			`stop_eoi_out_D <='1';`
93			`elsif(do_copy='1') then`
94			`stop_eoi_out_D<='0';`
95			`end if;`
96			`end process;`
97			`process(Clk)`
98			`begin`
99			`if rising_edge(Clk) then`
100			`if(reset_i='1') then`
101			`stop_eoi_out <='1';`
102			`elsif ce_in='1' then`
103			`stop_eoi_out <= stop_eoi_out_D;`
104			`end if;`
105			`end if;`
106			`end process;`
107
108
109
110			`-- handle the context`
111			`process(eoi, eoi_hold, context_i, counter_out, do_copy, stop_eoi_out)`
112			`begin`
113			`eoi_D <= eoi;`
114			`eoi_hold_D <= eoi_hold;`
115			`if (context_i(3)='1' and do_copy='0' and stop_eoi_out='1') then`
116			`eoi_hold_D <= '1';`
117			`elsif(context_i(3)='1' and (do_copy='1' and stop_eoi_out='1')) then`
118			`eoi_D <= '1';`
119			`eoi_hold_D <= '0';`
120			`elsif(context_i(3)='1' and stop_eoi_out='0') then`
121			`eoi_D <= '1';`
122			`eoi_hold_D <= '0';`
123			`elsif(eoi_hold='1' and do_copy='1') then`
124			`eoi_D <= '1';`
125			`eoi_hold_D <= '0';`
126			`end if;`
127			`if (counter_out=63 and eoi='1') then`
128			`eoi_D <= '0';`
129			`eoi_hold_D <= '0';`
130			`end if;`
131			`end process;`
132
133			`process(Clk)`
134			`begin`
135			`if rising_edge(Clk) then`
136			`eoi <= eoi_D;`
137			`eoi_hold <= eoi_hold_D;`
138			`context <= '0' & '0' & context(1 downto 0);`
139			`if counter_in=60 then`
140			`context_D <= context_i;`
141			`end if;`
142			`if do_copy='1' then`
143			`context <= context_D;`
144			`end if;`
145
146			`if reset_i='1' then`
147			`context <= (others=>'0');`
148			`eoi <='0';`
149			`eoi_hold <='0';`
150			`elsif counter_out=63 and ce_out='1' then`
151			`context(3) <= eoi;`
152			`end if;`
153
154			`end if;`
155			`end process;`
156
157
158
159
160
161			`-- SHIFT_IN`
162			`process(Clk)`
163			`begin`
164			`if rising_edge(Clk) then`
165			`if reset_i='1' then`
166			`sr_in <= (others=>X"000");`
167			`counter_in <= (others=>'0');`
168			`elsif ce_in='1' and do_copy='0' then`
169			`sr_in <= sr_in(1 to 63) & data_i;`
170			`counter_in <= counter_in+1;`
171			`end if;`
172			`end if;`
173			`end process;`
174
175			`process(datavalid_i, stop_in, do_copy)`
176			`begin`
177			`if datavalid_i='1' and stop_in='0' then`
178			`ce_in <='1';`
179			`elsif(do_copy='1') then`
180			`ce_in <= '1';`
181			`else`
182			`ce_in <='0';`
183			`end if;`
184			`end process;`
185
186			`process(counter_in, do_copy, ce_in)`
187			`begin`
188			`stop_in_D <= stop_in;`
189			`if(do_copy='1') then`
190			`stop_in_D <= '0';`
191			`elsif counter_in="111111" and ce_in='1' then`
192			`stop_in_D <= '1';`
193			`end if;`
194			`end process;`
195
196			`process(Clk)`
197			`begin`
198			`if rising_edge(Clk) then`
199			`if reset_i='1' then`
200			`stop_in <= '0';`
201			`else`
202			`stop_in <= stop_in_D;`
203			`end if;`
204			`end if;`
205			`end process;`
206
207
208
209
210
211			`-- DO_COPY`
212			`process(stop_in, stop_out)`
213			`begin`
214			`if stop_in ='1' and stop_out='1' then`
215			`do_copy_D <= '1';`
216			`else`
217			`do_copy_D <= '0';`
218			`end if;`
219			`end process;`
220			`process(Clk)`
221			`begin`
222			`if rising_edge(Clk) then`
223			`if(reset_i='1') then`
224			`do_copy <='0';`
225			`else`
226			`do_copy <= do_copy_D;`
227			`end if;`
228			`end if;`
229			`end process;`
230
231
232
233
234			`-- SHIFT_OUT`
235			`process(Clk)`
236			`begin`
237			`if rising_edge(Clk) then`
238
239			`if reset_i='1' then`
240			`sr_out <= (others=>X"000");`
241			`counter_out <= (others=>'0');`
242			`elsif do_copy='1' then`
243
244			`-- -- do the Zig-Zag Mapping`
245			`-- sr_out(00) <= sr_in(00);`
246			`-- sr_out(01) <= sr_in(01);`
247			`-- sr_out(02) <= sr_in(05);`
248			`-- sr_out(03) <= sr_in(06);`
249			`-- sr_out(04) <= sr_in(14);`
250	8	smanz	`-- sr_out(05) <= sr_in(15);`
251	2	smanz	`-- sr_out(06) <= sr_in(27);`
252			`-- sr_out(07) <= sr_in(28);`
253			`-- sr_out(08) <= sr_in(02);`
254			`-- sr_out(09) <= sr_in(04);`
255			`-- sr_out(10) <= sr_in(07);`
256			`-- sr_out(11) <= sr_in(13);`
257			`-- sr_out(12) <= sr_in(16);`
258			`-- sr_out(13) <= sr_in(26);`
259			`-- sr_out(14) <= sr_in(29);`
260			`-- sr_out(15) <= sr_in(42);`
261			`-- sr_out(16) <= sr_in(03);`
262			`-- sr_out(17) <= sr_in(08);`
263			`-- sr_out(18) <= sr_in(12);`
264			`-- sr_out(19) <= sr_in(17);`
265			`-- sr_out(20) <= sr_in(25);`
266			`-- sr_out(21) <= sr_in(30);`
267			`-- sr_out(22) <= sr_in(41);`
268			`-- sr_out(23) <= sr_in(43);`
269			`-- sr_out(24) <= sr_in(09);`
270			`-- sr_out(25) <= sr_in(11);`
271			`-- sr_out(26) <= sr_in(18);`
272			`-- sr_out(27) <= sr_in(24);`
273			`-- sr_out(28) <= sr_in(31);`
274			`-- sr_out(29) <= sr_in(40);`
275			`-- sr_out(30) <= sr_in(44);`
276			`-- sr_out(31) <= sr_in(53);`
277			`-- sr_out(32) <= sr_in(10);`
278			`-- sr_out(33) <= sr_in(19);`
279			`-- sr_out(34) <= sr_in(23);`
280			`-- sr_out(35) <= sr_in(32);`
281			`-- sr_out(36) <= sr_in(39);`
282			`-- sr_out(37) <= sr_in(45);`
283			`-- sr_out(38) <= sr_in(52);`
284			`-- sr_out(39) <= sr_in(54);`
285			`-- sr_out(40) <= sr_in(20);`
286			`-- sr_out(41) <= sr_in(22);`
287			`-- sr_out(42) <= sr_in(33);`
288			`-- sr_out(43) <= sr_in(38);`
289			`-- sr_out(44) <= sr_in(46);`
290			`-- sr_out(45) <= sr_in(51);`
291			`-- sr_out(46) <= sr_in(55);`
292			`-- sr_out(47) <= sr_in(60);`
293			`-- sr_out(48) <= sr_in(21);`
294			`-- sr_out(49) <= sr_in(34);`
295			`-- sr_out(50) <= sr_in(37);`
296			`-- sr_out(51) <= sr_in(47);`
297			`-- sr_out(52) <= sr_in(50);`
298			`-- sr_out(53) <= sr_in(56);`
299			`-- sr_out(54) <= sr_in(59);`
300			`-- sr_out(55) <= sr_in(61);`
301			`-- sr_out(56) <= sr_in(35);`
302			`-- sr_out(57) <= sr_in(36);`
303			`-- sr_out(58) <= sr_in(48);`
304			`-- sr_out(59) <= sr_in(49);`
305			`-- sr_out(60) <= sr_in(57);`
306			`-- sr_out(61) <= sr_in(58);`
307			`-- sr_out(62) <= sr_in(62);`
308			`-- sr_out(63) <= sr_in(63);`
309			`-- additionally transpose the inputx matrix`
310			`-- to compensate the column-wise output of the successional idct-entity`
311			`sr_out(00) <= sr_in(00);`
312			`sr_out(08) <= sr_in(01);`
313			`sr_out(16) <= sr_in(05);`
314			`sr_out(24) <= sr_in(06);`
315			`sr_out(32) <= sr_in(14);`
316	8	smanz	`sr_out(40) <= sr_in(15);`
317	2	smanz	`sr_out(48) <= sr_in(27);`
318			`sr_out(56) <= sr_in(28);`
319			`sr_out(01) <= sr_in(02);`
320			`sr_out(09) <= sr_in(04);`
321			`sr_out(17) <= sr_in(07);`
322			`sr_out(25) <= sr_in(13);`
323			`sr_out(33) <= sr_in(16);`
324			`sr_out(41) <= sr_in(26);`
325			`sr_out(49) <= sr_in(29);`
326			`sr_out(57) <= sr_in(42);`
327			`sr_out(02) <= sr_in(03);`
328			`sr_out(10) <= sr_in(08);`
329			`sr_out(18) <= sr_in(12);`
330			`sr_out(26) <= sr_in(17);`
331			`sr_out(34) <= sr_in(25);`
332			`sr_out(42) <= sr_in(30);`
333			`sr_out(50) <= sr_in(41);`
334			`sr_out(58) <= sr_in(43);`
335			`sr_out(03) <= sr_in(09);`
336			`sr_out(11) <= sr_in(11);`
337			`sr_out(19) <= sr_in(18);`
338			`sr_out(27) <= sr_in(24);`
339			`sr_out(35) <= sr_in(31);`
340			`sr_out(43) <= sr_in(40);`
341			`sr_out(51) <= sr_in(44);`
342			`sr_out(59) <= sr_in(53);`
343			`sr_out(04) <= sr_in(10);`
344			`sr_out(12) <= sr_in(19);`
345			`sr_out(20) <= sr_in(23);`
346			`sr_out(28) <= sr_in(32);`
347			`sr_out(36) <= sr_in(39);`
348			`sr_out(44) <= sr_in(45);`
349			`sr_out(51) <= sr_in(52);`
350			`sr_out(60) <= sr_in(54);`
351			`sr_out(05) <= sr_in(20);`
352			`sr_out(13) <= sr_in(22);`
353			`sr_out(21) <= sr_in(33);`
354			`sr_out(29) <= sr_in(38);`
355			`sr_out(37) <= sr_in(46);`
356			`sr_out(45) <= sr_in(51);`
357			`sr_out(53) <= sr_in(55);`
358			`sr_out(61) <= sr_in(60);`
359			`sr_out(06) <= sr_in(21);`
360			`sr_out(14) <= sr_in(34);`
361			`sr_out(22) <= sr_in(37);`
362			`sr_out(30) <= sr_in(47);`
363			`sr_out(38) <= sr_in(50);`
364			`sr_out(46) <= sr_in(56);`
365			`sr_out(54) <= sr_in(59);`
366			`sr_out(62) <= sr_in(61);`
367			`sr_out(07) <= sr_in(35);`
368			`sr_out(15) <= sr_in(36);`
369			`sr_out(23) <= sr_in(48);`
370			`sr_out(31) <= sr_in(49);`
371			`sr_out(39) <= sr_in(57);`
372			`sr_out(47) <= sr_in(58);`
373			`sr_out(55) <= sr_in(62);`
374			`sr_out(63) <= sr_in(63);`
375			`elsif ce_out='1' and do_copy='0' then`
376			`sr_out <= sr_out(1 to 63) & X"000";`
377			`counter_out <= counter_out+1;`
378			`end if;`
379
380			`end if;`
381			`end process;`
382
383
384			`process(ready_i, stop_out, do_copy)`
385			`begin`
386			`if ready_i='1' and stop_out='0' then`
387			`ce_out <='1';`
388			`elsif(do_copy='1') then`
389			`ce_out <= '1';`
390			`else`
391			`ce_out <='0';`
392			`end if;`
393			`end process;`
394
395
396			`process(counter_out, do_copy, ce_out)`
397			`begin`
398			`stop_out_D <= stop_out;`
399			`if(do_copy='1') then`
400			`stop_out_D <= '0';`
401			`elsif counter_out="111111" and ce_out='1' then`
402			`stop_out_D <= '1';`
403			`end if;`
404			`end process;`
405
406
407			`process(Clk)`
408			`begin`
409			`if rising_edge(Clk) then`
410			`if reset_i='1' then`
411			`stop_out <= '1';`
412			`else`
413			`stop_out <= stop_out_D;`
414			`end if;`
415			`end if;`
416			`end process;`
417
418
419			`end IMP;`