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[/] [myblaze/] [trunk/] [system/] [uart_test_top/] [SysTop.twr] - Blame information for rev 6

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Line No. Rev Author Line
1 6 rockee 
--------------------------------------------------------------------------------
2 
Release 10.1.03 Trace  (lin64)
3 
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
4 
 
5 
/home/daniel/Applications/Xilinx/10.1/ISE/bin/lin64/unwrapped/trce -ise
6 
/home/daniel/Sources/myblaze/system/uart_test_top/uart_test_top.ise -intstyle
7 
ise -v 3 -s 4 -xml SysTop SysTop.ncd -o SysTop.twr SysTop.pcf -ucf
8 
/home/daniel/Sources/myblaze/rtl/uart_test_top.ucf
9 
 
10 
Design file:              SysTop.ncd
11 
Physical constraint file: SysTop.pcf
12 
Device,package,speed:     xc3s500e,fg320,-4 (PRODUCTION 1.27 2008-01-09)
13 
Report level:             verbose report
14 
 
15 
Environment Variable      Effect
16 
--------------------      ------
17 
NONE                      No environment variables were set
18 
--------------------------------------------------------------------------------
19 
 
20 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
21 
   option. All paths that are not constrained will be reported in the
22 
   unconstrained paths section(s) of the report.
23 
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
24 
   a 50 Ohm transmission line loading model.  For the details of this model,
25 
   and for more information on accounting for different loading conditions,
26 
   please see the device datasheet.
27 
 
28 
================================================================================
29 
Timing constraint: TS_clock = PERIOD TIMEGRP "clock" 20 ns HIGH 50%;
30 
 
31 
 247273 paths analyzed, 1947 endpoints analyzed, 0 failing endpoints
32 
 
33 
 Minimum period is  17.967ns.
34 
--------------------------------------------------------------------------------
35 
Slack:                  2.033ns (requirement - (data path - clock path skew + uncertainty))
36 
  Source:               Mram_dmem_bank_3_ram.B (RAM)
37 
  Destination:          core_exeu_ex_r_carry (FF)
38 
  Requirement:          20.000ns
39 
  Data Path Delay:      17.967ns (Levels of Logic = 22)
40 
  Clock Path Skew:      0.000ns
41 
  Source Clock:         clock_BUFGP rising at 0.000ns
42 
  Destination Clock:    clock_BUFGP rising at 20.000ns
43 
  Clock Uncertainty:    0.000ns
44 
 
45 
  Maximum Data Path: Mram_dmem_bank_3_ram.B to core_exeu_ex_r_carry
46 
    Location             Delay type         Delay(ns)  Physical Resource
47 
                                                       Logical Resource(s)
48 
    -------------------------------------------------  -------------------
49 
    RAMB16_X1Y6.DOB2     Tbcko                 2.812   Mram_dmem_bank_3_ram
50 
                                                       Mram_dmem_bank_3_ram.B
51 
    SLICE_X54Y45.F1      net (fanout=3)        1.099   dmem_bank_out<3><2>
52 
    SLICE_X54Y45.X       Tilo                  0.759   N274
53 
                                                       core_deco_wb_dat_d<2>17_SW0
54 
    SLICE_X54Y44.G1      net (fanout=1)        0.438   N274
55 
    SLICE_X54Y44.Y       Tilo                  0.759   core_of_fwd_mem_result<2>
56 
                                                       core_deco_wb_dat_d<2>17
57 
    SLICE_X54Y44.F4      net (fanout=1)        0.023   core_deco_wb_dat_d<2>17/O
58 
    SLICE_X54Y44.X       Tilo                  0.759   core_of_fwd_mem_result<2>
59 
                                                       core_deco_wb_dat_d<2>38
60 
    SLICE_X27Y50.F2      net (fanout=10)       2.532   SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store<2>
61 
    SLICE_X27Y50.X       Tif5x                 1.025   N342
62 
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G
63 
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0
64 
    SLICE_X39Y48.F1      net (fanout=1)        1.092   N342
65 
    SLICE_X39Y48.X       Tilo                  0.704   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
66 
                                                       _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
67 
    SLICE_X43Y45.G2      net (fanout=3)        0.944   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
68 
    SLICE_X43Y45.COUT    Topcyg                1.001   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<1>
69 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<3>
70 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
71 
    SLICE_X43Y46.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
72 
    SLICE_X43Y46.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<3>
73 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4>
74 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
75 
    SLICE_X43Y47.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
76 
    SLICE_X43Y47.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<5>
77 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6>
78 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
79 
    SLICE_X43Y48.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
80 
    SLICE_X43Y48.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<7>
81 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8>
82 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
83 
    SLICE_X43Y49.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
84 
    SLICE_X43Y49.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<9>
85 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10>
86 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
87 
    SLICE_X43Y50.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
88 
    SLICE_X43Y50.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<11>
89 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12>
90 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
91 
    SLICE_X43Y51.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
92 
    SLICE_X43Y51.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<13>
93 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14>
94 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
95 
    SLICE_X43Y52.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
96 
    SLICE_X43Y52.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<15>
97 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16>
98 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
99 
    SLICE_X43Y53.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
100 
    SLICE_X43Y53.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<17>
101 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18>
102 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
103 
    SLICE_X43Y54.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
104 
    SLICE_X43Y54.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<19>
105 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20>
106 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
107 
    SLICE_X43Y55.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
108 
    SLICE_X43Y55.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<21>
109 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22>
110 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>
111 
    SLICE_X43Y56.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>
112 
    SLICE_X43Y56.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<23>
113 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<24>
114 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>
115 
    SLICE_X43Y57.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>
116 
    SLICE_X43Y57.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<25>
117 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<26>
118 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>
119 
    SLICE_X43Y58.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>
120 
    SLICE_X43Y58.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<27>
121 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<28>
122 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>
123 
    SLICE_X43Y59.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>
124 
    SLICE_X43Y59.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<29>
125 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<30>
126 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<31>
127 
    SLICE_X43Y60.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<31>
128 
    SLICE_X43Y60.XB      Tcinxb                0.404   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<31>
129 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<32>
130 
    SLICE_X36Y53.F1      net (fanout=1)        1.072   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<32>
131 
    SLICE_X36Y53.CLK     Tfck                  0.892   core_exeu_ex_r_carry
132 
                                                       _old_SYSTOP_CORE_EXEU_COMB_r_carry_57
133 
                                                       core_exeu_ex_r_carry
134 
    -------------------------------------------------  ---------------------------
135 
    Total                                     17.967ns (10.767ns logic, 7.200ns route)
136 
                                                       (59.9% logic, 40.1% route)
137 
 
138 
--------------------------------------------------------------------------------
139 
Slack:                  2.160ns (requirement - (data path - clock path skew + uncertainty))
140 
  Source:               Mram_dmem_bank_3_ram.B (RAM)
141 
  Destination:          core_exeu_ex_r_alu_result_30 (FF)
142 
  Requirement:          20.000ns
143 
  Data Path Delay:      17.828ns (Levels of Logic = 21)
144 
  Clock Path Skew:      -0.012ns (0.075 - 0.087)
145 
  Source Clock:         clock_BUFGP rising at 0.000ns
146 
  Destination Clock:    clock_BUFGP rising at 20.000ns
147 
  Clock Uncertainty:    0.000ns
148 
 
149 
  Maximum Data Path: Mram_dmem_bank_3_ram.B to core_exeu_ex_r_alu_result_30
150 
    Location             Delay type         Delay(ns)  Physical Resource
151 
                                                       Logical Resource(s)
152 
    -------------------------------------------------  -------------------
153 
    RAMB16_X1Y6.DOB2     Tbcko                 2.812   Mram_dmem_bank_3_ram
154 
                                                       Mram_dmem_bank_3_ram.B
155 
    SLICE_X54Y45.F1      net (fanout=3)        1.099   dmem_bank_out<3><2>
156 
    SLICE_X54Y45.X       Tilo                  0.759   N274
157 
                                                       core_deco_wb_dat_d<2>17_SW0
158 
    SLICE_X54Y44.G1      net (fanout=1)        0.438   N274
159 
    SLICE_X54Y44.Y       Tilo                  0.759   core_of_fwd_mem_result<2>
160 
                                                       core_deco_wb_dat_d<2>17
161 
    SLICE_X54Y44.F4      net (fanout=1)        0.023   core_deco_wb_dat_d<2>17/O
162 
    SLICE_X54Y44.X       Tilo                  0.759   core_of_fwd_mem_result<2>
163 
                                                       core_deco_wb_dat_d<2>38
164 
    SLICE_X27Y50.F2      net (fanout=10)       2.532   SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store<2>
165 
    SLICE_X27Y50.X       Tif5x                 1.025   N342
166 
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G
167 
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0
168 
    SLICE_X39Y48.F1      net (fanout=1)        1.092   N342
169 
    SLICE_X39Y48.X       Tilo                  0.704   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
170 
                                                       _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
171 
    SLICE_X43Y45.G2      net (fanout=3)        0.944   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
172 
    SLICE_X43Y45.COUT    Topcyg                1.001   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<1>
173 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<3>
174 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
175 
    SLICE_X43Y46.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
176 
    SLICE_X43Y46.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<3>
177 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4>
178 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
179 
    SLICE_X43Y47.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
180 
    SLICE_X43Y47.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<5>
181 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6>
182 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
183 
    SLICE_X43Y48.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
184 
    SLICE_X43Y48.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<7>
185 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8>
186 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
187 
    SLICE_X43Y49.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
188 
    SLICE_X43Y49.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<9>
189 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10>
190 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
191 
    SLICE_X43Y50.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
192 
    SLICE_X43Y50.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<11>
193 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12>
194 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
195 
    SLICE_X43Y51.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
196 
    SLICE_X43Y51.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<13>
197 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14>
198 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
199 
    SLICE_X43Y52.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
200 
    SLICE_X43Y52.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<15>
201 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16>
202 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
203 
    SLICE_X43Y53.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
204 
    SLICE_X43Y53.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<17>
205 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18>
206 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
207 
    SLICE_X43Y54.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
208 
    SLICE_X43Y54.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<19>
209 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20>
210 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
211 
    SLICE_X43Y55.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
212 
    SLICE_X43Y55.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<21>
213 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22>
214 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>
215 
    SLICE_X43Y56.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>
216 
    SLICE_X43Y56.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<23>
217 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<24>
218 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>
219 
    SLICE_X43Y57.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>
220 
    SLICE_X43Y57.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<25>
221 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<26>
222 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>
223 
    SLICE_X43Y58.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>
224 
    SLICE_X43Y58.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<27>
225 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<28>
226 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>
227 
    SLICE_X43Y59.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>
228 
    SLICE_X43Y59.Y       Tciny                 0.869   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<29>
229 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<30>
230 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_xor<31>
231 
    SLICE_X40Y62.F3      net (fanout=1)        0.586   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<30>
232 
    SLICE_X40Y62.CLK     Tfck                  0.892   core_exeu_ex_r_alu_result<30>
233 
                                                       _old_SYSTOP_CORE_EXEU_COMB_result_53<30>63
234 
                                                       core_exeu_ex_r_alu_result_30
235 
    -------------------------------------------------  ---------------------------
236 
    Total                                     17.828ns (11.114ns logic, 6.714ns route)
237 
                                                       (62.3% logic, 37.7% route)
238 
 
239 
--------------------------------------------------------------------------------
240 
Slack:                  2.225ns (requirement - (data path - clock path skew + uncertainty))
241 
  Source:               Mram_dmem_bank_3_ram.B (RAM)
242 
  Destination:          core_exeu_ex_r_alu_result_22 (FF)
243 
  Requirement:          20.000ns
244 
  Data Path Delay:      17.753ns (Levels of Logic = 17)
245 
  Clock Path Skew:      -0.022ns (0.065 - 0.087)
246 
  Source Clock:         clock_BUFGP rising at 0.000ns
247 
  Destination Clock:    clock_BUFGP rising at 20.000ns
248 
  Clock Uncertainty:    0.000ns
249 
 
250 
  Maximum Data Path: Mram_dmem_bank_3_ram.B to core_exeu_ex_r_alu_result_22
251 
    Location             Delay type         Delay(ns)  Physical Resource
252 
                                                       Logical Resource(s)
253 
    -------------------------------------------------  -------------------
254 
    RAMB16_X1Y6.DOB2     Tbcko                 2.812   Mram_dmem_bank_3_ram
255 
                                                       Mram_dmem_bank_3_ram.B
256 
    SLICE_X54Y45.F1      net (fanout=3)        1.099   dmem_bank_out<3><2>
257 
    SLICE_X54Y45.X       Tilo                  0.759   N274
258 
                                                       core_deco_wb_dat_d<2>17_SW0
259 
    SLICE_X54Y44.G1      net (fanout=1)        0.438   N274
260 
    SLICE_X54Y44.Y       Tilo                  0.759   core_of_fwd_mem_result<2>
261 
                                                       core_deco_wb_dat_d<2>17
262 
    SLICE_X54Y44.F4      net (fanout=1)        0.023   core_deco_wb_dat_d<2>17/O
263 
    SLICE_X54Y44.X       Tilo                  0.759   core_of_fwd_mem_result<2>
264 
                                                       core_deco_wb_dat_d<2>38
265 
    SLICE_X27Y50.F2      net (fanout=10)       2.532   SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store<2>
266 
    SLICE_X27Y50.X       Tif5x                 1.025   N342
267 
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G
268 
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0
269 
    SLICE_X39Y48.F1      net (fanout=1)        1.092   N342
270 
    SLICE_X39Y48.X       Tilo                  0.704   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
271 
                                                       _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
272 
    SLICE_X43Y45.G2      net (fanout=3)        0.944   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
273 
    SLICE_X43Y45.COUT    Topcyg                1.001   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<1>
274 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<3>
275 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
276 
    SLICE_X43Y46.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
277 
    SLICE_X43Y46.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<3>
278 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4>
279 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
280 
    SLICE_X43Y47.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
281 
    SLICE_X43Y47.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<5>
282 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6>
283 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
284 
    SLICE_X43Y48.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
285 
    SLICE_X43Y48.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<7>
286 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8>
287 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
288 
    SLICE_X43Y49.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
289 
    SLICE_X43Y49.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<9>
290 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10>
291 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
292 
    SLICE_X43Y50.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
293 
    SLICE_X43Y50.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<11>
294 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12>
295 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
296 
    SLICE_X43Y51.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
297 
    SLICE_X43Y51.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<13>
298 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14>
299 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
300 
    SLICE_X43Y52.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
301 
    SLICE_X43Y52.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<15>
302 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16>
303 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
304 
    SLICE_X43Y53.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
305 
    SLICE_X43Y53.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<17>
306 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18>
307 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
308 
    SLICE_X43Y54.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
309 
    SLICE_X43Y54.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<19>
310 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20>
311 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
312 
    SLICE_X43Y55.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
313 
    SLICE_X43Y55.Y       Tciny                 0.869   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<21>
314 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22>
315 
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_xor<23>
316 
    SLICE_X44Y60.F2      net (fanout=1)        0.983   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<22>
317 
    SLICE_X44Y60.CLK     Tfck                  0.892   core_exeu_ex_r_alu_result<22>
318 
                                                       _old_SYSTOP_CORE_EXEU_COMB_result_53<22>63
319 
                                                       core_exeu_ex_r_alu_result_22
320 
    -------------------------------------------------  ---------------------------
321 
    Total                                     17.753ns (10.642ns logic, 7.111ns route)
322 
                                                       (59.9% logic, 40.1% route)
323 
 
324 
--------------------------------------------------------------------------------
325 
 
326 
 
327 
All constraints were met.
328 
 
329 
 
330 
Data Sheet report:
331 
-----------------
332 
All values displayed in nanoseconds (ns)
333 
 
334 
Clock to Setup on destination clock clock
335 
---------------+---------+---------+---------+---------+
336 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
337 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
338 
---------------+---------+---------+---------+---------+
339 
clock          |   17.967|         |         |         |
340 
---------------+---------+---------+---------+---------+
341 
 
342 
 
343 
Timing summary:
344 
---------------
345 
 
346 
Timing errors: 0  Score: 0
347 
 
348 
Constraints cover 247273 paths, 0 nets, and 5595 connections
349 
 
350 
Design statistics:
351 
   Minimum period:  17.967ns{1}   (Maximum frequency:  55.658MHz)
352 
 
353 
 
354 
------------------------------------Footnotes-----------------------------------
355 
1)  The minimum period statistic assumes all single cycle delays.
356 
 
357 
Analysis completed Sun Nov 21 23:39:25 2010
358 
--------------------------------------------------------------------------------
359 
 
360 
Trace Settings:
361 
-------------------------
362 
Trace Settings
363 
 
364 
Peak Memory Usage: 248 MB
365 
 
366 
 
367 
 

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