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-- Title : ONFI compliant NAND interface
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-- File : nand_master.vhd
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-- Author : Alexey Lyashko <pradd@opencores.org>
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-- License : LGPL
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-- Description:
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-- The nand_master entity is the topmost entity of this ONFi (Open NAND Flash interface <http://www.onfi.org>)
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-- compliant NAND flash controller. It provides very simple interface and short and easy to use
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-- set of commands.
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-- It is important to mention, that the controller takes care of delays and proper NAND command
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-- sequences. See documentation for further details.
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-------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.onfi.all;
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entity nand_master is
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port
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(
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-- System clock
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clk : in std_logic;
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-- NAND chip control hardware interface. These signals should be bound to physical pins.
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nand_cle : out std_logic := '0';
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nand_ale : out std_logic := '0';
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nand_nwe : out std_logic := '1';
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nand_nwp : out std_logic := '0';
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nand_nce : out std_logic := '1';
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nand_nre : out std_logic := '1';
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nand_rnb : in std_logic;
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-- NAND chip data hardware interface. These signals should be boiund to physical pins.
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nand_data : inout std_logic_vector(15 downto 0);
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-- Component interface
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nreset : in std_logic;
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data_out : out std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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busy : out std_logic := '0';
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activate : in std_logic;
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cmd_in : in std_logic_vector(7 downto 0)
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);
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end nand_master;
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-- Structural architecture of the NAND_MASTER component.
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architecture struct of nand_master is
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-- Latch Unit.
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-- This component implements NAND's address and command latch interfaces.
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component latch_unit
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generic(latch_type : latch_t);
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port(
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activate,
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clk : in std_logic;
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data_in : in std_logic_vector(15 downto 0);
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latch_ctrl,
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write_enable,
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busy : out std_logic;
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data_out : out std_logic_vector(15 downto 0)
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);
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end component;
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-- Latch unit related signals
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signal cle_activate : std_logic;
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signal cle_latch_ctrl : std_logic;
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signal cle_write_enable : std_logic;
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signal cle_busy : std_logic;
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signal cle_data_in : std_logic_vector(15 downto 0);
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signal cle_data_out : std_logic_vector(15 downto 0);
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signal ale_activate : std_logic;
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signal ale_latch_ctrl : std_logic;
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signal ale_write_enable : std_logic;
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signal ale_busy : std_logic;
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signal ale_data_in : std_logic_vector(15 downto 0);
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signal ale_data_out : std_logic_vector(15 downto 0);
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-- IO Unit.
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-- This component implements NAND's read/write interfaces.
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component io_unit
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generic (io_type : io_t);
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port(
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activate,
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clk : in std_logic;
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data_in : in std_logic_vector(15 downto 0);
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io_ctrl,
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busy : out std_logic;
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data_out : out std_logic_vector(15 downto 0)
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);
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end component;
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-- IO Unit related signals
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signal io_rd_activate : std_logic;
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signal io_rd_io_ctrl : std_logic;
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signal io_rd_busy : std_logic;
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signal io_rd_data_in : std_logic_vector(15 downto 0);
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signal io_rd_data_out : std_logic_vector(15 downto 0);
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signal io_wr_activate : std_logic;
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signal io_wr_io_ctrl : std_logic;
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signal io_wr_busy : std_logic;
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signal io_wr_data_in : std_logic_vector(15 downto 0);
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signal io_wr_data_out : std_logic_vector(15 downto 0);
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-- FSM
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signal state : master_state_t := M_RESET;
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signal n_state : master_state_t := M_RESET;
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signal substate : master_substate_t := MS_BEGIN;
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signal n_substate : master_substate_t := MS_BEGIN;
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signal delay : integer := 0;
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signal byte_count : integer := 0;
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signal page_idx : integer := 0;
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signal page_data : page_t;
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signal page_param : param_page_t;
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signal chip_id : nand_id_t;
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signal current_address : nand_address_t;
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signal data_bytes_per_page : integer;
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signal oob_bytes_per_page : integer;
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signal addr_cycles : integer;
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signal state_switch : states_t :=
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(
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1 => M_NAND_RESET,
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2 => M_NAND_READ_PARAM_PAGE,
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3 => M_NAND_READ_ID,
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4 => M_NAND_BLOCK_ERASE,
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5 => M_NAND_READ_STATUS,
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6 => M_NAND_READ,
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7 => M_NAND_PAGE_PROGRAM,
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8 => MI_GET_STATUS,
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9 => MI_CHIP_ENABLE,
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10 => MI_CHIP_DISABLE,
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11 => MI_WRITE_PROTECT,
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12 => MI_WRITE_ENABLE,
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13 => MI_RESET_INDEX,
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14 => MI_GET_ID_BYTE,
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15 => MI_GET_PARAM_PAGE_BYTE,
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16 => MI_GET_DATA_PAGE_BYTE,
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17 => MI_SET_DATA_PAGE_BYTE,
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18 => MI_GET_CURRENT_ADDRESS_BYTE,
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19 => MI_SET_CURRENT_ADDRESS_BYTE,
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others => M_IDLE
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);
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-- The following is a sort of a status register. Bit set to 1 means TRUE, bit set to 0 means FALSE:
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-- 0 - is ONFI compliant
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-- 1 - bus width (0 - x8 / 1 - x16)
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-- 2 - is chip enabled
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-- 3 - is chip write protected
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-- 4 - array pointer out of bounds
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-- 5 -
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-- 6 -
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-- 7 -
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signal status : std_logic_vector(7 downto 0) := x"00";
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begin
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-- Asynchronous command latch interface.
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ACL: latch_unit
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generic map (latch_type => LATCH_CMD)
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port map
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(
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activate => cle_activate,
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latch_ctrl => cle_latch_ctrl,
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write_enable => cle_write_enable,
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busy => cle_busy,
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clk => clk,
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data_in => cle_data_in,
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data_out => cle_data_out
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);
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-- Asynchronous address latch interface.
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AAL: latch_unit
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generic map (latch_type => LATCH_ADDR)
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port map
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(
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activate => ale_activate,
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latch_ctrl => ale_latch_ctrl,
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write_enable => ale_write_enable,
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busy => ale_busy,
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clk => clk,
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data_in => ale_data_in,
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data_out => ale_data_out
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);
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-- Output to NAND
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IO_WR: io_unit
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generic map (io_type => IO_WRITE)
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port map
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(
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clk => clk,
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activate => io_wr_activate,
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data_in => io_wr_data_in,
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data_out => io_wr_data_out,
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io_ctrl => io_wr_io_ctrl,
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busy => io_wr_busy
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);
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-- Input from NAND
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IO_RD: io_unit
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generic map (io_type => IO_READ)
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port map
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(
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clk => clk,
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activate => io_rd_activate,
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data_in => io_rd_data_in,
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data_out => io_rd_data_out,
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io_ctrl => io_rd_io_ctrl,
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busy => io_rd_busy
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);
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-- Busy indicator
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busy <= '0' when state = M_IDLE else
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'1';
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-- Bidirection NAND data interface.
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--nand_data <= (cle_data_out or ale_data_out or io_wr_data_out) when (cle_busy or ale_busy or io_wr_busy) = '1' else x"ZZZZ";
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nand_data <= cle_data_out when cle_busy = '1' else
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ale_data_out when ale_busy = '1' else
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io_wr_data_out when io_wr_busy = '1' else
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"ZZZZZZZZZZZZZZZZ";
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io_rd_data_in <= nand_data;
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-- Command Latch Enable
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nand_cle <= cle_latch_ctrl;
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-- Address Latch Enable
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nand_ale <= ale_latch_ctrl;
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-- Write Enable
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nand_nwe <= cle_write_enable and ale_write_enable and io_wr_io_ctrl;
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-- Read Enable
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nand_nre <= io_rd_io_ctrl;
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-- Activation of command latch unit
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cle_activate <= '1' when state = M_NAND_RESET or -- initiate submission of RESET command
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(state = M_NAND_READ_PARAM_PAGE and substate = MS_BEGIN) or -- initiate submission of READ PARAMETER PAGE command
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(state = M_NAND_BLOCK_ERASE and substate = MS_BEGIN) or -- initiate submission of BLOCK ERASE command
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(state = M_NAND_BLOCK_ERASE and substate = MS_SUBMIT_COMMAND1) or -- initiate submission of BLOCK ERASE 2 command
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(state = M_NAND_READ_STATUS and substate = MS_BEGIN) or -- initiate submission of READ STATUS command
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(state = M_NAND_READ and substate = MS_BEGIN) or -- initiate read mode for READ command
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(state = M_NAND_READ and substate = MS_SUBMIT_COMMAND1) or -- initiate submission of READ command
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(state = M_NAND_PAGE_PROGRAM and substate = MS_BEGIN) or -- initiate write mode for PAGE PROGRAM command
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(state = M_NAND_PAGE_PROGRAM and substate = MS_SUBMIT_COMMAND1) or -- initiate submission for PAGE PROGRAM command
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(state = M_NAND_READ_ID and substate = MS_BEGIN) else -- initiate submission of READ ID command
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'0';
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-- Activation of address latch unit
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ale_activate <= '1' when (state = M_NAND_READ_PARAM_PAGE and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for READ PARAMETER PAGE command
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(state = M_NAND_BLOCK_ERASE and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for BLOCK ERASE command
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(state = M_NAND_READ and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for READ command
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(state = M_NAND_PAGE_PROGRAM and substate = MS_SUBMIT_ADDRESS) or -- initiate address submission for PAGE PROGRAM command
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(state = M_NAND_READ_ID and substate = MS_SUBMIT_COMMAND) else -- initiate address submission for READ ID command
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'0';
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-- Activation of read byte mechanism
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io_rd_activate <= '1' when (state = M_NAND_READ_PARAM_PAGE and substate = MS_READ_DATA0) or -- initiate byte read for READ PARAMETER PAGE command
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(state = M_NAND_READ_STATUS and substate = MS_READ_DATA0) or -- initiate byte read for READ STATUS command
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(state = M_NAND_READ and substate = MS_READ_DATA0) or -- initiate byte read for READ command
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(state = M_NAND_READ_ID and substate = MS_READ_DATA0) else -- initiate byte read for READ ID command
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'0';
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-- Activation of write byte mechanism
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io_wr_activate <= '1' when (state = M_NAND_PAGE_PROGRAM and substate = MS_WRITE_DATA3) else -- initiate byte write for PAGE_PROGRAM command
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'0';
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MASTER: process(clk, nreset, activate, cmd_in, data_in, state_switch)
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variable tmp_int : std_logic_vector(31 downto 0);
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variable tmp : integer;
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begin
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if(nreset = '0')then
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state <= M_RESET;
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-- elsif(activate = '1')then
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-- state <= state_switch(to_integer(unsigned(cmd_in)));
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elsif(rising_edge(clk))then
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case state is
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-- RESET state. Speaks for itself
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when M_RESET =>
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state <= M_IDLE;
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substate <= MS_BEGIN;
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delay <= 0;
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byte_count <= 0;
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page_idx <= 0;
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current_address(0)<= x"00";
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current_address(1)<= x"00";
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current_address(2)<= x"00";
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current_address(3)<= x"00";
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current_address(4)<= x"00";
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data_bytes_per_page <= 0;
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oob_bytes_per_page <= 0;
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addr_cycles <= 0;
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status <= x"08"; -- We start write protected!
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nand_nce <= '1';
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nand_nwp <= '0';
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-- This is in fact a command interpreter
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when M_IDLE =>
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if(activate = '1')then
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state <= state_switch(to_integer(unsigned(cmd_in)));
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end if;
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-- Reset the NAND chip
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when M_NAND_RESET =>
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cle_data_in <= x"00ff";
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state <= M_WAIT;
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n_state <= M_IDLE;
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when MI_GET_STATUS =>
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data_out <= status;
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state <= M_IDLE;
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when MI_CHIP_ENABLE =>
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nand_nce <= '0';
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state <= M_IDLE;
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|
|
status(2) <= '1';
|
| 324 |
|
|
|
| 325 |
|
|
when MI_CHIP_DISABLE =>
|
| 326 |
|
|
nand_nce <= '1';
|
| 327 |
|
|
state <= M_IDLE;
|
| 328 |
|
|
status(2) <= '0';
|
| 329 |
|
|
|
| 330 |
|
|
when MI_WRITE_PROTECT =>
|
| 331 |
|
|
nand_nwp <= '0';
|
| 332 |
|
|
status(3) <= '1';
|
| 333 |
|
|
state <= M_IDLE;
|
| 334 |
|
|
|
| 335 |
|
|
when MI_WRITE_ENABLE =>
|
| 336 |
|
|
nand_nwp <= '1';
|
| 337 |
|
|
status(3) <= '0';
|
| 338 |
|
|
state <= M_IDLE;
|
| 339 |
|
|
|
| 340 |
|
|
when MI_RESET_INDEX =>
|
| 341 |
|
|
page_idx <= 0;
|
| 342 |
|
|
state <= M_IDLE;
|
| 343 |
|
|
|
| 344 |
|
|
when MI_GET_ID_BYTE =>
|
| 345 |
|
|
if(page_idx < 5)then
|
| 346 |
|
|
data_out <= chip_id(page_idx);
|
| 347 |
|
|
page_idx <= page_idx + 1;
|
| 348 |
|
|
status(4) <= '0';
|
| 349 |
|
|
else
|
| 350 |
|
|
data_out <= x"00";
|
| 351 |
|
|
page_idx <= 0;
|
| 352 |
|
|
status(4) <= '1';
|
| 353 |
|
|
end if;
|
| 354 |
|
|
state <= M_IDLE;
|
| 355 |
|
|
|
| 356 |
|
|
when MI_GET_PARAM_PAGE_BYTE =>
|
| 357 |
|
|
if(page_idx < 256)then
|
| 358 |
|
|
data_out <= page_param(page_idx);
|
| 359 |
|
|
page_idx <= page_idx + 1;
|
| 360 |
|
|
status(4) <= '0';
|
| 361 |
|
|
else
|
| 362 |
|
|
data_out <= x"00";
|
| 363 |
|
|
page_idx <= 0;
|
| 364 |
|
|
status(4) <= '1';
|
| 365 |
|
|
end if;
|
| 366 |
|
|
state <= M_IDLE;
|
| 367 |
|
|
|
| 368 |
|
|
when MI_GET_DATA_PAGE_BYTE =>
|
| 369 |
|
|
if(page_idx < data_bytes_per_page + oob_bytes_per_page)then
|
| 370 |
|
|
data_out <= page_data(page_idx);
|
| 371 |
|
|
page_idx <= page_idx + 1;
|
| 372 |
|
|
status(4) <= '0';
|
| 373 |
|
|
else
|
| 374 |
|
|
data_out <= x"00";
|
| 375 |
|
|
page_idx <= 0;
|
| 376 |
|
|
status(4) <= '1';
|
| 377 |
|
|
end if;
|
| 378 |
|
|
state <= M_IDLE;
|
| 379 |
|
|
|
| 380 |
|
|
when MI_SET_DATA_PAGE_BYTE =>
|
| 381 |
|
|
if(page_idx < data_bytes_per_page + oob_bytes_per_page)then
|
| 382 |
|
|
page_data(page_idx) <= data_in;
|
| 383 |
|
|
page_idx <= page_idx + 1;
|
| 384 |
|
|
status(4) <= '0';
|
| 385 |
|
|
else
|
| 386 |
|
|
page_idx <= 0;
|
| 387 |
|
|
status(4) <= '1';
|
| 388 |
|
|
end if;
|
| 389 |
|
|
state <= M_IDLE;
|
| 390 |
|
|
|
| 391 |
|
|
when MI_GET_CURRENT_ADDRESS_BYTE =>
|
| 392 |
|
|
if(page_idx < addr_cycles)then
|
| 393 |
|
|
data_out <= current_address(page_idx);
|
| 394 |
|
|
page_idx <= page_idx + 1;
|
| 395 |
|
|
status(4) <= '0';
|
| 396 |
|
|
else
|
| 397 |
|
|
page_idx <= 0;
|
| 398 |
|
|
status(4) <= '1';
|
| 399 |
|
|
end if;
|
| 400 |
|
|
state <= M_IDLE;
|
| 401 |
|
|
|
| 402 |
|
|
when MI_SET_CURRENT_ADDRESS_BYTE =>
|
| 403 |
|
|
if(page_idx < addr_cycles)then
|
| 404 |
|
|
current_address(page_idx) <= data_in;
|
| 405 |
|
|
page_idx <= page_idx + 1;
|
| 406 |
|
|
status(4) <= '0';
|
| 407 |
|
|
else
|
| 408 |
|
|
page_idx <= 0;
|
| 409 |
|
|
status(4) <= '1';
|
| 410 |
|
|
end if;
|
| 411 |
|
|
state <= M_IDLE;
|
| 412 |
|
|
|
| 413 |
|
|
-- Program one page.
|
| 414 |
|
|
when M_NAND_PAGE_PROGRAM =>
|
| 415 |
|
|
if(substate = MS_BEGIN)then
|
| 416 |
|
|
cle_data_in <= x"0080";
|
| 417 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 418 |
|
|
state <= M_WAIT;
|
| 419 |
|
|
n_state <= M_NAND_PAGE_PROGRAM;
|
| 420 |
|
|
byte_count <= 0;
|
| 421 |
|
|
|
| 422 |
|
|
elsif(substate = MS_SUBMIT_COMMAND)then
|
| 423 |
|
|
byte_count <= byte_count + 1;
|
| 424 |
|
|
ale_data_in <= x"00"¤t_address(byte_count);
|
| 425 |
|
|
substate <= MS_SUBMIT_ADDRESS;
|
| 426 |
|
|
|
| 427 |
|
|
elsif(substate = MS_SUBMIT_ADDRESS)then
|
| 428 |
|
|
if(byte_count < addr_cycles)then
|
| 429 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 430 |
|
|
else
|
| 431 |
|
|
substate <= MS_WRITE_DATA0;
|
| 432 |
|
|
end if;
|
| 433 |
|
|
state <= M_WAIT;
|
| 434 |
|
|
n_state <= M_NAND_PAGE_PROGRAM;
|
| 435 |
|
|
|
| 436 |
|
|
elsif(substate = MS_WRITE_DATA0)then
|
| 437 |
|
|
delay <= t_adl;
|
| 438 |
|
|
state <= M_DELAY;
|
| 439 |
|
|
n_state <= M_NAND_PAGE_PROGRAM;
|
| 440 |
|
|
substate <= MS_WRITE_DATA1;
|
| 441 |
|
|
page_idx <= 0;
|
| 442 |
|
|
byte_count <= 0;
|
| 443 |
|
|
|
| 444 |
|
|
elsif(substate = MS_WRITE_DATA1)then
|
| 445 |
|
|
byte_count <= byte_count + 1;
|
| 446 |
|
|
page_idx <= page_idx + 1;
|
| 447 |
|
|
io_wr_data_in <= x"00"&page_data(page_idx);
|
| 448 |
|
|
if(status(1) = '0')then
|
| 449 |
|
|
substate <= MS_WRITE_DATA3;
|
| 450 |
|
|
else
|
| 451 |
|
|
substate <= MS_WRITE_DATA2;
|
| 452 |
|
|
end if;
|
| 453 |
|
|
|
| 454 |
|
|
elsif(substate = MS_WRITE_DATA2)then
|
| 455 |
|
|
page_idx <= page_idx + 1;
|
| 456 |
|
|
io_wr_data_in(15 downto 8) <= page_data(page_idx);
|
| 457 |
|
|
substate <= MS_WRITE_DATA3;
|
| 458 |
|
|
|
| 459 |
|
|
elsif(substate = MS_WRITE_DATA3)then
|
| 460 |
|
|
if(byte_count < data_bytes_per_page + oob_bytes_per_page)then
|
| 461 |
|
|
substate <= MS_WRITE_DATA1;
|
| 462 |
|
|
else
|
| 463 |
|
|
substate <= MS_SUBMIT_COMMAND1;
|
| 464 |
|
|
end if;
|
| 465 |
|
|
n_state <= M_NAND_PAGE_PROGRAM;
|
| 466 |
|
|
state <= M_WAIT;
|
| 467 |
|
|
|
| 468 |
|
|
elsif(substate = MS_SUBMIT_COMMAND1)then
|
| 469 |
|
|
cle_data_in <= x"0010";
|
| 470 |
|
|
n_state <= M_NAND_PAGE_PROGRAM;
|
| 471 |
|
|
state <= M_WAIT;
|
| 472 |
|
|
substate <= MS_WAIT;
|
| 473 |
|
|
|
| 474 |
|
|
elsif(substate = MS_WAIT)then
|
| 475 |
|
|
delay <= t_wb + t_prog;
|
| 476 |
|
|
state <= M_DELAY;
|
| 477 |
|
|
n_state <= M_NAND_PAGE_PROGRAM;
|
| 478 |
|
|
substate <= MS_END;
|
| 479 |
|
|
byte_count <= 0;
|
| 480 |
|
|
page_idx <= 0;
|
| 481 |
|
|
|
| 482 |
|
|
elsif(substate = MS_END)then
|
| 483 |
|
|
state <= M_WAIT;
|
| 484 |
|
|
n_state <= M_IDLE;
|
| 485 |
|
|
substate <= MS_BEGIN;
|
| 486 |
|
|
end if;
|
| 487 |
|
|
|
| 488 |
|
|
|
| 489 |
|
|
-- Reads single page into the buffer.
|
| 490 |
|
|
when M_NAND_READ =>
|
| 491 |
|
|
if(substate = MS_BEGIN)then
|
| 492 |
|
|
cle_data_in <= x"0000";
|
| 493 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 494 |
|
|
state <= M_WAIT;
|
| 495 |
|
|
n_state <= M_NAND_READ;
|
| 496 |
|
|
byte_count <= 0;
|
| 497 |
|
|
|
| 498 |
|
|
elsif(substate = MS_SUBMIT_COMMAND)then
|
| 499 |
|
|
byte_count <= byte_count + 1;
|
| 500 |
|
|
ale_data_in <= x"00"¤t_address(byte_count);
|
| 501 |
|
|
substate <= MS_SUBMIT_ADDRESS;
|
| 502 |
|
|
|
| 503 |
|
|
elsif(substate = MS_SUBMIT_ADDRESS)then
|
| 504 |
|
|
if(byte_count < addr_cycles)then
|
| 505 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 506 |
|
|
else
|
| 507 |
|
|
substate <= MS_SUBMIT_COMMAND1;
|
| 508 |
|
|
end if;
|
| 509 |
|
|
state <= M_WAIT;
|
| 510 |
|
|
n_state <= M_NAND_READ;
|
| 511 |
|
|
|
| 512 |
|
|
elsif(substate = MS_SUBMIT_COMMAND1)then
|
| 513 |
|
|
cle_data_in <= x"0030";
|
| 514 |
|
|
substate <= MS_DELAY;
|
| 515 |
|
|
state <= M_WAIT;
|
| 516 |
|
|
n_state <= M_NAND_READ;
|
| 517 |
|
|
|
| 518 |
|
|
elsif(substate = MS_DELAY)then
|
| 519 |
|
|
delay <= t_wb;
|
| 520 |
|
|
substate <= MS_READ_DATA0;
|
| 521 |
|
|
state <= M_DELAY;
|
| 522 |
|
|
n_state <= M_NAND_READ;
|
| 523 |
|
|
byte_count <= 0;
|
| 524 |
|
|
page_idx <= 0;
|
| 525 |
|
|
|
| 526 |
|
|
elsif(substate = MS_READ_DATA0)then
|
| 527 |
|
|
byte_count <= byte_count + 1;
|
| 528 |
|
|
n_state <= M_NAND_READ;
|
| 529 |
|
|
state <= M_WAIT;
|
| 530 |
|
|
substate <= MS_READ_DATA1;
|
| 531 |
|
|
|
| 532 |
|
|
elsif(substate = MS_READ_DATA1)then
|
| 533 |
|
|
page_data(page_idx) <= io_rd_data_out(7 downto 0);
|
| 534 |
|
|
page_idx <= page_idx + 1;
|
| 535 |
|
|
if(byte_count = data_bytes_per_page + oob_bytes_per_page and status(1) = '0')then
|
| 536 |
|
|
substate <= MS_END;
|
| 537 |
|
|
else
|
| 538 |
|
|
if(status(1) = '0')then
|
| 539 |
|
|
substate <= MS_READ_DATA0;
|
| 540 |
|
|
else
|
| 541 |
|
|
substate <= MS_READ_DATA2;
|
| 542 |
|
|
end if;
|
| 543 |
|
|
end if;
|
| 544 |
|
|
|
| 545 |
|
|
elsif(substate = MS_READ_DATA2)then
|
| 546 |
|
|
page_idx <= page_idx + 1;
|
| 547 |
|
|
page_data(page_idx) <= io_rd_data_out(15 downto 8);
|
| 548 |
|
|
if(byte_count = data_bytes_per_page + oob_bytes_per_page)then
|
| 549 |
|
|
substate <= MS_END;
|
| 550 |
|
|
else
|
| 551 |
|
|
substate <= MS_READ_DATA0;
|
| 552 |
|
|
end if;
|
| 553 |
|
|
|
| 554 |
|
|
elsif(substate = MS_END)then
|
| 555 |
|
|
substate <= MS_BEGIN;
|
| 556 |
|
|
state <= M_IDLE;
|
| 557 |
|
|
byte_count <= 0;
|
| 558 |
|
|
end if;
|
| 559 |
|
|
|
| 560 |
|
|
-- Read status byte
|
| 561 |
|
|
when M_NAND_READ_STATUS =>
|
| 562 |
|
|
if(substate = MS_BEGIN)then
|
| 563 |
|
|
cle_data_in <= x"0070";
|
| 564 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 565 |
|
|
state <= M_WAIT;
|
| 566 |
|
|
n_state <= M_NAND_READ_STATUS;
|
| 567 |
|
|
|
| 568 |
|
|
elsif(substate = MS_SUBMIT_COMMAND)then
|
| 569 |
|
|
delay <= t_whr;
|
| 570 |
|
|
substate <= MS_READ_DATA0;
|
| 571 |
|
|
state <= M_DELAY;
|
| 572 |
|
|
n_state <= M_NAND_READ_STATUS;
|
| 573 |
|
|
|
| 574 |
|
|
elsif(substate = MS_READ_DATA0)then
|
| 575 |
|
|
substate <= MS_READ_DATA1;
|
| 576 |
|
|
state <= M_WAIT;
|
| 577 |
|
|
n_state <= M_NAND_READ_STATUS;
|
| 578 |
|
|
|
| 579 |
|
|
elsif(substate = MS_READ_DATA1)then -- This is to make sure 'data_out' has valid data before 'busy' goes low.
|
| 580 |
|
|
data_out <= io_rd_data_out(7 downto 0);
|
| 581 |
|
|
state <= M_NAND_READ_STATUS;
|
| 582 |
|
|
substate <= MS_END;
|
| 583 |
|
|
|
| 584 |
|
|
elsif(substate = MS_END)then
|
| 585 |
|
|
substate <= MS_BEGIN;
|
| 586 |
|
|
state <= M_IDLE;
|
| 587 |
|
|
end if;
|
| 588 |
|
|
|
| 589 |
|
|
-- Erase block specified by current_address
|
| 590 |
|
|
when M_NAND_BLOCK_ERASE =>
|
| 591 |
|
|
if(substate = MS_BEGIN)then
|
| 592 |
|
|
cle_data_in <= x"0060";
|
| 593 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 594 |
|
|
state <= M_WAIT;
|
| 595 |
|
|
n_state <= M_NAND_BLOCK_ERASE;
|
| 596 |
|
|
byte_count <= 3; -- number of address bytes to submit
|
| 597 |
|
|
|
| 598 |
|
|
elsif(substate = MS_SUBMIT_COMMAND)then
|
| 599 |
|
|
byte_count <= byte_count - 1;
|
| 600 |
|
|
ale_data_in(15 downto 8) <= x"00";
|
| 601 |
|
|
ale_data_in(7 downto 0) <= current_address(5 - byte_count);
|
| 602 |
|
|
substate <= MS_SUBMIT_ADDRESS;
|
| 603 |
|
|
state <= M_WAIT;
|
| 604 |
|
|
n_state <= M_NAND_BLOCK_ERASE;
|
| 605 |
|
|
|
| 606 |
|
|
elsif(substate = MS_SUBMIT_ADDRESS)then
|
| 607 |
|
|
if(0 < byte_count)then
|
| 608 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 609 |
|
|
else
|
| 610 |
|
|
substate <= MS_SUBMIT_COMMAND1;
|
| 611 |
|
|
end if;
|
| 612 |
|
|
|
| 613 |
|
|
elsif(substate = MS_SUBMIT_COMMAND1)then
|
| 614 |
|
|
cle_data_in <= x"00d0";
|
| 615 |
|
|
substate <= MS_END;
|
| 616 |
|
|
state <= M_WAIT;
|
| 617 |
|
|
n_state <= M_NAND_BLOCK_ERASE;
|
| 618 |
|
|
|
| 619 |
|
|
elsif(substate = MS_END)then
|
| 620 |
|
|
n_state <= M_IDLE;
|
| 621 |
|
|
delay <= t_wb + t_bers;
|
| 622 |
|
|
state <= M_DELAY;
|
| 623 |
|
|
substate <= MS_BEGIN;
|
| 624 |
|
|
byte_count <= 0;
|
| 625 |
|
|
end if;
|
| 626 |
|
|
|
| 627 |
|
|
-- Read NAND chip JEDEC ID
|
| 628 |
|
|
when M_NAND_READ_ID =>
|
| 629 |
|
|
if(substate = MS_BEGIN)then
|
| 630 |
|
|
cle_data_in <= x"0090";
|
| 631 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 632 |
|
|
state <= M_WAIT;
|
| 633 |
|
|
n_state <= M_NAND_READ_ID;
|
| 634 |
|
|
|
| 635 |
|
|
elsif(substate = MS_SUBMIT_COMMAND)then
|
| 636 |
|
|
ale_data_in <= X"0000";
|
| 637 |
|
|
substate <= MS_SUBMIT_ADDRESS;
|
| 638 |
|
|
state <= M_WAIT;
|
| 639 |
|
|
n_state <= M_NAND_READ_ID;
|
| 640 |
|
|
|
| 641 |
|
|
elsif(substate = MS_SUBMIT_ADDRESS)then
|
| 642 |
|
|
delay <= t_wb;
|
| 643 |
|
|
state <= M_DELAY;
|
| 644 |
|
|
n_state <= M_NAND_READ_ID;
|
| 645 |
|
|
substate <= MS_READ_DATA0;
|
| 646 |
|
|
byte_count <= 5;
|
| 647 |
|
|
page_idx <= 0;
|
| 648 |
|
|
|
| 649 |
|
|
elsif(substate = MS_READ_DATA0)then
|
| 650 |
|
|
byte_count <= byte_count - 1;
|
| 651 |
|
|
state <= M_WAIT;
|
| 652 |
|
|
n_state <= M_NAND_READ_ID;
|
| 653 |
|
|
substate <= MS_READ_DATA1;
|
| 654 |
|
|
|
| 655 |
|
|
elsif(substate = MS_READ_DATA1)then
|
| 656 |
|
|
chip_id(page_idx) <= io_rd_data_out(7 downto 0);
|
| 657 |
|
|
if(0 < byte_count)then
|
| 658 |
|
|
page_idx <= page_idx + 1;
|
| 659 |
|
|
substate <= MS_READ_DATA0;
|
| 660 |
|
|
else
|
| 661 |
|
|
substate <= MS_END;
|
| 662 |
|
|
end if;
|
| 663 |
|
|
|
| 664 |
|
|
elsif(substate = MS_END)then
|
| 665 |
|
|
byte_count <= 0;
|
| 666 |
|
|
page_idx <= 0;
|
| 667 |
|
|
substate <= MS_BEGIN;
|
| 668 |
|
|
state <= M_IDLE;
|
| 669 |
|
|
end if;
|
| 670 |
|
|
|
| 671 |
|
|
-- *data_in is assigned one clock cycle after *_activate is triggered!!!!
|
| 672 |
|
|
-- According to ONFI's timing diagrams this should be normal, but who knows...
|
| 673 |
|
|
when M_NAND_READ_PARAM_PAGE =>
|
| 674 |
|
|
if(substate = MS_BEGIN)then
|
| 675 |
|
|
cle_data_in <= x"00ec";
|
| 676 |
|
|
substate <= MS_SUBMIT_COMMAND;
|
| 677 |
|
|
state <= M_WAIT;
|
| 678 |
|
|
n_state <= M_NAND_READ_PARAM_PAGE;
|
| 679 |
|
|
|
| 680 |
|
|
elsif(substate = MS_SUBMIT_COMMAND)then
|
| 681 |
|
|
ale_data_in <= X"0000";
|
| 682 |
|
|
substate <= MS_SUBMIT_ADDRESS;
|
| 683 |
|
|
state <= M_WAIT;
|
| 684 |
|
|
n_state <= M_NAND_READ_PARAM_PAGE;
|
| 685 |
|
|
|
| 686 |
|
|
elsif(substate = MS_SUBMIT_ADDRESS)then
|
| 687 |
|
|
delay <= t_wb;
|
| 688 |
|
|
state <= M_DELAY;
|
| 689 |
|
|
n_state <= M_NAND_READ_PARAM_PAGE;
|
| 690 |
|
|
substate <= MS_READ_DATA0;
|
| 691 |
|
|
byte_count <= 256;
|
| 692 |
|
|
page_idx <= 0;
|
| 693 |
|
|
|
| 694 |
|
|
elsif(substate = MS_READ_DATA0)then
|
| 695 |
|
|
byte_count <= byte_count - 1;
|
| 696 |
|
|
state <= M_WAIT;
|
| 697 |
|
|
n_state <= M_NAND_READ_PARAM_PAGE;
|
| 698 |
|
|
substate <= MS_READ_DATA1;
|
| 699 |
|
|
|
| 700 |
|
|
elsif(substate = MS_READ_DATA1)then
|
| 701 |
|
|
page_param(page_idx) <= io_rd_data_out(7 downto 0);
|
| 702 |
|
|
if(0 < byte_count)then
|
| 703 |
|
|
page_idx <= page_idx + 1;
|
| 704 |
|
|
substate <= MS_READ_DATA0;
|
| 705 |
|
|
else
|
| 706 |
|
|
substate <= MS_END;
|
| 707 |
|
|
end if;
|
| 708 |
|
|
|
| 709 |
|
|
elsif(substate = MS_END)then
|
| 710 |
|
|
byte_count <= 0;
|
| 711 |
|
|
page_idx <= 0;
|
| 712 |
|
|
substate <= MS_BEGIN;
|
| 713 |
|
|
state <= M_IDLE;
|
| 714 |
|
|
|
| 715 |
|
|
-- Check the chip for being ONFI compliant
|
| 716 |
|
|
if(page_param(0) = x"4f" and page_param(1) = x"4e" and page_param(2) = x"46" and page_param(3) = x"49")then
|
| 717 |
|
|
-- Set status bit 0
|
| 718 |
|
|
status(0) <= '1';
|
| 719 |
|
|
|
| 720 |
|
|
-- Bus width
|
| 721 |
|
|
status(1) <= page_param(6)(0);
|
| 722 |
|
|
|
| 723 |
|
|
-- Setup counters:
|
| 724 |
|
|
-- Number of bytes per page
|
| 725 |
|
|
tmp_int := page_param(83)&page_param(82)&page_param(81)&page_param(80);
|
| 726 |
|
|
data_bytes_per_page <= to_integer(unsigned(tmp_int));
|
| 727 |
|
|
|
| 728 |
|
|
-- Number of spare bytes per page (OOB)
|
| 729 |
|
|
tmp_int := "0000000000000000" & page_param(85) & page_param(84);
|
| 730 |
|
|
oob_bytes_per_page <= to_integer(unsigned(tmp_int));
|
| 731 |
|
|
|
| 732 |
|
|
-- Number of address cycles
|
| 733 |
|
|
addr_cycles <= to_integer(unsigned(page_param(101)(3 downto 0))) + to_integer(unsigned(page_param(101)(7 downto 4)));
|
| 734 |
|
|
end if;
|
| 735 |
|
|
end if;
|
| 736 |
|
|
|
| 737 |
|
|
-- Wait for latch and IO modules to become ready as well as for NAND's R/B# to be '1'
|
| 738 |
|
|
when M_WAIT =>
|
| 739 |
|
|
if('0' = (cle_busy or ale_busy or io_rd_busy or io_wr_busy or (not nand_rnb)))then
|
| 740 |
|
|
state <= n_state;
|
| 741 |
|
|
end if;
|
| 742 |
|
|
|
| 743 |
|
|
-- Simple delay mechanism
|
| 744 |
|
|
when M_DELAY =>
|
| 745 |
|
|
if(delay > 1)then
|
| 746 |
|
|
delay <= delay - 1;
|
| 747 |
|
|
else
|
| 748 |
|
|
state <= n_state;
|
| 749 |
|
|
end if;
|
| 750 |
|
|
|
| 751 |
|
|
-- For just in case ("Shit happens..." (C) Forrest Gump)
|
| 752 |
|
|
when others =>
|
| 753 |
|
|
state <= M_RESET;
|
| 754 |
|
|
end case;
|
| 755 |
|
|
end if;
|
| 756 |
|
|
end process;
|
| 757 |
|
|
end struct;
|
| 758 |
|
|
|
